[mirror_edk2.git] / OvmfPkg / PciHostBridgeDxe / PciHostBridge.c

/** @file\r
  Provides the basic interfaces to abstract a PCI Host Bridge Resource\r
  Allocation\r
\r
  Copyright (C) 2015, Red Hat, Inc.\r
  Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
\r
  This program and the accompanying materials are licensed and made available\r
  under the terms and conditions of the BSD License which accompanies this\r
  distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <Library/QemuFwCfgLib.h>\r
\r
#include "PciHostBridge.h"\r
\r
STATIC\r
CONST\r
EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {\r
  {\r
    {\r
      ACPI_DEVICE_PATH,\r
      ACPI_DP,\r
      {\r
        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r
        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)\r
      }\r
    },\r
    EISA_PNP_ID(0x0A03), // HID\r
    0                    // UID\r
  },\r
\r
  {\r
    END_DEVICE_PATH_TYPE,\r
    END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
    {\r
      END_DEVICE_PATH_LENGTH,\r
      0\r
    }\r
  }\r
};\r
\r
EFI_HANDLE mDriverImageHandle;\r
\r
PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {\r
  PCI_HOST_BRIDGE_SIGNATURE,  // Signature\r
  NULL,                       // HostBridgeHandle\r
  {NULL, NULL},               // Head\r
  FALSE,                      // ResourceSubiteed\r
  TRUE,                       // CanRestarted\r
  {\r
    NotifyPhase,\r
    GetNextRootBridge,\r
    GetAttributes,\r
    StartBusEnumeration,\r
    SetBusNumbers,\r
    SubmitResources,\r
    GetProposedResources,\r
    PreprocessController\r
  }\r
};\r
\r
//\r
// Implementation\r
//\r
\r
/**\r
  Allocate and initialize a root bridge.\r
\r
  param[in]  RootBusNumber     The bus number of the root bus (root bridge) to\r
                               create.\r
\r
  param[in]  MaxSubBusNumber   The inclusive maximum bus number that can be\r
                               assigned to any subordinate bus found behind any\r
                               PCI bridge hanging off this root bus.\r
\r
                               The caller is repsonsible for ensuring that\r
                               RootBusNumber <= MaxSubBusNumber. If\r
                               RootBusNumber equals MaxSubBusNumber, then the\r
                               root bus has no room for subordinate buses.\r
\r
  param[in]  HostBridgeHandle  The EFI_HANDLE corresponding to the host bridge\r
                               that is the parent of the root bridge to create.\r
                               HostBridgeHandle is expected to have\r
                               EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
                               installed on it.\r
\r
  param[out] RootBus           The private PCI_ROOT_BRIDGE_INSTANCE that has\r
                               been created as the result of the function call.\r
\r
  @retval EFI_SUCCESS           Initialization successful. A new\r
                                EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL has been\r
                                created as the child of HostBridgeHandle. A\r
                                device path consisting of an ACPI device path\r
                                node, with UID = RootBusNumber, has been\r
                                installed on the same new handle.\r
\r
  @retval EFI_OUT_OF_RESOURCES  Memory allocation failed.\r
\r
  @return                       Error codes from\r
                                gBS->InstallMultipleProtocolInterfaces().\r
**/\r
STATIC\r
EFI_STATUS\r
InitRootBridge (\r
  IN  UINT8                    RootBusNumber,\r
  IN  UINT8                    MaxSubBusNumber,\r
  IN  EFI_HANDLE               HostBridgeHandle,\r
  OUT PCI_ROOT_BRIDGE_INSTANCE **RootBus\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE          *PrivateData;\r
  PCI_ROOT_BRIDGE_RESOURCE_APERTURE ResAperture;\r
  EFI_STATUS                        Status;\r
\r
  ASSERT (RootBusNumber <= MaxSubBusNumber);\r
\r
  PrivateData = AllocateZeroPool (sizeof *PrivateData);\r
  if (PrivateData == NULL) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;\r
\r
  CopyMem (&PrivateData->DevicePath, &mRootBridgeDevicePathTemplate,\r
    sizeof mRootBridgeDevicePathTemplate);\r
  PrivateData->DevicePath.AcpiDevicePath.UID = RootBusNumber;\r
\r
  ResAperture.BusBase  = RootBusNumber;\r
  ResAperture.BusLimit = MaxSubBusNumber;\r
  ResAperture.MemBase  = BASE_2GB;\r
  ResAperture.MemLimit = BASE_4GB - 1;\r
  ResAperture.IoBase   = 0;\r
  ResAperture.IoLimit  = MAX_UINT16;\r
  //\r
  // The function call below allocates no resources and performs no actions\r
  // that have to be rolled back on later failure. It always succeeds.\r
  //\r
  Status = RootBridgeConstructor (&PrivateData->Io, HostBridgeHandle,\r
             EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM, &ResAperture);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Status = gBS->InstallMultipleProtocolInterfaces (&PrivateData->Handle,\r
                  &gEfiDevicePathProtocolGuid,      &PrivateData->DevicePath,\r
                  &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,\r
                  NULL);\r
  if (EFI_ERROR (Status)) {\r
    goto FreePrivateData;\r
  }\r
\r
  DEBUG ((EFI_D_INFO,\r
    "%a: installed root bus %d, with room for %d subordinate bus(es)\n",\r
    __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));\r
  *RootBus = PrivateData;\r
  return EFI_SUCCESS;\r
\r
FreePrivateData:\r
  FreePool (PrivateData);\r
  return Status;\r
}\r
\r
\r
/**\r
  Uninitialize and free a root bridge set up with InitRootBridge().\r
\r
  On return, the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance and the device path\r
  will have been released, freeing RootBus->Handle as well.\r
\r
  param[in] RootBus  The private PCI_ROOT_BRIDGE_INSTANCE that has been created\r
                     with InitRootBridge(), and should be released.\r
**/\r
STATIC\r
VOID\r
UninitRootBridge (\r
  IN PCI_ROOT_BRIDGE_INSTANCE *RootBus\r
  )\r
{\r
  EFI_STATUS Status;\r
\r
  Status = gBS->UninstallMultipleProtocolInterfaces (RootBus->Handle,\r
                  &gEfiDevicePathProtocolGuid,      &RootBus->DevicePath,\r
                  &gEfiPciRootBridgeIoProtocolGuid, &RootBus->Io,\r
                  NULL);\r
  ASSERT_EFI_ERROR (Status);\r
  FreePool (RootBus);\r
}\r
\r
\r
/**\r
  Entry point of this driver\r
\r
  @param ImageHandle     Handle of driver image\r
  @param SystemTable     Point to EFI_SYSTEM_TABLE\r
\r
  @retval EFI_OUT_OF_RESOURCES  Can not allocate memory resource\r
  @retval EFI_DEVICE_ERROR      Can not install the protocol instance\r
  @retval EFI_SUCCESS           Success to initialize the Pci host bridge.\r
**/\r
EFI_STATUS\r
EFIAPI\r
InitializePciHostBridge (\r
  IN EFI_HANDLE        ImageHandle,\r
  IN EFI_SYSTEM_TABLE  *SystemTable\r
  )\r
{\r
  EFI_STATUS                  Status;\r
  FIRMWARE_CONFIG_ITEM        FwCfgItem;\r
  UINTN                       FwCfgSize;\r
  UINT64                      ExtraRootBridgesLeft;\r
  UINTN                       LastRootBridgeNumber;\r
  UINTN                       RootBridgeNumber;\r
  PCI_HOST_BRIDGE_INSTANCE    *HostBridge;\r
  PCI_ROOT_BRIDGE_INSTANCE    *RootBus;\r
  EFI_STATUS                  UninstallStatus;\r
\r
  mDriverImageHandle = ImageHandle;\r
\r
  //\r
  // Create Host Bridge Device Handle\r
  //\r
  HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE),\r
                 &mPciHostBridgeInstanceTemplate);\r
  if (HostBridge == NULL) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  InitializeListHead (&HostBridge->Head);\r
\r
  Status = gBS->InstallMultipleProtocolInterfaces (\r
                  &HostBridge->HostBridgeHandle,\r
                  &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
                  &HostBridge->ResAlloc,\r
                  NULL\r
                  );\r
  if (EFI_ERROR (Status)) {\r
    goto FreeHostBridge;\r
  }\r
\r
  //\r
  // QEMU provides the number of extra root buses, shortening the exhaustive\r
  // search below. If there is no hint, the feature is missing.\r
  //\r
  Status = QemuFwCfgFindFile ("etc/extra-pci-roots", &FwCfgItem, &FwCfgSize);\r
  if (EFI_ERROR (Status) || FwCfgSize != sizeof ExtraRootBridgesLeft) {\r
    ExtraRootBridgesLeft = 0;\r
  } else {\r
    QemuFwCfgSelectItem (FwCfgItem);\r
    QemuFwCfgReadBytes (FwCfgSize, &ExtraRootBridgesLeft);\r
    DEBUG ((EFI_D_INFO, "%a: %Lu extra root buses reported by QEMU\n",\r
      __FUNCTION__, ExtraRootBridgesLeft));\r
  }\r
\r
  //\r
  // The "main" root bus is always there.\r
  //\r
  LastRootBridgeNumber = 0;\r
\r
  //\r
  // Scan all other root buses. If function 0 of any device on a bus returns a\r
  // VendorId register value different from all-bits-one, then that bus is\r
  // alive.\r
  //\r
  for (RootBridgeNumber = 1;\r
       RootBridgeNumber < 256 && ExtraRootBridgesLeft > 0;\r
       ++RootBridgeNumber) {\r
    UINTN Device;\r
\r
    for (Device = 0; Device <= MAX_PCI_DEVICE_NUMBER; ++Device) {\r
      if (PciRead16 (PCI_LIB_ADDRESS (RootBridgeNumber, Device, 0,\r
                       PCI_VENDOR_ID_OFFSET)) != MAX_UINT16) {\r
        break;\r
      }\r
    }\r
    if (Device <= MAX_PCI_DEVICE_NUMBER) {\r
      //\r
      // Found the next root bus. We can now install the *previous* one,\r
      // because now we know how big a bus number range *that* one has, for any\r
      // subordinate buses that might exist behind PCI bridges hanging off it.\r
      //\r
      Status = InitRootBridge ((UINT8)LastRootBridgeNumber,\r
                 (UINT8)(RootBridgeNumber - 1), HostBridge->HostBridgeHandle,\r
                 &RootBus);\r
      if (EFI_ERROR (Status)) {\r
        goto RollbackProtocols;\r
      }\r
      InsertTailList (&HostBridge->Head, &RootBus->Link);\r
      LastRootBridgeNumber = RootBridgeNumber;\r
      --ExtraRootBridgesLeft;\r
    }\r
  }\r
\r
  //\r
  // Install the last root bus (which might be the only, ie. main, root bus, if\r
  // we've found no extra root buses).\r
  //\r
  Status = InitRootBridge ((UINT8)LastRootBridgeNumber, 255,\r
             HostBridge->HostBridgeHandle, &RootBus);\r
  if (EFI_ERROR (Status)) {\r
    goto RollbackProtocols;\r
  }\r
  InsertTailList (&HostBridge->Head, &RootBus->Link);\r
\r
  return EFI_SUCCESS;\r
\r
RollbackProtocols:\r
  while (!IsListEmpty (&HostBridge->Head)) {\r
    LIST_ENTRY *Entry;\r
\r
    Entry = GetFirstNode (&HostBridge->Head);\r
    RemoveEntryList (Entry);\r
    RootBus = DRIVER_INSTANCE_FROM_LIST_ENTRY (Entry);\r
    UninitRootBridge (RootBus);\r
  }\r
  UninstallStatus = gBS->UninstallMultipleProtocolInterfaces (\r
                           HostBridge->HostBridgeHandle,\r
                           &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
                           &HostBridge->ResAlloc,\r
                           NULL\r
                           );\r
  ASSERT_EFI_ERROR (UninstallStatus);\r
\r
FreeHostBridge:\r
  FreePool (HostBridge);\r
\r
  return Status;\r
}\r
\r
\r
/**\r
  These are the notifications from the PCI bus driver that it is about to enter\r
  a certain phase of the PCI enumeration process.\r
\r
  This member function can be used to notify the host bridge driver to perform\r
  specific actions, including any chipset-specific initialization, so that the\r
  chipset is ready to enter the next phase. Eight notification points are\r
  defined at this time. See belows:\r
\r
  EfiPciHostBridgeBeginEnumeration       Resets the host bridge PCI apertures\r
                                         and internal data structures. The PCI\r
                                         enumerator should issue this\r
                                         notification before starting a fresh\r
                                         enumeration process. Enumeration\r
                                         cannot be restarted after sending any\r
                                         other notification such as\r
                                         EfiPciHostBridgeBeginBusAllocation.\r
\r
  EfiPciHostBridgeBeginBusAllocation     The bus allocation phase is about to\r
                                         begin. No specific action is required\r
                                         here. This notification can be used to\r
                                         perform any chipset-specific\r
                                         programming.\r
\r
  EfiPciHostBridgeEndBusAllocation       The bus allocation and bus programming\r
                                         phase is complete. No specific action\r
                                         is required here. This notification\r
                                         can be used to perform any\r
                                         chipset-specific programming.\r
\r
  EfiPciHostBridgeBeginResourceAllocation\r
                                         The resource allocation phase is about\r
                                         to begin. No specific action is\r
                                         required here. This notification can\r
                                         be used to perform any\r
                                         chipset-specific programming.\r
\r
  EfiPciHostBridgeAllocateResources      Allocates resources per previously\r
                                         submitted requests for all the PCI\r
                                         root bridges. These resource settings\r
                                         are returned on the next call to\r
                                         GetProposedResources(). Before calling\r
                                         NotifyPhase() with a Phase of\r
                                         EfiPciHostBridgeAllocateResource, the\r
                                         PCI bus enumerator is responsible for\r
                                         gathering I/O and memory requests for\r
                                         all the PCI root bridges and\r
                                         submitting these requests using\r
                                         SubmitResources(). This function pads\r
                                         the resource amount to suit the root\r
                                         bridge hardware, takes care of\r
                                         dependencies between the PCI root\r
                                         bridges, and calls the Global\r
                                         Coherency Domain (GCD) with the\r
                                         allocation request. In the case of\r
                                         padding, the allocated range could be\r
                                         bigger than what was requested.\r
\r
  EfiPciHostBridgeSetResources           Programs the host bridge hardware to\r
                                         decode previously allocated resources\r
                                         (proposed resources) for all the PCI\r
                                         root bridges. After the hardware is\r
                                         programmed, reassigning resources will\r
                                         not be supported. The bus settings are\r
                                         not affected.\r
\r
  EfiPciHostBridgeFreeResources          Deallocates resources that were\r
                                         previously allocated for all the PCI\r
                                         root bridges and resets the I/O and\r
                                         memory apertures to their initial\r
                                         state. The bus settings are not\r
                                         affected. If the request to allocate\r
                                         resources fails, the PCI enumerator\r
                                         can use this notification to\r
                                         deallocate previous resources, adjust\r
                                         the requests, and retry allocation.\r
\r
  EfiPciHostBridgeEndResourceAllocation  The resource allocation phase is\r
                                         completed. No specific action is\r
                                         required here. This notification can\r
                                         be used to perform any chipsetspecific\r
                                         programming.\r
\r
  @param[in] This                The instance pointer of\r
                               EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
\r
  @param[in] Phase               The phase during enumeration\r
\r
  @retval EFI_NOT_READY          This phase cannot be entered at this time. For\r
                                 example, this error is valid for a Phase of\r
                                 EfiPciHostBridgeAllocateResources if\r
                                 SubmitResources() has not been called for one\r
                                 or more PCI root bridges before this call\r
\r
  @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.\r
                                 This error is valid for a Phase of\r
                                 EfiPciHostBridgeSetResources.\r
\r
  @retval EFI_INVALID_PARAMETER  Invalid phase parameter\r
\r
  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a\r
                                 lack of resources. This error is valid for a\r
                                 Phase of EfiPciHostBridgeAllocateResources if\r
                                 the previously submitted resource requests\r
                                 cannot be fulfilled or were only partially\r
                                 fulfilled.\r
\r
  @retval EFI_SUCCESS            The notification was accepted without any\r
                                 errors.\r
**/\r
EFI_STATUS\r
EFIAPI\r
NotifyPhase(\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE    Phase\r
  )\r
{\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
  PCI_RESOURCE_TYPE                     Index;\r
  LIST_ENTRY                            *List;\r
  EFI_PHYSICAL_ADDRESS                  BaseAddress;\r
  UINT64                                AddrLen;\r
  UINTN                                 BitsOfAlignment;\r
  EFI_STATUS                            Status;\r
  EFI_STATUS                            ReturnStatus;\r
\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
\r
  switch (Phase) {\r
\r
  case EfiPciHostBridgeBeginEnumeration:\r
    if (HostBridgeInstance->CanRestarted) {\r
      //\r
      // Reset the Each Root Bridge\r
      //\r
      List = HostBridgeInstance->Head.ForwardLink;\r
\r
      while (List != &HostBridgeInstance->Head) {\r
        RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
        for (Index = TypeIo; Index < TypeMax; Index++) {\r
          RootBridgeInstance->ResAllocNode[Index].Type      = Index;\r
          RootBridgeInstance->ResAllocNode[Index].Base      = 0;\r
          RootBridgeInstance->ResAllocNode[Index].Length    = 0;\r
          RootBridgeInstance->ResAllocNode[Index].Status    = ResNone;\r
        }\r
\r
        List = List->ForwardLink;\r
      }\r
\r
      HostBridgeInstance->ResourceSubmited = FALSE;\r
      HostBridgeInstance->CanRestarted     = TRUE;\r
    } else {\r
      //\r
      // Can not restart\r
      //\r
      return EFI_NOT_READY;\r
    }\r
    break;\r
\r
  case EfiPciHostBridgeEndEnumeration:\r
    break;\r
\r
  case EfiPciHostBridgeBeginBusAllocation:\r
    //\r
    // No specific action is required here, can perform any chipset specific\r
    // programing\r
    //\r
    HostBridgeInstance->CanRestarted = FALSE;\r
    break;\r
\r
  case EfiPciHostBridgeEndBusAllocation:\r
    //\r
    // No specific action is required here, can perform any chipset specific\r
    // programing\r
    //\r
    //HostBridgeInstance->CanRestarted = FALSE;\r
    break;\r
\r
  case EfiPciHostBridgeBeginResourceAllocation:\r
    //\r
    // No specific action is required here, can perform any chipset specific\r
    // programing\r
    //\r
    //HostBridgeInstance->CanRestarted = FALSE;\r
    break;\r
\r
  case EfiPciHostBridgeAllocateResources:\r
    ReturnStatus = EFI_SUCCESS;\r
    if (HostBridgeInstance->ResourceSubmited) {\r
      //\r
      // Take care of the resource dependencies between the root bridges\r
      //\r
      List = HostBridgeInstance->Head.ForwardLink;\r
\r
      while (List != &HostBridgeInstance->Head) {\r
        RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
        for (Index = TypeIo; Index < TypeBus; Index++) {\r
          if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
\r
            AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
\r
            //\r
            // Get the number of '1' in Alignment.\r
            //\r
            BitsOfAlignment =\r
              (UINTN)(HighBitSet64 (\r
                        RootBridgeInstance->ResAllocNode[Index].Alignment\r
                        ) + 1);\r
\r
            switch (Index) {\r
\r
              case TypeIo:\r
                //\r
                // It is impossible for this chipset to align 0xFFFF for IO16\r
                // So clear it\r
                //\r
                if (BitsOfAlignment >= 16) {\r
                  BitsOfAlignment = 0;\r
                }\r
\r
                Status = gDS->AllocateIoSpace (\r
                                EfiGcdAllocateAnySearchBottomUp,\r
                                EfiGcdIoTypeIo,\r
                                BitsOfAlignment,\r
                                AddrLen,\r
                                &BaseAddress,\r
                                mDriverImageHandle,\r
                                NULL\r
                                );\r
\r
                if (!EFI_ERROR (Status)) {\r
                  RootBridgeInstance->ResAllocNode[Index].Base   =\r
                    (UINTN)BaseAddress;\r
                  RootBridgeInstance->ResAllocNode[Index].Status =\r
                    ResAllocated;\r
                } else {\r
                  ReturnStatus = Status;\r
                  if (Status != EFI_OUT_OF_RESOURCES) {\r
                    RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
                  }\r
                }\r
\r
                break;\r
\r
\r
              case TypeMem32:\r
                //\r
                // It is impossible for this chipset to align 0xFFFFFFFF for\r
                // Mem32\r
                // So clear it\r
                //\r
\r
                if (BitsOfAlignment >= 32) {\r
                  BitsOfAlignment = 0;\r
                }\r
\r
                Status = gDS->AllocateMemorySpace (\r
                                EfiGcdAllocateAnySearchBottomUp,\r
                                EfiGcdMemoryTypeMemoryMappedIo,\r
                                BitsOfAlignment,\r
                                AddrLen,\r
                                &BaseAddress,\r
                                mDriverImageHandle,\r
                                NULL\r
                                );\r
\r
                if (!EFI_ERROR (Status)) {\r
                  // We were able to allocate the PCI memory\r
                  RootBridgeInstance->ResAllocNode[Index].Base   =\r
                    (UINTN)BaseAddress;\r
                  RootBridgeInstance->ResAllocNode[Index].Status =\r
                    ResAllocated;\r
\r
                } else {\r
                  // Not able to allocate enough PCI memory\r
                  ReturnStatus = Status;\r
\r
                  if (Status != EFI_OUT_OF_RESOURCES) {\r
                    RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
                  }\r
                  ASSERT (FALSE);\r
                }\r
                break;\r
\r
              case TypePMem32:\r
              case TypeMem64:\r
              case TypePMem64:\r
                  ReturnStatus = EFI_ABORTED;\r
                  break;\r
              default:\r
                ASSERT (FALSE);\r
                break;\r
              }; //end switch\r
          }\r
        }\r
\r
        List = List->ForwardLink;\r
      }\r
\r
      return ReturnStatus;\r
\r
    } else {\r
      return EFI_NOT_READY;\r
    }\r
    break;\r
\r
  case EfiPciHostBridgeSetResources:\r
    break;\r
\r
  case EfiPciHostBridgeFreeResources:\r
    ReturnStatus = EFI_SUCCESS;\r
    List = HostBridgeInstance->Head.ForwardLink;\r
    while (List != &HostBridgeInstance->Head) {\r
      RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
      for (Index = TypeIo; Index < TypeBus; Index++) {\r
        if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {\r
          AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
          BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;\r
          switch (Index) {\r
\r
          case TypeIo:\r
            Status = gDS->FreeIoSpace (BaseAddress, AddrLen);\r
            if (EFI_ERROR (Status)) {\r
              ReturnStatus = Status;\r
            }\r
            break;\r
\r
          case TypeMem32:\r
            Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);\r
            if (EFI_ERROR (Status)) {\r
              ReturnStatus = Status;\r
            }\r
            break;\r
\r
          case TypePMem32:\r
            break;\r
\r
          case TypeMem64:\r
            break;\r
\r
          case TypePMem64:\r
            break;\r
\r
          default:\r
            ASSERT (FALSE);\r
            break;\r
\r
          }; //end switch\r
          RootBridgeInstance->ResAllocNode[Index].Type      = Index;\r
          RootBridgeInstance->ResAllocNode[Index].Base      = 0;\r
          RootBridgeInstance->ResAllocNode[Index].Length    = 0;\r
          RootBridgeInstance->ResAllocNode[Index].Status    = ResNone;\r
        }\r
      }\r
\r
      List = List->ForwardLink;\r
    }\r
\r
    HostBridgeInstance->ResourceSubmited = FALSE;\r
    HostBridgeInstance->CanRestarted     = TRUE;\r
    return ReturnStatus;\r
\r
  case EfiPciHostBridgeEndResourceAllocation:\r
    HostBridgeInstance->CanRestarted = FALSE;\r
    break;\r
\r
  default:\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Return the device handle of the next PCI root bridge that is associated with\r
  this Host Bridge.\r
\r
  This function is called multiple times to retrieve the device handles of all\r
  the PCI root bridges that are associated with this PCI host bridge. Each PCI\r
  host bridge is associated with one or more PCI root bridges. On each call,\r
  the handle that was returned by the previous call is passed into the\r
  interface, and on output the interface returns the device handle of the next\r
  PCI root bridge. The caller can use the handle to obtain the instance of the\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL for that root bridge. When there are no more\r
  PCI root bridges to report, the interface returns EFI_NOT_FOUND. A PCI\r
  enumerator must enumerate the PCI root bridges in the order that they are\r
  returned by this function.\r
\r
  For D945 implementation, there is only one root bridge in PCI host bridge.\r
\r
  @param[in]       This              The instance pointer of\r
                               EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
\r
  @param[in, out]  RootBridgeHandle  Returns the device handle of the next PCI\r
                                     root bridge.\r
\r
  @retval EFI_SUCCESS            If parameter RootBridgeHandle = NULL, then\r
                                 return the first Rootbridge handle of the\r
                                 specific Host bridge and return EFI_SUCCESS.\r
\r
  @retval EFI_NOT_FOUND          Can not find the any more root bridge in\r
                                 specific host bridge.\r
\r
  @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not an EFI_HANDLE that was\r
                                 returned on a previous call to\r
                                 GetNextRootBridge().\r
**/\r
EFI_STATUS\r
EFIAPI\r
GetNextRootBridge(\r
  IN       EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN OUT   EFI_HANDLE                                       *RootBridgeHandle\r
  )\r
{\r
  BOOLEAN                               NoRootBridge;\r
  LIST_ENTRY                            *List;\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
\r
  NoRootBridge = TRUE;\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
\r
  while (List != &HostBridgeInstance->Head) {\r
    NoRootBridge = FALSE;\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (*RootBridgeHandle == NULL) {\r
      //\r
      // Return the first Root Bridge Handle of the Host Bridge\r
      //\r
      *RootBridgeHandle = RootBridgeInstance->Handle;\r
      return EFI_SUCCESS;\r
    } else {\r
      if (*RootBridgeHandle == RootBridgeInstance->Handle) {\r
        //\r
        // Get next if have\r
        //\r
        List = List->ForwardLink;\r
        if (List!=&HostBridgeInstance->Head) {\r
          RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
          *RootBridgeHandle = RootBridgeInstance->Handle;\r
          return EFI_SUCCESS;\r
        } else {\r
          return EFI_NOT_FOUND;\r
        }\r
      }\r
    }\r
\r
    List = List->ForwardLink;\r
  } //end while\r
\r
  if (NoRootBridge) {\r
    return EFI_NOT_FOUND;\r
  } else {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
}\r
\r
/**\r
  Returns the allocation attributes of a PCI root bridge.\r
\r
  The function returns the allocation attributes of a specific PCI root bridge.\r
  The attributes can vary from one PCI root bridge to another. These attributes\r
  are different from the decode-related attributes that are returned by the\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r
  RootBridgeHandle parameter is used to specify the instance of the PCI root\r
  bridge. The device handles of all the root bridges that are associated with\r
  this host bridge must be obtained by calling GetNextRootBridge(). The\r
  attributes are static in the sense that they do not change during or after\r
  the enumeration process. The hardware may provide mechanisms to change the\r
  attributes on the fly, but such changes must be completed before\r
  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is installed. The permitted\r
  values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r
  "Related Definitions" below. The caller uses these attributes to combine\r
  multiple resource requests.\r
\r
  For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI\r
  bus enumerator needs to include requests for the prefetchable memory in the\r
  nonprefetchable memory pool and not request any prefetchable memory.\r
\r
  Attribute                             Description\r
  ------------------------------------  ---------------------------------------\r
  EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM  If this bit is set, then the PCI root\r
                                        bridge does not support separate\r
                                        windows for nonprefetchable and\r
                                        prefetchable memory. A PCI bus driver\r
                                        needs to include requests for\r
                                        prefetchable memory in the\r
                                        nonprefetchable memory pool.\r
\r
  EFI_PCI_HOST_BRIDGE_MEM64_DECODE      If this bit is set, then the PCI root\r
                                        bridge supports 64-bit memory windows.\r
                                        If this bit is not set, the PCI bus\r
                                        driver needs to include requests for a\r
                                        64-bit memory address in the\r
                                        corresponding 32-bit memory pool.\r
\r
  @param[in]   This               The instance pointer of\r
                               EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
\r
  @param[in]   RootBridgeHandle   The device handle of the PCI root bridge in\r
                                  which the caller is interested. Type\r
                                  EFI_HANDLE is defined in\r
                                  InstallProtocolInterface() in the UEFI 2.0\r
                                  Specification.\r
\r
  @param[out]  Attributes         The pointer to attribte of root bridge, it is\r
                                  output parameter\r
\r
  @retval EFI_INVALID_PARAMETER   Attribute pointer is NULL\r
\r
  @retval EFI_INVALID_PARAMETER   RootBridgehandle is invalid.\r
\r
  @retval EFI_SUCCESS             Success to get attribute of interested root\r
                                  bridge.\r
**/\r
EFI_STATUS\r
EFIAPI\r
GetAttributes(\r
  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN  EFI_HANDLE                                       RootBridgeHandle,\r
  OUT UINT64                                           *Attributes\r
  )\r
{\r
  LIST_ENTRY                            *List;\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
\r
  if (Attributes == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
  while (List != &HostBridgeInstance->Head) {\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
      *Attributes = RootBridgeInstance->RootBridgeAttrib;\r
      return EFI_SUCCESS;\r
    }\r
    List = List->ForwardLink;\r
  }\r
\r
  //\r
  // RootBridgeHandle is not an EFI_HANDLE\r
  // that was returned on a previous call to GetNextRootBridge()\r
  //\r
  return EFI_INVALID_PARAMETER;\r
}\r
\r
/**\r
  Sets up the specified PCI root bridge for the bus enumeration process.\r
\r
  This member function sets up the root bridge for bus enumeration and returns\r
  the PCI bus range over which the search should be performed in ACPI 2.0\r
  resource descriptor format.\r
\r
  @param[in]   This              The\r
                               EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
                                 instance.\r
\r
  @param[in]   RootBridgeHandle  The PCI Root Bridge to be set up.\r
\r
  @param[out]  Configuration     Pointer to the pointer to the PCI bus resource\r
                                 descriptor.\r
\r
  @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r
\r
  @retval EFI_OUT_OF_RESOURCES  Fail to allocate ACPI resource descriptor tag.\r
\r
  @retval EFI_SUCCESS           Sucess to allocate ACPI resource descriptor.\r
**/\r
EFI_STATUS\r
EFIAPI\r
StartBusEnumeration(\r
  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN  EFI_HANDLE                                       RootBridgeHandle,\r
  OUT VOID                                             **Configuration\r
  )\r
{\r
  LIST_ENTRY                            *List;\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
  VOID                                  *Buffer;\r
  UINT8                                 *Temp;\r
  UINT64                                BusStart;\r
  UINT64                                BusEnd;\r
\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
  while (List != &HostBridgeInstance->Head) {\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
      //\r
      // Set up the Root Bridge for Bus Enumeration\r
      //\r
      BusStart = RootBridgeInstance->BusBase;\r
      BusEnd   = RootBridgeInstance->BusLimit;\r
      //\r
      // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR\r
      //\r
\r
      Buffer = AllocatePool (\r
                 sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) +\r
                 sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)\r
                 );\r
      if (Buffer == NULL) {\r
        return EFI_OUT_OF_RESOURCES;\r
      }\r
\r
      Temp = (UINT8 *)Buffer;\r
\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len  = 0x2B;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen =\r
        BusEnd - BusStart + 1;\r
\r
      Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
      ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;\r
      ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;\r
\r
      *Configuration = Buffer;\r
      return EFI_SUCCESS;\r
    }\r
    List = List->ForwardLink;\r
  }\r
\r
  return EFI_INVALID_PARAMETER;\r
}\r
\r
/**\r
  Programs the PCI root bridge hardware so that it decodes the specified PCI\r
  bus range.\r
\r
  This member function programs the specified PCI root bridge to decode the bus\r
  range that is specified by the input parameter Configuration.\r
  The bus range information is specified in terms of the ACPI 2.0 resource\r
  descriptor format.\r
\r
  @param[in] This              The\r
                               EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
                               instance\r
\r
  @param[in] RootBridgeHandle  The PCI Root Bridge whose bus range is to be\r
                               programmed\r
\r
  @param[in] Configuration     The pointer to the PCI bus resource descriptor\r
\r
  @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge\r
                                 handle.\r
\r
  @retval EFI_INVALID_PARAMETER  Configuration is NULL.\r
\r
  @retval EFI_INVALID_PARAMETER  Configuration does not point to a valid ACPI\r
                                 2.0 resource descriptor.\r
\r
  @retval EFI_INVALID_PARAMETER  Configuration does not include a valid ACPI\r
                                 2.0 bus resource descriptor.\r
\r
  @retval EFI_INVALID_PARAMETER  Configuration includes valid ACPI 2.0 resource\r
                                 descriptors other than bus descriptors.\r
\r
  @retval EFI_INVALID_PARAMETER  Configuration contains one or more invalid\r
                                 ACPI resource descriptors.\r
\r
  @retval EFI_INVALID_PARAMETER  "Address Range Minimum" is invalid for this\r
                                 root bridge.\r
\r
  @retval EFI_INVALID_PARAMETER  "Address Range Length" is invalid for this\r
                                 root bridge.\r
\r
  @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.\r
\r
  @retval EFI_SUCCESS            The bus range for the PCI root bridge was\r
                                 programmed.\r
**/\r
EFI_STATUS\r
EFIAPI\r
SetBusNumbers(\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN EFI_HANDLE                                       RootBridgeHandle,\r
  IN VOID                                             *Configuration\r
  )\r
{\r
  LIST_ENTRY                            *List;\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
  UINT8                                 *Ptr;\r
  UINTN                                 BusStart;\r
  UINTN                                 BusEnd;\r
  UINTN                                 BusLen;\r
\r
  if (Configuration == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Ptr = Configuration;\r
\r
  //\r
  // Check the Configuration is valid\r
  //\r
  if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
  if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
  Ptr = Configuration;\r
\r
  while (List != &HostBridgeInstance->Head) {\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
      EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;\r
\r
      Desc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr;\r
      BusStart = (UINTN)Desc->AddrRangeMin;\r
      BusLen = (UINTN)Desc->AddrLen;\r
      BusEnd = BusStart + BusLen - 1;\r
\r
      if (BusStart > BusEnd) {\r
        return EFI_INVALID_PARAMETER;\r
      }\r
\r
      if ((BusStart < RootBridgeInstance->BusBase) ||\r
          (BusEnd > RootBridgeInstance->BusLimit)) {\r
        return EFI_INVALID_PARAMETER;\r
      }\r
\r
      //\r
      // Update the Bus Range\r
      //\r
      RootBridgeInstance->ResAllocNode[TypeBus].Base   = BusStart;\r
      RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;\r
      RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;\r
\r
      //\r
      // Program the Root Bridge Hardware\r
      //\r
\r
      return EFI_SUCCESS;\r
    }\r
\r
    List = List->ForwardLink;\r
  }\r
\r
  return EFI_INVALID_PARAMETER;\r
}\r
\r
\r
/**\r
  Submits the I/O and memory resource requirements for the specified PCI root\r
  bridge.\r
\r
  This function is used to submit all the I/O and memory resources that are\r
  required by the specified PCI root bridge. The input parameter Configuration\r
  is used to specify the following:\r
  - The various types of resources that are required\r
  - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
\r
  @param[in] This              Pointer to the\r
                               EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
                               instance.\r
\r
  @param[in] RootBridgeHandle  The PCI root bridge whose I/O and memory\r
                               resource requirements are being submitted.\r
\r
  @param[in] Configuration     The pointer to the PCI I/O and PCI memory\r
                               resource descriptor.\r
\r
  @retval EFI_SUCCESS            The I/O and memory resource requests for a PCI\r
                                 root bridge were accepted.\r
\r
  @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge\r
                                 handle.\r
\r
  @retval EFI_INVALID_PARAMETER  Configuration is NULL.\r
\r
  @retval EFI_INVALID_PARAMETER  Configuration does not point to a valid ACPI\r
                                 2.0 resource descriptor.\r
\r
  @retval EFI_INVALID_PARAMETER  Configuration includes requests for one or\r
                                 more resource types that are not supported by\r
                                 this PCI root bridge. This error will happen\r
                                 if the caller did not combine resources\r
                                 according to Attributes that were returned by\r
                                 GetAllocAttributes().\r
\r
  @retval EFI_INVALID_PARAMETER  Address Range Maximum" is invalid.\r
\r
  @retval EFI_INVALID_PARAMETER  "Address Range Length" is invalid for this PCI\r
                                 root bridge.\r
\r
  @retval EFI_INVALID_PARAMETER  "Address Space Granularity" is invalid for\r
                                 this PCI root bridge.\r
**/\r
EFI_STATUS\r
EFIAPI\r
SubmitResources(\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN EFI_HANDLE                                       RootBridgeHandle,\r
  IN VOID                                             *Configuration\r
  )\r
{\r
  LIST_ENTRY                            *List;\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
  UINT8                                 *Temp;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *Ptr;\r
  UINT64                                AddrLen;\r
  UINT64                                Alignment;\r
\r
  //\r
  // Check the input parameter: Configuration\r
  //\r
  if (Configuration == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
  Temp = (UINT8 *)Configuration;\r
  while ( *Temp == 0x8A) {\r
    Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;\r
  }\r
  if (*Temp != 0x79) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Temp = (UINT8 *)Configuration;\r
  while (List != &HostBridgeInstance->Head) {\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
      while ( *Temp == 0x8A) {\r
        Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
\r
        //\r
        // Check Address Length\r
        //\r
        if (Ptr->AddrLen > 0xffffffff) {\r
          return EFI_INVALID_PARAMETER;\r
        }\r
\r
        //\r
        // Check address range alignment\r
        //\r
        if (Ptr->AddrRangeMax >= 0xffffffff ||\r
            Ptr->AddrRangeMax != (GetPowerOfTwo64 (\r
                                    Ptr->AddrRangeMax + 1) - 1)) {\r
          return EFI_INVALID_PARAMETER;\r
        }\r
\r
        switch (Ptr->ResType) {\r
\r
        case 0:\r
\r
          //\r
          // Check invalid Address Sapce Granularity\r
          //\r
          if (Ptr->AddrSpaceGranularity != 32) {\r
            return EFI_INVALID_PARAMETER;\r
          }\r
\r
          //\r
          // check the memory resource request is supported by PCI root bridge\r
          //\r
          if (RootBridgeInstance->RootBridgeAttrib ==\r
                EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&\r
              Ptr->SpecificFlag == 0x06) {\r
            return EFI_INVALID_PARAMETER;\r
          }\r
\r
          AddrLen = Ptr->AddrLen;\r
          Alignment = Ptr->AddrRangeMax;\r
          if (Ptr->AddrSpaceGranularity == 32) {\r
            if (Ptr->SpecificFlag == 0x06) {\r
              //\r
              // Apply from GCD\r
              //\r
              RootBridgeInstance->ResAllocNode[TypePMem32].Status =\r
                ResSubmitted;\r
            } else {\r
              RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;\r
              RootBridgeInstance->ResAllocNode[TypeMem32].Alignment =\r
                Alignment;\r
              RootBridgeInstance->ResAllocNode[TypeMem32].Status =\r
                ResRequested;\r
              HostBridgeInstance->ResourceSubmited = TRUE;\r
            }\r
          }\r
\r
          if (Ptr->AddrSpaceGranularity == 64) {\r
            if (Ptr->SpecificFlag == 0x06) {\r
              RootBridgeInstance->ResAllocNode[TypePMem64].Status =\r
                ResSubmitted;\r
            } else {\r
              RootBridgeInstance->ResAllocNode[TypeMem64].Status =\r
                ResSubmitted;\r
            }\r
          }\r
          break;\r
\r
        case 1:\r
          AddrLen = (UINTN) Ptr->AddrLen;\r
          Alignment = (UINTN) Ptr->AddrRangeMax;\r
          RootBridgeInstance->ResAllocNode[TypeIo].Length  = AddrLen;\r
          RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;\r
          RootBridgeInstance->ResAllocNode[TypeIo].Status  = ResRequested;\r
          HostBridgeInstance->ResourceSubmited = TRUE;\r
          break;\r
\r
        default:\r
            break;\r
        };\r
\r
        Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;\r
      }\r
\r
      return EFI_SUCCESS;\r
    }\r
\r
    List = List->ForwardLink;\r
  }\r
\r
  return EFI_INVALID_PARAMETER;\r
}\r
\r
/**\r
   Returns the proposed resource settings for the specified PCI root bridge.\r
\r
   This member function returns the proposed resource settings for the\r
   specified PCI root bridge. The proposed resource settings are prepared when\r
   NotifyPhase() is called with a Phase of EfiPciHostBridgeAllocateResources.\r
   The output parameter Configuration specifies the following:\r
   - The various types of resources, excluding bus resources, that are\r
     allocated\r
   - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
\r
   @param[in]  This              Pointer to the\r
                               EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
                                 instance.\r
\r
   @param[in]  RootBridgeHandle  The PCI root bridge handle. Type EFI_HANDLE is\r
                                 defined in InstallProtocolInterface() in the\r
                                 UEFI 2.0 Specification.\r
\r
   @param[out] Configuration     The pointer to the pointer to the PCI I/O and\r
                                 memory resource descriptor.\r
\r
   @retval EFI_SUCCESS            The requested parameters were returned.\r
\r
   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge\r
                                  handle.\r
\r
   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.\r
\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a\r
                                  lack of resources.\r
**/\r
EFI_STATUS\r
EFIAPI\r
GetProposedResources(\r
  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN  EFI_HANDLE                                       RootBridgeHandle,\r
  OUT VOID                                             **Configuration\r
  )\r
{\r
  LIST_ENTRY                            *List;\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
  UINTN                                 Index;\r
  UINTN                                 Number;\r
  VOID                                  *Buffer;\r
  UINT8                                 *Temp;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *Ptr;\r
  UINT64                                ResStatus;\r
\r
  Buffer = NULL;\r
  Number = 0;\r
  //\r
  // Get the Host Bridge Instance from the resource allocation protocol\r
  //\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
  //\r
  // Enumerate the root bridges in this host bridge\r
  //\r
  while (List != &HostBridgeInstance->Head) {\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
      for (Index = 0; Index < TypeBus; Index ++) {\r
        if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
          Number ++;\r
        }\r
      }\r
\r
      if (Number ==  0) {\r
        return EFI_INVALID_PARAMETER;\r
      }\r
\r
      Buffer = AllocateZeroPool (\r
                 Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) +\r
                 sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)\r
                 );\r
      if (Buffer == NULL) {\r
        return EFI_OUT_OF_RESOURCES;\r
      }\r
\r
      Temp = Buffer;\r
      for (Index = 0; Index < TypeBus; Index ++) {\r
        if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
          Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
          ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;\r
\r
          switch (Index) {\r
\r
          case TypeIo:\r
            //\r
            // Io\r
            //\r
            Ptr->Desc = 0x8A;\r
            Ptr->Len  = 0x2B;\r
            Ptr->ResType = 1;\r
            Ptr->GenFlag = 0;\r
            Ptr->SpecificFlag = 0;\r
            Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
            Ptr->AddrRangeMax = 0;\r
            Ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ?\r
                                           EFI_RESOURCE_SATISFIED :\r
                                           EFI_RESOURCE_LESS;\r
            Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
            break;\r
\r
          case TypeMem32:\r
            //\r
            // Memory 32\r
            //\r
            Ptr->Desc = 0x8A;\r
            Ptr->Len  = 0x2B;\r
            Ptr->ResType = 0;\r
            Ptr->GenFlag = 0;\r
            Ptr->SpecificFlag = 0;\r
            Ptr->AddrSpaceGranularity = 32;\r
            Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
            Ptr->AddrRangeMax = 0;\r
            Ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ?\r
                                           EFI_RESOURCE_SATISFIED :\r
                                           EFI_RESOURCE_LESS;\r
            Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
            break;\r
\r
          case TypePMem32:\r
            //\r
            // Prefetch memory 32\r
            //\r
            Ptr->Desc = 0x8A;\r
            Ptr->Len  = 0x2B;\r
            Ptr->ResType = 0;\r
            Ptr->GenFlag = 0;\r
            Ptr->SpecificFlag = 6;\r
            Ptr->AddrSpaceGranularity = 32;\r
            Ptr->AddrRangeMin = 0;\r
            Ptr->AddrRangeMax = 0;\r
            Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
            Ptr->AddrLen = 0;\r
            break;\r
\r
          case TypeMem64:\r
            //\r
            // Memory 64\r
            //\r
            Ptr->Desc = 0x8A;\r
            Ptr->Len  = 0x2B;\r
            Ptr->ResType = 0;\r
            Ptr->GenFlag = 0;\r
            Ptr->SpecificFlag = 0;\r
            Ptr->AddrSpaceGranularity = 64;\r
            Ptr->AddrRangeMin = 0;\r
            Ptr->AddrRangeMax = 0;\r
            Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
            Ptr->AddrLen = 0;\r
            break;\r
\r
          case TypePMem64:\r
            //\r
            // Prefetch memory 64\r
            //\r
            Ptr->Desc = 0x8A;\r
            Ptr->Len  = 0x2B;\r
            Ptr->ResType = 0;\r
            Ptr->GenFlag = 0;\r
            Ptr->SpecificFlag = 6;\r
            Ptr->AddrSpaceGranularity = 64;\r
            Ptr->AddrRangeMin = 0;\r
            Ptr->AddrRangeMax = 0;\r
            Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
            Ptr->AddrLen = 0;\r
            break;\r
          };\r
\r
          Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
        }\r
      }\r
\r
      ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;\r
      ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;\r
\r
      *Configuration = Buffer;\r
\r
      return EFI_SUCCESS;\r
    }\r
\r
    List = List->ForwardLink;\r
  }\r
\r
  return EFI_INVALID_PARAMETER;\r
}\r
\r
/**\r
  Provides the hooks from the PCI bus driver to every PCI controller\r
  (device/function) at various stages of the PCI enumeration process that allow\r
  the host bridge driver to preinitialize individual PCI controllers before\r
  enumeration.\r
\r
  This function is called during the PCI enumeration process. No specific\r
  action is expected from this member function. It allows the host bridge\r
  driver to preinitialize individual PCI controllers before enumeration.\r
\r
  @param This              Pointer to the\r
                           EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
                           instance.\r
\r
  @param RootBridgeHandle  The associated PCI root bridge handle. Type\r
                           EFI_HANDLE is defined in InstallProtocolInterface()\r
                           in the UEFI 2.0 Specification.\r
\r
  @param PciAddress        The address of the PCI device on the PCI bus. This\r
                           address can be passed to the\r
                           EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to\r
                           access the PCI configuration space of the device.\r
                           See Table 12-1 in the UEFI 2.0 Specification for the\r
                           definition of\r
                           EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r
\r
  @param Phase             The phase of the PCI device enumeration.\r
\r
  @retval EFI_SUCCESS              The requested parameters were returned.\r
\r
  @retval EFI_INVALID_PARAMETER    RootBridgeHandle is not a valid root bridge\r
                                   handle.\r
\r
  @retval EFI_INVALID_PARAMETER    Phase is not a valid phase that is defined\r
                                   in\r
                                  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
\r
  @retval EFI_DEVICE_ERROR         Programming failed due to a hardware error.\r
                                   The PCI enumerator should not enumerate this\r
                                   device, including its child devices if it is\r
                                   a PCI-to-PCI bridge.\r
**/\r
EFI_STATUS\r
EFIAPI\r
PreprocessController (\r
  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL        *This,\r
  IN  EFI_HANDLE                                              RootBridgeHandle,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS             PciAddress,\r
  IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE            Phase\r
  )\r
{\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
  LIST_ENTRY                            *List;\r
\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
  //\r
  // Enumerate the root bridges in this host bridge\r
  //\r
  while (List != &HostBridgeInstance->Head) {\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
      break;\r
    }\r
    List = List->ForwardLink;\r
  }\r
  if (List == &HostBridgeInstance->Head) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((UINT32)Phase > EfiPciBeforeResourceCollection) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r