]> git.proxmox.com Git - mirror_edk2.git/blame - OvmfPkg/PciHostBridgeDxe/PciHostBridge.h
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
BaseTools/Ecc: Fix a bug to report fake issue
[mirror_edk2.git] / OvmfPkg / PciHostBridgeDxe / PciHostBridge.h
CommitLineData
d52bde1c
LE		 1/** @file\r
2 The Header file of the Pci Host Bridge Driver\r
3\r
fe907a68 4 Copyright (C) 2015, Red Hat, Inc.\r
d52bde1c
LE		 5 Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r
6\r
7 This program and the accompanying materials are licensed and made available\r
8 under the terms and conditions of the BSD License which accompanies this\r
9 distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14**/\r
15\r
16#ifndef _PCI_HOST_BRIDGE_H_\r
17#define _PCI_HOST_BRIDGE_H_\r
18\r
19#include <PiDxe.h>\r
20\r
21#include <IndustryStandard/Pci.h>\r
22#include <IndustryStandard/Acpi.h>\r
23\r
24#include <Protocol/PciHostBridgeResourceAllocation.h>\r
25#include <Protocol/PciRootBridgeIo.h>\r
26#include <Protocol/Metronome.h>\r
27#include <Protocol/DevicePath.h>\r
28\r
29\r
30#include <Library/BaseLib.h>\r
31#include <Library/DebugLib.h>\r
32#include <Library/BaseMemoryLib.h>\r
33#include <Library/MemoryAllocationLib.h>\r
34#include <Library/UefiLib.h>\r
35#include <Library/UefiBootServicesTableLib.h>\r
36#include <Library/DxeServicesTableLib.h>\r
37#include <Library/DevicePathLib.h>\r
38#include <Library/IoLib.h>\r
39#include <Library/PciLib.h>\r
40\r
d52bde1c
LE		 41#define MAX_PCI_DEVICE_NUMBER 31\r
42#define MAX_PCI_FUNCTION_NUMBER 7\r
43#define MAX_PCI_REG_ADDRESS 0xFF\r
44\r
45typedef enum {\r
46 IoOperation,\r
47 MemOperation,\r
48 PciOperation\r
49} OPERATION_TYPE;\r
50\r
51#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')\r
52typedef struct {\r
53 UINTN Signature;\r
54 EFI_HANDLE HostBridgeHandle;\r
d52bde1c
LE		 55 LIST_ENTRY Head;\r
56 BOOLEAN ResourceSubmited;\r
57 BOOLEAN CanRestarted;\r
58 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;\r
59} PCI_HOST_BRIDGE_INSTANCE;\r
60\r
61#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \\r
62 CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r
63\r
64//\r
65// HostBridge Resource Allocation interface\r
66//\r
67\r
68/**\r
69 These are the notifications from the PCI bus driver that it is about to enter\r
70 a certain phase of the PCI enumeration process.\r
71\r
72 This member function can be used to notify the host bridge driver to perform\r
73 specific actions, including any chipset-specific initialization, so that the\r
74 chipset is ready to enter the next phase. Eight notification points are\r
75 defined at this time. See belows:\r
76\r
77 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures\r
78 and internal data structures. The PCI\r
79 enumerator should issue this\r
80 notification before starting a fresh\r
81 enumeration process. Enumeration\r
82 cannot be restarted after sending any\r
83 other notification such as\r
84 EfiPciHostBridgeBeginBusAllocation.\r
85\r
86 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to\r
87 begin. No specific action is required\r
88 here. This notification can be used to\r
89 perform any chipset-specific\r
90 programming.\r
91\r
92 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming\r
93 phase is complete. No specific action\r
94 is required here. This notification\r
95 can be used to perform any\r
96 chipset-specific programming.\r
97\r
98 EfiPciHostBridgeBeginResourceAllocation\r
99 The resource allocation phase is about\r
100 to begin. No specific action is\r
101 required here. This notification can\r
102 be used to perform any\r
103 chipset-specific programming.\r
104\r
105 EfiPciHostBridgeAllocateResources Allocates resources per previously\r
106 submitted requests for all the PCI\r
107 root bridges. These resource settings\r
108 are returned on the next call to\r
109 GetProposedResources(). Before calling\r
110 NotifyPhase() with a Phase of\r
111 EfiPciHostBridgeAllocateResource, the\r
112 PCI bus enumerator is responsible for\r
113 gathering I/O and memory requests for\r
114 all the PCI root bridges and\r
115 submitting these requests using\r
116 SubmitResources(). This function pads\r
117 the resource amount to suit the root\r
118 bridge hardware, takes care of\r
119 dependencies between the PCI root\r
120 bridges, and calls the Global\r
121 Coherency Domain (GCD) with the\r
122 allocation request. In the case of\r
123 padding, the allocated range could be\r
124 bigger than what was requested.\r
125\r
126 EfiPciHostBridgeSetResources Programs the host bridge hardware to\r
127 decode previously allocated resources\r
128 (proposed resources) for all the PCI\r
129 root bridges. After the hardware is\r
130 programmed, reassigning resources will\r
131 not be supported. The bus settings are\r
132 not affected.\r
133\r
134 EfiPciHostBridgeFreeResources Deallocates resources that were\r
135 previously allocated for all the PCI\r
136 root bridges and resets the I/O and\r
137 memory apertures to their initial\r
138 state. The bus settings are not\r
139 affected. If the request to allocate\r
140 resources fails, the PCI enumerator\r
141 can use this notification to\r
142 deallocate previous resources, adjust\r
143 the requests, and retry allocation.\r
144\r
145 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is\r
146 completed. No specific action is\r
147 required here. This notification can\r
148 be used to perform any chipsetspecific\r
149 programming.\r
150\r
151 @param[in] This The instance pointer of\r
152 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
153\r
154 @param[in] Phase The phase during enumeration\r
155\r
156 @retval EFI_NOT_READY This phase cannot be entered at this time. For\r
157 example, this error is valid for a Phase of\r
158 EfiPciHostBridgeAllocateResources if\r
159 SubmitResources() has not been called for one\r
160 or more PCI root bridges before this call\r
161\r
162 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
163 This error is valid for a Phase of\r
164 EfiPciHostBridgeSetResources.\r
165\r
166 @retval EFI_INVALID_PARAMETER Invalid phase parameter\r
167\r
168 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
169 lack of resources. This error is valid for a\r
170 Phase of EfiPciHostBridgeAllocateResources if\r
171 the previously submitted resource requests\r
172 cannot be fulfilled or were only partially\r
173 fulfilled.\r
174\r
175 @retval EFI_SUCCESS The notification was accepted without any\r
176 errors.\r
177**/\r
178EFI_STATUS\r
179EFIAPI\r
180NotifyPhase(\r
181 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
182 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
183 );\r
184\r
185/**\r
186 Return the device handle of the next PCI root bridge that is associated with\r
187 this Host Bridge.\r
188\r
189 This function is called multiple times to retrieve the device handles of all\r
190 the PCI root bridges that are associated with this PCI host bridge. Each PCI\r
191 host bridge is associated with one or more PCI root bridges. On each call,\r
192 the handle that was returned by the previous call is passed into the\r
193 interface, and on output the interface returns the device handle of the next\r
194 PCI root bridge. The caller can use the handle to obtain the instance of the\r
195 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL for that root bridge. When there are no more\r
196 PCI root bridges to report, the interface returns EFI_NOT_FOUND. A PCI\r
197 enumerator must enumerate the PCI root bridges in the order that they are\r
198 returned by this function.\r
199\r
200 For D945 implementation, there is only one root bridge in PCI host bridge.\r
201\r
202 @param[in] This The instance pointer of\r
203 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
204\r
205 @param[in, out] RootBridgeHandle Returns the device handle of the next PCI\r
206 root bridge.\r
207\r
208 @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then\r
209 return the first Rootbridge handle of the\r
210 specific Host bridge and return EFI_SUCCESS.\r
211\r
212 @retval EFI_NOT_FOUND Can not find the any more root bridge in\r
213 specific host bridge.\r
214\r
215 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was\r
216 returned on a previous call to\r
217 GetNextRootBridge().\r
218**/\r
219EFI_STATUS\r
220EFIAPI\r
221GetNextRootBridge(\r
222 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
223 IN OUT EFI_HANDLE *RootBridgeHandle\r
224 );\r
225\r
226/**\r
227 Returns the allocation attributes of a PCI root bridge.\r
228\r
229 The function returns the allocation attributes of a specific PCI root bridge.\r
230 The attributes can vary from one PCI root bridge to another. These attributes\r
231 are different from the decode-related attributes that are returned by the\r
232 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r
233 RootBridgeHandle parameter is used to specify the instance of the PCI root\r
234 bridge. The device handles of all the root bridges that are associated with\r
235 this host bridge must be obtained by calling GetNextRootBridge(). The\r
236 attributes are static in the sense that they do not change during or after\r
237 the enumeration process. The hardware may provide mechanisms to change the\r
238 attributes on the fly, but such changes must be completed before\r
239 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is installed. The permitted\r
240 values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r
241 "Related Definitions" below. The caller uses these attributes to combine\r
242 multiple resource requests.\r
243\r
244 For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI\r
245 bus enumerator needs to include requests for the prefetchable memory in the\r
246 nonprefetchable memory pool and not request any prefetchable memory.\r
247\r
248 Attribute Description\r
249 ------------------------------------ ---------------------------------------\r
250 EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root\r
251 bridge does not support separate\r
252 windows for nonprefetchable and\r
253 prefetchable memory. A PCI bus driver\r
254 needs to include requests for\r
255 prefetchable memory in the\r
256 nonprefetchable memory pool.\r
257\r
258 EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root\r
259 bridge supports 64-bit memory windows.\r
260 If this bit is not set, the PCI bus\r
261 driver needs to include requests for a\r
262 64-bit memory address in the\r
263 corresponding 32-bit memory pool.\r
264\r
265 @param[in] This The instance pointer of\r
266 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
267\r
268 @param[in] RootBridgeHandle The device handle of the PCI root bridge in\r
269 which the caller is interested. Type\r
270 EFI_HANDLE is defined in\r
271 InstallProtocolInterface() in the UEFI 2.0\r
272 Specification.\r
273\r
274 @param[out] Attributes The pointer to attribte of root bridge, it is\r
275 output parameter\r
276\r
277 @retval EFI_INVALID_PARAMETER Attribute pointer is NULL\r
278\r
279 @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.\r
280\r
281 @retval EFI_SUCCESS Success to get attribute of interested root\r
282 bridge.\r
283**/\r
284EFI_STATUS\r
285EFIAPI\r
286GetAttributes(\r
287 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
288 IN EFI_HANDLE RootBridgeHandle,\r
289 OUT UINT64 *Attributes\r
290 );\r
291\r
292/**\r
293 Sets up the specified PCI root bridge for the bus enumeration process.\r
294\r
295 This member function sets up the root bridge for bus enumeration and returns\r
296 the PCI bus range over which the search should be performed in ACPI 2.0\r
297 resource descriptor format.\r
298\r
299 @param[in] This The\r
300 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
301 instance.\r
302\r
303 @param[in] RootBridgeHandle The PCI Root Bridge to be set up.\r
304\r
305 @param[out] Configuration Pointer to the pointer to the PCI bus resource\r
306 descriptor.\r
307\r
308 @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r
309\r
310 @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.\r
311\r
312 @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.\r
313**/\r
314EFI_STATUS\r
315EFIAPI\r
316StartBusEnumeration(\r
317 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
318 IN EFI_HANDLE RootBridgeHandle,\r
319 OUT VOID **Configuration\r
320 );\r
321\r
322/**\r
323 Programs the PCI root bridge hardware so that it decodes the specified PCI\r
324 bus range.\r
325\r
326 This member function programs the specified PCI root bridge to decode the bus\r
327 range that is specified by the input parameter Configuration.\r
328 The bus range information is specified in terms of the ACPI 2.0 resource\r
329 descriptor format.\r
330\r
331 @param[in] This The\r
332 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
333 instance\r
334\r
335 @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be\r
336 programmed\r
337\r
338 @param[in] Configuration The pointer to the PCI bus resource descriptor\r
339\r
340 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r
341 handle.\r
342\r
343 @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
344\r
345 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI\r
346 2.0 resource descriptor.\r
347\r
348 @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI\r
349 2.0 bus resource descriptor.\r
350\r
351 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource\r
352 descriptors other than bus descriptors.\r
353\r
354 @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid\r
355 ACPI resource descriptors.\r
356\r
357 @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this\r
358 root bridge.\r
359\r
360 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this\r
361 root bridge.\r
362\r
363 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
364\r
365 @retval EFI_SUCCESS The bus range for the PCI root bridge was\r
366 programmed.\r
367**/\r
368EFI_STATUS\r
369EFIAPI\r
370SetBusNumbers(\r
371 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
372 IN EFI_HANDLE RootBridgeHandle,\r
373 IN VOID *Configuration\r
374 );\r
375\r
376/**\r
377 Submits the I/O and memory resource requirements for the specified PCI root\r
378 bridge.\r
379\r
380 This function is used to submit all the I/O and memory resources that are\r
381 required by the specified PCI root bridge. The input parameter Configuration\r
382 is used to specify the following:\r
383 - The various types of resources that are required\r
384 - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
385\r
386 @param[in] This Pointer to the\r
387 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
388 instance.\r
389\r
390 @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory\r
391 resource requirements are being submitted.\r
392\r
393 @param[in] Configuration The pointer to the PCI I/O and PCI memory\r
394 resource descriptor.\r
395\r
396 @retval EFI_SUCCESS The I/O and memory resource requests for a PCI\r
397 root bridge were accepted.\r
398\r
399 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r
400 handle.\r
401\r
402 @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
403\r
404 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI\r
405 2.0 resource descriptor.\r
406\r
407 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or\r
408 more resource types that are not supported by\r
409 this PCI root bridge. This error will happen\r
410 if the caller did not combine resources\r
411 according to Attributes that were returned by\r
412 GetAllocAttributes().\r
413\r
414 @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.\r
415\r
416 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI\r
417 root bridge.\r
418\r
419 @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for\r
420 this PCI root bridge.\r
421**/\r
422EFI_STATUS\r
423EFIAPI\r
424SubmitResources(\r
425 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
426 IN EFI_HANDLE RootBridgeHandle,\r
427 IN VOID *Configuration\r
428 );\r
429\r
430/**\r
431 Returns the proposed resource settings for the specified PCI root bridge.\r
432\r
433 This member function returns the proposed resource settings for the\r
434 specified PCI root bridge. The proposed resource settings are prepared when\r
435 NotifyPhase() is called with a Phase of EfiPciHostBridgeAllocateResources.\r
436 The output parameter Configuration specifies the following:\r
437 - The various types of resources, excluding bus resources, that are\r
438 allocated\r
439 - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
440\r
441 @param[in] This Pointer to the\r
442 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
443 instance.\r
444\r
445 @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is\r
446 defined in InstallProtocolInterface() in the\r
447 UEFI 2.0 Specification.\r
448\r
449 @param[out] Configuration The pointer to the pointer to the PCI I/O and\r
450 memory resource descriptor.\r
451\r
452 @retval EFI_SUCCESS The requested parameters were returned.\r
453\r
454 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r
455 handle.\r
456\r
457 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
458\r
459 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
460 lack of resources.\r
461**/\r
462EFI_STATUS\r
463EFIAPI\r
464GetProposedResources(\r
465 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
466 IN EFI_HANDLE RootBridgeHandle,\r
467 OUT VOID **Configuration\r
468 );\r
469\r
470/**\r
471 Provides the hooks from the PCI bus driver to every PCI controller\r
472 (device/function) at various stages of the PCI enumeration process that allow\r
473 the host bridge driver to preinitialize individual PCI controllers before\r
474 enumeration.\r
475\r
476 This function is called during the PCI enumeration process. No specific\r
477 action is expected from this member function. It allows the host bridge\r
478 driver to preinitialize individual PCI controllers before enumeration.\r
479\r
480 @param This Pointer to the\r
481 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
482 instance.\r
483\r
484 @param RootBridgeHandle The associated PCI root bridge handle. Type\r
485 EFI_HANDLE is defined in InstallProtocolInterface()\r
486 in the UEFI 2.0 Specification.\r
487\r
488 @param PciAddress The address of the PCI device on the PCI bus. This\r
489 address can be passed to the\r
490 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to\r
491 access the PCI configuration space of the device.\r
492 See Table 12-1 in the UEFI 2.0 Specification for the\r
493 definition of\r
494 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r
495\r
496 @param Phase The phase of the PCI device enumeration.\r
497\r
498 @retval EFI_SUCCESS The requested parameters were returned.\r
499\r
500 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r
501 handle.\r
502\r
503 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined\r
504 in\r
505 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
506\r
507 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
508 The PCI enumerator should not enumerate this\r
509 device, including its child devices if it is\r
510 a PCI-to-PCI bridge.\r
511**/\r
512EFI_STATUS\r
513EFIAPI\r
514PreprocessController (\r
515 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
516 IN EFI_HANDLE RootBridgeHandle,\r
517 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
518 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
519 );\r
520\r
521\r
522//\r
523// Define resource status constant\r
524//\r
525#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r
526#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r
527\r
528\r
529//\r
530// Driver Instance Data Prototypes\r
531//\r
532\r
533typedef struct {\r
534 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;\r
535 UINTN NumberOfBytes;\r
536 UINTN NumberOfPages;\r
537 EFI_PHYSICAL_ADDRESS HostAddress;\r
538 EFI_PHYSICAL_ADDRESS MappedHostAddress;\r
539} MAP_INFO;\r
540\r
541typedef struct {\r
542 ACPI_HID_DEVICE_PATH AcpiDevicePath;\r
543 EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
544} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
545\r
546typedef struct {\r
547 UINT64 BusBase;\r
548 UINT64 BusLimit;\r
549\r
550 UINT64 MemBase;\r
551 UINT64 MemLimit;\r
552\r
553 UINT64 IoBase;\r
554 UINT64 IoLimit;\r
555} PCI_ROOT_BRIDGE_RESOURCE_APERTURE;\r
556\r
557typedef enum {\r
558 TypeIo = 0,\r
559 TypeMem32,\r
560 TypePMem32,\r
561 TypeMem64,\r
562 TypePMem64,\r
563 TypeBus,\r
564 TypeMax\r
565} PCI_RESOURCE_TYPE;\r
566\r
567typedef enum {\r
568 ResNone = 0,\r
569 ResSubmitted,\r
570 ResRequested,\r
571 ResAllocated,\r
572 ResStatusMax\r
573} RES_STATUS;\r
574\r
575typedef struct {\r
576 PCI_RESOURCE_TYPE Type;\r
577 UINT64 Base;\r
578 UINT64 Length;\r
579 UINT64 Alignment;\r
580 RES_STATUS Status;\r
581} PCI_RES_NODE;\r
582\r
20f7840e
LE		 583#pragma pack(1)\r
584typedef struct {\r
585 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesc[TypeMax];\r
586 EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;\r
587} RESOURCE_CONFIGURATION;\r
588#pragma pack()\r
589\r
d52bde1c
LE		 590#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b')\r
591\r
592typedef struct {\r
593 UINT32 Signature;\r
594 LIST_ENTRY Link;\r
595 EFI_HANDLE Handle;\r
596 UINT64 RootBridgeAttrib;\r
597 UINT64 Attributes;\r
598 UINT64 Supports;\r
599\r
600 //\r
601 // Specific for this memory controller: Bus, I/O, Mem\r
602 //\r
603 PCI_RES_NODE ResAllocNode[6];\r
604\r
605 //\r
606 // Addressing for Memory and I/O and Bus arrange\r
607 //\r
608 UINT64 BusBase;\r
609 UINT64 MemBase;\r
610 UINT64 IoBase;\r
611 UINT64 BusLimit;\r
612 UINT64 MemLimit;\r
613 UINT64 IoLimit;\r
614\r
fe907a68 615 EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;\r
d52bde1c
LE		 616 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r
617\r
20f7840e 618 RESOURCE_CONFIGURATION ConfigBuffer;\r
d52bde1c
LE		 619} PCI_ROOT_BRIDGE_INSTANCE;\r
620\r
621\r
622//\r
623// Driver Instance Data Macros\r
624//\r
625#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \\r
626 CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)\r
627\r
628\r
629#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \\r
630 CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)\r
631\r
632/**\r
633\r
634 Construct the Pci Root Bridge Io protocol\r
635\r
636 @param Protocol Point to protocol instance\r
637 @param HostBridgeHandle Handle of host bridge\r
638 @param Attri Attribute of host bridge\r
639 @param ResAperture ResourceAperture for host bridge\r
640\r
641 @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r
642**/\r
643EFI_STATUS\r
644RootBridgeConstructor (\r
645 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r
646 IN EFI_HANDLE HostBridgeHandle,\r
647 IN UINT64 Attri,\r
648 IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture\r
649 );\r
650\r
651#endif\r
EFI Development Kit II mirror for PVE