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8aba40b7
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1/** @file\r
2 This driver implements EFI_PCI_HOT_PLUG_INIT_PROTOCOL, providing the PCI bus\r
3 driver with resource padding information, for PCIe hotplug purposes.\r
4\r
5 Copyright (C) 2016, Red Hat, Inc.\r
6\r
b26f0cf9 7 SPDX-License-Identifier: BSD-2-Clause-Patent\r
8aba40b7
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8**/\r
9\r
10#include <IndustryStandard/Acpi10.h>\r
3815101f 11#include <IndustryStandard/Q35MchIch9.h>\r
fe404947 12#include <IndustryStandard/QemuPciBridgeCapabilities.h>\r
8aba40b7 13\r
4776d5cb 14#include <Library/BaseLib.h>\r
a9803247 15#include <Library/BaseMemoryLib.h>\r
8aba40b7
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16#include <Library/DebugLib.h>\r
17#include <Library/DevicePathLib.h>\r
18#include <Library/MemoryAllocationLib.h>\r
3815101f
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19#include <Library/PciCapLib.h>\r
20#include <Library/PciCapPciSegmentLib.h>\r
fe404947 21#include <Library/PciLib.h>\r
8aba40b7
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22#include <Library/UefiBootServicesTableLib.h>\r
23\r
24#include <Protocol/PciHotPlugInit.h>\r
25#include <Protocol/PciRootBridgeIo.h>\r
26\r
3815101f
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27//\r
28// TRUE if the PCI platform supports extended config space, FALSE otherwise.\r
29//\r
ac0a286f 30STATIC BOOLEAN mPciExtConfSpaceSupported;\r
3815101f 31\r
8aba40b7
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32//\r
33// The protocol interface this driver produces.\r
34//\r
35// Refer to 12.6 "PCI Hot Plug PCI Initialization Protocol" in the Platform\r
36// Init 1.4a Spec, Volume 5.\r
37//\r
ac0a286f 38STATIC EFI_PCI_HOT_PLUG_INIT_PROTOCOL mPciHotPlugInit;\r
8aba40b7
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39\r
40//\r
41// Resource padding template for the GetResourcePadding() protocol member\r
42// function.\r
43//\r
44// Refer to Table 8 "ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage" in\r
45// the Platform Init 1.4a Spec, Volume 5.\r
46//\r
47// This structure is interpreted by the ApplyResourcePadding() function in the\r
48// edk2 PCI Bus UEFI_DRIVER.\r
49//\r
a9803247
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50// We can request padding for at most four resource types, each of which is\r
51// optional, independently of the others:\r
52// (a) bus numbers,\r
53// (b) IO space,\r
54// (c) non-prefetchable MMIO space (32-bit only),\r
55// (d) prefetchable MMIO space (either 32-bit or 64-bit, never both).\r
56//\r
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57#pragma pack (1)\r
58typedef struct {\r
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59 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Padding[4];\r
60 EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;\r
8aba40b7
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61} RESOURCE_PADDING;\r
62#pragma pack ()\r
63\r
a9803247
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64/**\r
65 Initialize a RESOURCE_PADDING object.\r
66\r
67 @param[out] ResourcePadding The caller-allocated RESOURCE_PADDING object to\r
68 initialize.\r
69**/\r
70STATIC\r
71VOID\r
72InitializeResourcePadding (\r
ac0a286f 73 OUT RESOURCE_PADDING *ResourcePadding\r
a9803247
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74 )\r
75{\r
ac0a286f 76 UINTN Index;\r
a9803247
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77\r
78 ZeroMem (ResourcePadding, sizeof *ResourcePadding);\r
8aba40b7
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79\r
80 //\r
a9803247 81 // Fill in the Padding fields that don't vary across resource types.\r
8aba40b7 82 //\r
a9803247 83 for (Index = 0; Index < ARRAY_SIZE (ResourcePadding->Padding); ++Index) {\r
ac0a286f 84 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
a9803247
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85\r
86 Descriptor = ResourcePadding->Padding + Index;\r
87 Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
88 Descriptor->Len = (UINT16)(\r
ac0a286f
MK
89 sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) -\r
90 OFFSET_OF (\r
91 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR,\r
92 ResType\r
93 )\r
94 );\r
a9803247 95 }\r
8aba40b7
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96\r
97 //\r
a9803247 98 // Fill in the End Tag.\r
8aba40b7 99 //\r
a9803247
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100 ResourcePadding->EndDesc.Desc = ACPI_END_TAG_DESCRIPTOR;\r
101}\r
8aba40b7 102\r
4776d5cb
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103/**\r
104 Set up a descriptor entry for reserving IO space.\r
105\r
106 @param[in,out] Descriptor The descriptor to configure. The caller shall have\r
107 initialized Descriptor earlier, with\r
108 InitializeResourcePadding().\r
109\r
110 @param[in] SizeExponent The size and natural alignment of the reservation\r
111 are determined by raising two to this power.\r
112**/\r
113STATIC\r
114VOID\r
115SetIoPadding (\r
ac0a286f
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116 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor,\r
117 IN UINTN SizeExponent\r
4776d5cb
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118 )\r
119{\r
ac0a286f
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120 Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
121 Descriptor->AddrLen = LShiftU64 (1, SizeExponent);\r
4776d5cb
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122 Descriptor->AddrRangeMax = Descriptor->AddrLen - 1;\r
123}\r
124\r
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125/**\r
126 Set up a descriptor entry for reserving MMIO space.\r
127\r
128 @param[in,out] Descriptor The descriptor to configure. The caller shall\r
129 have initialized Descriptor earlier, with\r
130 InitializeResourcePadding().\r
131\r
132 @param[in] Prefetchable TRUE if the descriptor should reserve\r
133 prefetchable MMIO space. Pass FALSE for\r
134 reserving non-prefetchable MMIO space.\r
135\r
136 @param[in] ThirtyTwoBitOnly TRUE if the reservation should be limited to\r
137 32-bit address space. FALSE if the reservation\r
138 can be satisfied from 64-bit address space.\r
139 ThirtyTwoBitOnly is ignored if Prefetchable is\r
140 FALSE; in that case ThirtyTwoBitOnly is always\r
141 considered TRUE.\r
142\r
143 @param[in] SizeExponent The size and natural alignment of the\r
144 reservation are determined by raising two to\r
145 this power.\r
146**/\r
147STATIC\r
148VOID\r
149SetMmioPadding (\r
ac0a286f
MK
150 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor,\r
151 IN BOOLEAN Prefetchable,\r
152 IN BOOLEAN ThirtyTwoBitOnly,\r
153 IN UINTN SizeExponent\r
4776d5cb
LE
154 )\r
155{\r
156 Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
157 if (Prefetchable) {\r
158 Descriptor->SpecificFlag =\r
159 EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
160 Descriptor->AddrSpaceGranularity = ThirtyTwoBitOnly ? 32 : 64;\r
161 } else {\r
162 Descriptor->SpecificFlag =\r
163 EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE;\r
164 Descriptor->AddrSpaceGranularity = 32;\r
165 }\r
ac0a286f
MK
166\r
167 Descriptor->AddrLen = LShiftU64 (1, SizeExponent);\r
4776d5cb
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168 Descriptor->AddrRangeMax = Descriptor->AddrLen - 1;\r
169}\r
170\r
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171/**\r
172 Round up a positive 32-bit value to the next whole power of two, and return\r
173 the bit position of the highest bit set in the result. Equivalent to\r
174 ceil(log2(x)).\r
175\r
176 @param[in] Operand The 32-bit operand to evaluate.\r
177\r
178 @retval -1 Operand is zero.\r
179\r
180 @retval -1 Operand is positive, not a whole power of two, and rounding it\r
181 up to the next power of two does not fit into 32 bits.\r
182\r
183 @retval 0..31 Otherwise, return ceil(log2(Value)).\r
184**/\r
185STATIC\r
186INTN\r
187HighBitSetRoundUp32 (\r
ac0a286f 188 IN UINT32 Operand\r
4776d5cb
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189 )\r
190{\r
ac0a286f 191 INTN HighBit;\r
4776d5cb
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192\r
193 HighBit = HighBitSet32 (Operand);\r
194 if (HighBit == -1) {\r
195 //\r
196 // Operand is zero.\r
197 //\r
198 return HighBit;\r
199 }\r
ac0a286f 200\r
4776d5cb
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201 if ((Operand & (Operand - 1)) != 0) {\r
202 //\r
203 // Operand is not a whole power of two.\r
204 //\r
205 ++HighBit;\r
206 }\r
ac0a286f 207\r
4776d5cb
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208 return (HighBit < 32) ? HighBit : -1;\r
209}\r
210\r
4776d5cb
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211/**\r
212 Round up a positive 64-bit value to the next whole power of two, and return\r
213 the bit position of the highest bit set in the result. Equivalent to\r
214 ceil(log2(x)).\r
215\r
216 @param[in] Operand The 64-bit operand to evaluate.\r
217\r
218 @retval -1 Operand is zero.\r
219\r
220 @retval -1 Operand is positive, not a whole power of two, and rounding it\r
221 up to the next power of two does not fit into 64 bits.\r
222\r
223 @retval 0..63 Otherwise, return ceil(log2(Value)).\r
224**/\r
225STATIC\r
226INTN\r
227HighBitSetRoundUp64 (\r
ac0a286f 228 IN UINT64 Operand\r
4776d5cb
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229 )\r
230{\r
ac0a286f 231 INTN HighBit;\r
4776d5cb
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232\r
233 HighBit = HighBitSet64 (Operand);\r
234 if (HighBit == -1) {\r
235 //\r
236 // Operand is zero.\r
237 //\r
238 return HighBit;\r
239 }\r
ac0a286f 240\r
4776d5cb
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241 if ((Operand & (Operand - 1)) != 0) {\r
242 //\r
243 // Operand is not a whole power of two.\r
244 //\r
245 ++HighBit;\r
246 }\r
ac0a286f 247\r
4776d5cb
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248 return (HighBit < 64) ? HighBit : -1;\r
249}\r
250\r
fe404947
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251/**\r
252 Look up the QEMU-specific Resource Reservation capability in the conventional\r
253 config space of a Hotplug Controller (that is, PCI Bridge).\r
254\r
3815101f 255 On error, the contents of ReservationHint are indeterminate.\r
fe404947
LE
256\r
257 @param[in] HpcPciAddress The address of the PCI Bridge -- Bus, Device,\r
258 Function -- in UEFI (not PciLib) encoding.\r
259\r
260 @param[out] ReservationHint The caller-allocated capability structure to\r
261 populate from the PCI Bridge's config space.\r
262\r
263 @retval EFI_SUCCESS The capability has been found, ReservationHint has\r
264 been populated.\r
265\r
3815101f
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266 @retval EFI_NOT_FOUND The capability is missing.\r
267\r
268 @return Error codes from PciCapPciSegmentLib and PciCapLib.\r
fe404947
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269**/\r
270STATIC\r
271EFI_STATUS\r
272QueryReservationHint (\r
ac0a286f
MK
273 IN CONST EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *HpcPciAddress,\r
274 OUT QEMU_PCI_BRIDGE_CAPABILITY_RESOURCE_RESERVATION *ReservationHint\r
275 )\r
fe404947 276{\r
ac0a286f
MK
277 UINT16 PciVendorId;\r
278 EFI_STATUS Status;\r
279 PCI_CAP_DEV *PciDevice;\r
280 PCI_CAP_LIST *CapList;\r
281 UINT16 VendorInstance;\r
282 PCI_CAP *VendorCap;\r
fe404947
LE
283\r
284 //\r
285 // Check the vendor identifier.\r
286 //\r
287 PciVendorId = PciRead16 (\r
288 PCI_LIB_ADDRESS (\r
289 HpcPciAddress->Bus,\r
290 HpcPciAddress->Device,\r
291 HpcPciAddress->Function,\r
292 PCI_VENDOR_ID_OFFSET\r
293 )\r
294 );\r
295 if (PciVendorId != QEMU_PCI_BRIDGE_VENDOR_ID_REDHAT) {\r
296 return EFI_NOT_FOUND;\r
297 }\r
298\r
299 //\r
3815101f 300 // Parse the capabilities lists.\r
fe404947 301 //\r
3815101f
LE
302 Status = PciCapPciSegmentDeviceInit (\r
303 mPciExtConfSpaceSupported ? PciCapExtended : PciCapNormal,\r
304 0, // Segment\r
305 HpcPciAddress->Bus,\r
306 HpcPciAddress->Device,\r
307 HpcPciAddress->Function,\r
308 &PciDevice\r
309 );\r
310 if (EFI_ERROR (Status)) {\r
311 return Status;\r
312 }\r
ac0a286f 313\r
3815101f
LE
314 Status = PciCapListInit (PciDevice, &CapList);\r
315 if (EFI_ERROR (Status)) {\r
316 goto UninitPciDevice;\r
fe404947
LE
317 }\r
318\r
319 //\r
3815101f
LE
320 // Scan the vendor capability instances for the Resource Reservation\r
321 // capability.\r
fe404947 322 //\r
3815101f 323 VendorInstance = 0;\r
ac0a286f
MK
324 for ( ; ;) {\r
325 UINT8 VendorLength;\r
326 UINT8 BridgeCapType;\r
3815101f
LE
327\r
328 Status = PciCapListFindCap (\r
329 CapList,\r
330 PciCapNormal,\r
331 EFI_PCI_CAPABILITY_ID_VENDOR,\r
332 VendorInstance++,\r
333 &VendorCap\r
334 );\r
335 if (EFI_ERROR (Status)) {\r
336 goto UninitCapList;\r
fe404947
LE
337 }\r
338\r
339 //\r
3815101f 340 // Check the vendor capability length.\r
fe404947 341 //\r
3815101f
LE
342 Status = PciCapRead (\r
343 PciDevice,\r
344 VendorCap,\r
345 OFFSET_OF (EFI_PCI_CAPABILITY_VENDOR_HDR, Length),\r
346 &VendorLength,\r
347 sizeof VendorLength\r
348 );\r
349 if (EFI_ERROR (Status)) {\r
350 goto UninitCapList;\r
351 }\r
ac0a286f 352\r
3815101f 353 if (VendorLength != sizeof *ReservationHint) {\r
fe404947
LE
354 continue;\r
355 }\r
356\r
357 //\r
3815101f 358 // Check the vendor bridge capability type.\r
fe404947 359 //\r
3815101f
LE
360 Status = PciCapRead (\r
361 PciDevice,\r
362 VendorCap,\r
363 OFFSET_OF (QEMU_PCI_BRIDGE_CAPABILITY_HDR, Type),\r
364 &BridgeCapType,\r
365 sizeof BridgeCapType\r
366 );\r
367 if (EFI_ERROR (Status)) {\r
368 goto UninitCapList;\r
369 }\r
ac0a286f 370\r
3815101f 371 if (BridgeCapType ==\r
ac0a286f
MK
372 QEMU_PCI_BRIDGE_CAPABILITY_TYPE_RESOURCE_RESERVATION)\r
373 {\r
3815101f
LE
374 //\r
375 // We have a match.\r
376 //\r
377 break;\r
fe404947 378 }\r
fe404947
LE
379 }\r
380\r
3815101f
LE
381 //\r
382 // Populate ReservationHint.\r
383 //\r
384 Status = PciCapRead (\r
385 PciDevice,\r
386 VendorCap,\r
387 0, // SourceOffsetInCap\r
388 ReservationHint,\r
389 sizeof *ReservationHint\r
390 );\r
391\r
392UninitCapList:\r
393 PciCapListUninit (CapList);\r
394\r
395UninitPciDevice:\r
396 PciCapPciSegmentDeviceUninit (PciDevice);\r
397\r
398 return Status;\r
fe404947
LE
399}\r
400\r
8aba40b7
LE
401/**\r
402 Returns a list of root Hot Plug Controllers (HPCs) that require\r
403 initialization during the boot process.\r
404\r
405 This procedure returns a list of root HPCs. The PCI bus driver must\r
406 initialize these controllers during the boot process. The PCI bus driver may\r
407 or may not be able to detect these HPCs. If the platform includes a\r
408 PCI-to-CardBus bridge, it can be included in this list if it requires\r
409 initialization. The HpcList must be self consistent. An HPC cannot control\r
410 any of its parent buses. Only one HPC can control a PCI bus. Because this\r
411 list includes only root HPCs, no HPC in the list can be a child of another\r
412 HPC. This policy must be enforced by the EFI_PCI_HOT_PLUG_INIT_PROTOCOL.\r
413 The PCI bus driver may not check for such invalid conditions. The callee\r
414 allocates the buffer HpcList\r
415\r
416 @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL\r
417 instance.\r
418 @param[out] HpcCount The number of root HPCs that were returned.\r
419 @param[out] HpcList The list of root HPCs. HpcCount defines the number of\r
420 elements in this list.\r
421\r
422 @retval EFI_SUCCESS HpcList was returned.\r
423 @retval EFI_OUT_OF_RESOURCES HpcList was not returned due to insufficient\r
424 resources.\r
425 @retval EFI_INVALID_PARAMETER HpcCount is NULL or HpcList is NULL.\r
426**/\r
427STATIC\r
428EFI_STATUS\r
429EFIAPI\r
430GetRootHpcList (\r
ac0a286f
MK
431 IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,\r
432 OUT UINTN *HpcCount,\r
433 OUT EFI_HPC_LOCATION **HpcList\r
8aba40b7
LE
434 )\r
435{\r
ac0a286f 436 if ((HpcCount == NULL) || (HpcList == NULL)) {\r
8aba40b7
LE
437 return EFI_INVALID_PARAMETER;\r
438 }\r
439\r
440 //\r
441 // There are no top-level (i.e., un-enumerable) hot-plug controllers in QEMU\r
442 // that would require special initialization.\r
443 //\r
444 *HpcCount = 0;\r
ac0a286f 445 *HpcList = NULL;\r
8aba40b7
LE
446 return EFI_SUCCESS;\r
447}\r
448\r
8aba40b7
LE
449/**\r
450 Initializes one root Hot Plug Controller (HPC). This process may causes\r
451 initialization of its subordinate buses.\r
452\r
453 This function initializes the specified HPC. At the end of initialization,\r
454 the hot-plug slots or sockets (controlled by this HPC) are powered and are\r
455 connected to the bus. All the necessary registers in the HPC are set up. For\r
456 a Standard (PCI) Hot Plug Controller (SHPC), the registers that must be set\r
457 up are defined in the PCI Standard Hot Plug Controller and Subsystem\r
458 Specification.\r
459\r
460 @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL\r
461 instance.\r
462 @param[in] HpcDevicePath The device path to the HPC that is being\r
463 initialized.\r
464 @param[in] HpcPciAddress The address of the HPC function on the PCI bus.\r
465 @param[in] Event The event that should be signaled when the HPC\r
466 initialization is complete. Set to NULL if the\r
467 caller wants to wait until the entire\r
468 initialization process is complete.\r
469 @param[out] HpcState The state of the HPC hardware. The state is\r
470 EFI_HPC_STATE_INITIALIZED or\r
471 EFI_HPC_STATE_ENABLED.\r
472\r
473 @retval EFI_SUCCESS If Event is NULL, the specific HPC was\r
474 successfully initialized. If Event is not\r
475 NULL, Event will be signaled at a later time\r
476 when initialization is complete.\r
477 @retval EFI_UNSUPPORTED This instance of\r
478 EFI_PCI_HOT_PLUG_INIT_PROTOCOL does not\r
479 support the specified HPC.\r
480 @retval EFI_OUT_OF_RESOURCES Initialization failed due to insufficient\r
481 resources.\r
482 @retval EFI_INVALID_PARAMETER HpcState is NULL.\r
483**/\r
484STATIC\r
485EFI_STATUS\r
486EFIAPI\r
487InitializeRootHpc (\r
ac0a286f
MK
488 IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,\r
489 IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,\r
490 IN UINT64 HpcPciAddress,\r
491 IN EFI_EVENT Event OPTIONAL,\r
492 OUT EFI_HPC_STATE *HpcState\r
8aba40b7
LE
493 )\r
494{\r
495 //\r
496 // This function should never be called, due to the information returned by\r
497 // GetRootHpcList().\r
498 //\r
499 ASSERT (FALSE);\r
500\r
501 if (HpcState == NULL) {\r
502 return EFI_INVALID_PARAMETER;\r
503 }\r
ac0a286f 504\r
8aba40b7
LE
505 return EFI_UNSUPPORTED;\r
506}\r
507\r
8aba40b7
LE
508/**\r
509 Returns the resource padding that is required by the PCI bus that is\r
510 controlled by the specified Hot Plug Controller (HPC).\r
511\r
512 This function returns the resource padding that is required by the PCI bus\r
513 that is controlled by the specified HPC. This member function is called for\r
514 all the root HPCs and nonroot HPCs that are detected by the PCI bus\r
515 enumerator. This function will be called before PCI resource allocation is\r
516 completed. This function must be called after all the root HPCs, with the\r
517 possible exception of a PCI-to-CardBus bridge, have completed\r
518 initialization.\r
519\r
520 @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL\r
521 instance.\r
522 @param[in] HpcDevicePath The device path to the HPC.\r
523 @param[in] HpcPciAddress The address of the HPC function on the PCI bus.\r
524 @param[in] HpcState The state of the HPC hardware.\r
525 @param[out] Padding The amount of resource padding that is required\r
526 by the PCI bus under the control of the specified\r
527 HPC.\r
528 @param[out] Attributes Describes how padding is accounted for. The\r
529 padding is returned in the form of ACPI 2.0\r
530 resource descriptors.\r
531\r
532 @retval EFI_SUCCESS The resource padding was successfully\r
533 returned.\r
534 @retval EFI_UNSUPPORTED This instance of the\r
535 EFI_PCI_HOT_PLUG_INIT_PROTOCOL does not\r
536 support the specified HPC.\r
537 @retval EFI_NOT_READY This function was called before HPC\r
538 initialization is complete.\r
539 @retval EFI_INVALID_PARAMETER HpcState or Padding or Attributes is NULL.\r
540 @retval EFI_OUT_OF_RESOURCES ACPI 2.0 resource descriptors for Padding\r
541 cannot be allocated due to insufficient\r
542 resources.\r
543**/\r
544STATIC\r
545EFI_STATUS\r
546EFIAPI\r
547GetResourcePadding (\r
ac0a286f
MK
548 IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,\r
549 IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,\r
550 IN UINT64 HpcPciAddress,\r
551 OUT EFI_HPC_STATE *HpcState,\r
552 OUT VOID **Padding,\r
553 OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes\r
8aba40b7
LE
554 )\r
555{\r
ac0a286f
MK
556 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *Address;\r
557 BOOLEAN DefaultIo;\r
558 BOOLEAN DefaultMmio;\r
559 RESOURCE_PADDING ReservationRequest;\r
560 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *FirstResource;\r
561 EFI_STATUS ReservationHintStatus;\r
562 QEMU_PCI_BRIDGE_CAPABILITY_RESOURCE_RESERVATION ReservationHint;\r
fe404947
LE
563\r
564 Address = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&HpcPciAddress;\r
a9803247 565\r
8e875037 566 DEBUG_CODE_BEGIN ();\r
ac0a286f
MK
567 CHAR16 *DevicePathString;\r
568\r
569 DevicePathString = ConvertDevicePathToText (HpcDevicePath, FALSE, FALSE);\r
570\r
571 DEBUG ((\r
572 DEBUG_VERBOSE,\r
573 "%a: Address=%02x:%02x.%x DevicePath=%s\n",\r
574 __FUNCTION__,\r
575 Address->Bus,\r
576 Address->Device,\r
577 Address->Function,\r
578 (DevicePathString == NULL) ? L"<unavailable>" : DevicePathString\r
579 ));\r
580\r
581 if (DevicePathString != NULL) {\r
582 FreePool (DevicePathString);\r
583 }\r
8aba40b7 584\r
8e875037 585 DEBUG_CODE_END ();\r
8aba40b7 586\r
ac0a286f 587 if ((HpcState == NULL) || (Padding == NULL) || (Attributes == NULL)) {\r
8aba40b7
LE
588 return EFI_INVALID_PARAMETER;\r
589 }\r
590\r
ac0a286f 591 DefaultIo = TRUE;\r
a9803247
LE
592 DefaultMmio = TRUE;\r
593\r
594 //\r
595 // Init ReservationRequest, and point FirstResource one past the last\r
596 // descriptor entry. We're going to build the entries backwards from\r
597 // ReservationRequest.EndDesc.\r
598 //\r
599 InitializeResourcePadding (&ReservationRequest);\r
600 FirstResource = ReservationRequest.Padding +\r
601 ARRAY_SIZE (ReservationRequest.Padding);\r
602\r
603 //\r
fe404947 604 // Try to get the QEMU-specific Resource Reservation capability.\r
a9803247 605 //\r
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606 ReservationHintStatus = QueryReservationHint (Address, &ReservationHint);\r
607 if (!EFI_ERROR (ReservationHintStatus)) {\r
ac0a286f 608 INTN HighBit;\r
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609\r
610 DEBUG ((\r
611 DEBUG_VERBOSE,\r
612 "%a: BusNumbers=0x%x Io=0x%Lx NonPrefetchable32BitMmio=0x%x\n"\r
613 "%a: Prefetchable32BitMmio=0x%x Prefetchable64BitMmio=0x%Lx\n",\r
614 __FUNCTION__,\r
615 ReservationHint.BusNumbers,\r
616 ReservationHint.Io,\r
617 ReservationHint.NonPrefetchable32BitMmio,\r
618 __FUNCTION__,\r
619 ReservationHint.Prefetchable32BitMmio,\r
620 ReservationHint.Prefetchable64BitMmio\r
621 ));\r
622\r
623 //\r
624 // (a) Reserve bus numbers.\r
625 //\r
626 switch (ReservationHint.BusNumbers) {\r
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627 case 0:\r
628 //\r
629 // No reservation needed.\r
630 //\r
631 break;\r
632 case MAX_UINT32:\r
633 //\r
634 // Firmware default (unspecified). Treat it as "no reservation needed".\r
635 //\r
636 break;\r
637 default:\r
638 //\r
639 // Request the specified amount.\r
640 //\r
641 --FirstResource;\r
642 FirstResource->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;\r
643 FirstResource->AddrLen = ReservationHint.BusNumbers;\r
644 break;\r
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645 }\r
646\r
647 //\r
648 // (b) Reserve IO space.\r
649 //\r
650 switch (ReservationHint.Io) {\r
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651 case 0:\r
652 //\r
653 // No reservation needed, disable our built-in.\r
654 //\r
fe404947 655 DefaultIo = FALSE;\r
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656 break;\r
657 case MAX_UINT64:\r
658 //\r
659 // Firmware default (unspecified). Stick with our built-in.\r
660 //\r
661 break;\r
662 default:\r
663 //\r
664 // Round the specified amount up to the next power of two. If rounding is\r
665 // successful, reserve the rounded value. Fall back to the default\r
666 // otherwise.\r
667 //\r
668 HighBit = HighBitSetRoundUp64 (ReservationHint.Io);\r
669 if (HighBit != -1) {\r
670 SetIoPadding (--FirstResource, (UINTN)HighBit);\r
671 DefaultIo = FALSE;\r
672 }\r
673\r
674 break;\r
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675 }\r
676\r
677 //\r
678 // (c) Reserve non-prefetchable MMIO space (32-bit only).\r
679 //\r
680 switch (ReservationHint.NonPrefetchable32BitMmio) {\r
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681 case 0:\r
682 //\r
683 // No reservation needed, disable our built-in.\r
684 //\r
fe404947 685 DefaultMmio = FALSE;\r
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686 break;\r
687 case MAX_UINT32:\r
688 //\r
689 // Firmware default (unspecified). Stick with our built-in.\r
690 //\r
691 break;\r
692 default:\r
693 //\r
694 // Round the specified amount up to the next power of two. If rounding is\r
695 // successful, reserve the rounded value. Fall back to the default\r
696 // otherwise.\r
697 //\r
698 HighBit = HighBitSetRoundUp32 (ReservationHint.NonPrefetchable32BitMmio);\r
699 if (HighBit != -1) {\r
700 SetMmioPadding (--FirstResource, FALSE, TRUE, (UINTN)HighBit);\r
701 DefaultMmio = FALSE;\r
702 }\r
703\r
704 break;\r
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705 }\r
706\r
707 //\r
708 // (d) Reserve prefetchable MMIO space (either 32-bit or 64-bit, never\r
709 // both).\r
710 //\r
711 // For either space, we treat 0 as "no reservation needed", and the maximum\r
712 // value as "firmware default". The latter is unspecified, and we interpret\r
713 // it as the former.\r
714 //\r
715 // Otherwise, round the specified amount up to the next power of two. If\r
716 // rounding is successful, reserve the rounded value. Do not reserve\r
717 // prefetchable MMIO space otherwise.\r
718 //\r
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719 if ((ReservationHint.Prefetchable32BitMmio > 0) &&\r
720 (ReservationHint.Prefetchable32BitMmio < MAX_UINT32))\r
721 {\r
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722 HighBit = HighBitSetRoundUp32 (ReservationHint.Prefetchable32BitMmio);\r
723 if (HighBit != -1) {\r
724 SetMmioPadding (--FirstResource, TRUE, TRUE, (UINTN)HighBit);\r
725 }\r
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726 } else if ((ReservationHint.Prefetchable64BitMmio > 0) &&\r
727 (ReservationHint.Prefetchable64BitMmio < MAX_UINT64))\r
728 {\r
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729 HighBit = HighBitSetRoundUp64 (ReservationHint.Prefetchable64BitMmio);\r
730 if (HighBit != -1) {\r
731 SetMmioPadding (--FirstResource, TRUE, FALSE, (UINTN)HighBit);\r
732 }\r
733 }\r
734 }\r
735\r
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736 if (DefaultIo) {\r
737 //\r
738 // Request defaults.\r
739 //\r
4776d5cb 740 SetIoPadding (--FirstResource, (UINTN)HighBitSetRoundUp64 (512));\r
a9803247
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741 }\r
742\r
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743 if (DefaultMmio) {\r
744 //\r
745 // Request defaults.\r
746 //\r
4776d5cb
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747 SetMmioPadding (\r
748 --FirstResource,\r
749 FALSE,\r
750 TRUE,\r
751 (UINTN)HighBitSetRoundUp32 (SIZE_2MB)\r
752 );\r
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753 }\r
754\r
755 //\r
756 // Output a copy of ReservationRequest from the lowest-address populated\r
757 // entry until the end of the structure (including\r
758 // ReservationRequest.EndDesc). If no reservations are necessary, we'll only\r
759 // output the End Tag.\r
760 //\r
761 *Padding = AllocateCopyPool (\r
762 (UINT8 *)(&ReservationRequest + 1) - (UINT8 *)FirstResource,\r
763 FirstResource\r
764 );\r
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765 if (*Padding == NULL) {\r
766 return EFI_OUT_OF_RESOURCES;\r
767 }\r
768\r
769 //\r
770 // Resource padding is required.\r
771 //\r
772 *HpcState = EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED;\r
773\r
774 //\r
775 // The padding should be applied at PCI bus level, and considered by upstream\r
776 // bridges, recursively.\r
777 //\r
778 *Attributes = EfiPaddingPciBus;\r
779 return EFI_SUCCESS;\r
780}\r
781\r
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782/**\r
783 Entry point for this driver.\r
784\r
785 @param[in] ImageHandle Image handle of this driver.\r
786 @param[in] SystemTable Pointer to SystemTable.\r
787\r
788 @retval EFI_SUCESS Driver has loaded successfully.\r
789 @return Error codes from lower level functions.\r
790\r
791**/\r
792EFI_STATUS\r
793EFIAPI\r
794DriverInitialize (\r
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795 IN EFI_HANDLE ImageHandle,\r
796 IN EFI_SYSTEM_TABLE *SystemTable\r
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797 )\r
798{\r
ac0a286f 799 EFI_STATUS Status;\r
8aba40b7 800\r
3815101f
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801 mPciExtConfSpaceSupported = (PcdGet16 (PcdOvmfHostBridgePciDevId) ==\r
802 INTEL_Q35_MCH_DEVICE_ID);\r
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803 mPciHotPlugInit.GetRootHpcList = GetRootHpcList;\r
804 mPciHotPlugInit.InitializeRootHpc = InitializeRootHpc;\r
8aba40b7 805 mPciHotPlugInit.GetResourcePadding = GetResourcePadding;\r
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806 Status = gBS->InstallMultipleProtocolInterfaces (\r
807 &ImageHandle,\r
808 &gEfiPciHotPlugInitProtocolGuid,\r
809 &mPciHotPlugInit,\r
810 NULL\r
811 );\r
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812 return Status;\r
813}\r