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49ba9447 | 1 | /**@file\r |
2 | Memory Detection for Virtual Machines.\r | |
3 | \r | |
035ce3b3 | 4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
b26f0cf9 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
49ba9447 | 6 | \r |
7 | Module Name:\r | |
8 | \r | |
9 | MemDetect.c\r | |
10 | \r | |
11 | **/\r | |
12 | \r | |
13 | //\r | |
14 | // The package level header files this module uses\r | |
15 | //\r | |
1fceaddb | 16 | #include <IndustryStandard/E820.h>\r |
49edde15 | 17 | #include <IndustryStandard/I440FxPiix4.h>\r |
d5e06444 | 18 | #include <IndustryStandard/Q35MchIch9.h>\r |
49ba9447 | 19 | #include <PiPei.h>\r |
adec2bd5 | 20 | #include <Register/Intel/SmramSaveStateMap.h>\r |
49ba9447 | 21 | \r |
22 | //\r | |
23 | // The Library classes this module consumes\r | |
24 | //\r | |
d5e06444 | 25 | #include <Library/BaseLib.h>\r |
6a7cba79 | 26 | #include <Library/BaseMemoryLib.h>\r |
49ba9447 | 27 | #include <Library/DebugLib.h>\r |
28 | #include <Library/HobLib.h>\r | |
29 | #include <Library/IoLib.h>\r | |
0bbed066 | 30 | #include <Library/MemEncryptSevLib.h>\r |
c1c2669c | 31 | #include <Library/PcdLib.h>\r |
d5e06444 | 32 | #include <Library/PciLib.h>\r |
49ba9447 | 33 | #include <Library/PeimEntryPoint.h>\r |
34 | #include <Library/ResourcePublicationLib.h>\r | |
e8e5cd4a | 35 | #include <Library/MtrrLib.h>\r |
7e5b1b67 | 36 | #include <Library/QemuFwCfgLib.h>\r |
98800cce | 37 | #include <Library/QemuFwCfgSimpleParserLib.h>\r |
49ba9447 | 38 | \r |
39 | #include "Platform.h"\r | |
40 | #include "Cmos.h"\r | |
41 | \r | |
ac0a286f | 42 | UINT8 mPhysMemAddressWidth;\r |
bc89fe48 | 43 | \r |
ac0a286f MK |
44 | STATIC UINT32 mS3AcpiReservedMemoryBase;\r |
45 | STATIC UINT32 mS3AcpiReservedMemorySize;\r | |
45d87081 | 46 | \r |
ac0a286f | 47 | STATIC UINT16 mQ35TsegMbytes;\r |
23bfb5c0 | 48 | \r |
ac0a286f | 49 | BOOLEAN mQ35SmramAtDefaultSmbase;\r |
73974f80 | 50 | \r |
ac0a286f | 51 | UINT32 mQemuUc32Base;\r |
49edde15 | 52 | \r |
23bfb5c0 LE |
53 | VOID\r |
54 | Q35TsegMbytesInitialization (\r | |
55 | VOID\r | |
56 | )\r | |
57 | {\r | |
ac0a286f MK |
58 | UINT16 ExtendedTsegMbytes;\r |
59 | RETURN_STATUS PcdStatus;\r | |
d5e06444 | 60 | \r |
e0ed7a9b | 61 | ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r |
d5e06444 LE |
62 | \r |
63 | //\r | |
64 | // Check if QEMU offers an extended TSEG.\r | |
65 | //\r | |
66 | // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB\r | |
67 | // register, and reading back the register.\r | |
68 | //\r | |
69 | // On a QEMU machine type that does not offer an extended TSEG, the initial\r | |
70 | // write overwrites whatever value a malicious guest OS may have placed in\r | |
71 | // the (unimplemented) register, before entering S3 or rebooting.\r | |
72 | // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.\r | |
73 | //\r | |
74 | // On a QEMU machine type that offers an extended TSEG, the initial write\r | |
75 | // triggers an update to the register. Subsequently, the value read back\r | |
76 | // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the\r | |
77 | // number of megabytes.\r | |
78 | //\r | |
79 | PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);\r | |
80 | ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));\r | |
81 | if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {\r | |
82 | mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r | |
83 | return;\r | |
84 | }\r | |
85 | \r | |
86 | DEBUG ((\r | |
87 | DEBUG_INFO,\r | |
88 | "%a: QEMU offers an extended TSEG (%d MB)\n",\r | |
89 | __FUNCTION__,\r | |
90 | ExtendedTsegMbytes\r | |
91 | ));\r | |
92 | PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);\r | |
93 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
94 | mQ35TsegMbytes = ExtendedTsegMbytes;\r | |
23bfb5c0 LE |
95 | }\r |
96 | \r | |
73974f80 LE |
97 | VOID\r |
98 | Q35SmramAtDefaultSmbaseInitialization (\r | |
99 | VOID\r | |
100 | )\r | |
101 | {\r | |
ac0a286f | 102 | RETURN_STATUS PcdStatus;\r |
73974f80 LE |
103 | \r |
104 | ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r | |
105 | \r | |
106 | mQ35SmramAtDefaultSmbase = FALSE;\r | |
75839f97 | 107 | if (FeaturePcdGet (PcdCsmEnable)) {\r |
ac0a286f MK |
108 | DEBUG ((\r |
109 | DEBUG_INFO,\r | |
110 | "%a: SMRAM at default SMBASE not checked due to CSM\n",\r | |
111 | __FUNCTION__\r | |
112 | ));\r | |
75839f97 | 113 | } else {\r |
ac0a286f MK |
114 | UINTN CtlReg;\r |
115 | UINT8 CtlRegVal;\r | |
75839f97 LE |
116 | \r |
117 | CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);\r | |
118 | PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);\r | |
ac0a286f | 119 | CtlRegVal = PciRead8 (CtlReg);\r |
75839f97 LE |
120 | mQ35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==\r |
121 | MCH_DEFAULT_SMBASE_IN_RAM);\r | |
ac0a286f MK |
122 | DEBUG ((\r |
123 | DEBUG_INFO,\r | |
124 | "%a: SMRAM at default SMBASE %a\n",\r | |
125 | __FUNCTION__,\r | |
126 | mQ35SmramAtDefaultSmbase ? "found" : "not found"\r | |
127 | ));\r | |
75839f97 LE |
128 | }\r |
129 | \r | |
ac0a286f MK |
130 | PcdStatus = PcdSetBoolS (\r |
131 | PcdQ35SmramAtDefaultSmbase,\r | |
132 | mQ35SmramAtDefaultSmbase\r | |
133 | );\r | |
73974f80 LE |
134 | ASSERT_RETURN_ERROR (PcdStatus);\r |
135 | }\r | |
136 | \r | |
49edde15 LE |
137 | VOID\r |
138 | QemuUc32BaseInitialization (\r | |
139 | VOID\r | |
140 | )\r | |
141 | {\r | |
ac0a286f MK |
142 | UINT32 LowerMemorySize;\r |
143 | UINT32 Uc32Size;\r | |
49edde15 | 144 | \r |
6a8e9ad2 GH |
145 | if (mHostBridgeDevId == 0xffff /* microvm */) {\r |
146 | return;\r | |
147 | }\r | |
148 | \r | |
49edde15 LE |
149 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
150 | //\r | |
151 | // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,\r | |
152 | // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for\r | |
153 | // setting PcdPciExpressBaseAddress such that describing the\r | |
154 | // [PcdPciExpressBaseAddress, 4GB) range require a very small number of\r | |
155 | // variable MTRRs (preferably 1 or 2).\r | |
156 | //\r | |
157 | ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);\r | |
158 | mQemuUc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
159 | return;\r | |
160 | }\r | |
161 | \r | |
162 | ASSERT (mHostBridgeDevId == INTEL_82441_DEVICE_ID);\r | |
163 | //\r | |
164 | // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one\r | |
165 | // variable MTRR suffices by truncating the size to a whole power of two,\r | |
166 | // while keeping the end affixed to 4GB. This will round the base up.\r | |
167 | //\r | |
168 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r | |
ac0a286f MK |
169 | Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));\r |
170 | mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);\r | |
49edde15 LE |
171 | //\r |
172 | // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.\r | |
173 | // Therefore mQemuUc32Base is at least 2GB.\r | |
174 | //\r | |
175 | ASSERT (mQemuUc32Base >= BASE_2GB);\r | |
176 | \r | |
177 | if (mQemuUc32Base != LowerMemorySize) {\r | |
ac0a286f MK |
178 | DEBUG ((\r |
179 | DEBUG_VERBOSE,\r | |
180 | "%a: rounded UC32 base from 0x%x up to 0x%x, for "\r | |
181 | "an UC32 size of 0x%x\n",\r | |
182 | __FUNCTION__,\r | |
183 | LowerMemorySize,\r | |
184 | mQemuUc32Base,\r | |
185 | Uc32Size\r | |
186 | ));\r | |
49edde15 LE |
187 | }\r |
188 | }\r | |
189 | \r | |
1fceaddb LE |
190 | /**\r |
191 | Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside\r | |
192 | of the 32-bit address range.\r | |
193 | \r | |
194 | Find the highest exclusive >=4GB RAM address, or produce memory resource\r | |
195 | descriptor HOBs for RAM entries that start at or above 4GB.\r | |
196 | \r | |
197 | @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ram()\r | |
198 | produces memory resource descriptor HOBs for RAM\r | |
199 | entries that start at or above 4GB.\r | |
200 | \r | |
201 | Otherwise, MaxAddress holds the highest exclusive\r | |
202 | >=4GB RAM address on output. If QEMU's fw_cfg E820\r | |
203 | RAM map contains no RAM entry that starts outside of\r | |
204 | the 32-bit address range, then MaxAddress is exactly\r | |
205 | 4GB on output.\r | |
206 | \r | |
207 | @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.\r | |
208 | \r | |
209 | @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a\r | |
210 | whole multiple of sizeof(EFI_E820_ENTRY64). No\r | |
211 | RAM entry was processed.\r | |
212 | \r | |
213 | @return Error codes from QemuFwCfgFindFile(). No RAM\r | |
214 | entry was processed.\r | |
215 | **/\r | |
216 | STATIC\r | |
217 | EFI_STATUS\r | |
218 | ScanOrAdd64BitE820Ram (\r | |
ac0a286f | 219 | OUT UINT64 *MaxAddress OPTIONAL\r |
1fceaddb LE |
220 | )\r |
221 | {\r | |
ac0a286f MK |
222 | EFI_STATUS Status;\r |
223 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
224 | UINTN FwCfgSize;\r | |
225 | EFI_E820_ENTRY64 E820Entry;\r | |
226 | UINTN Processed;\r | |
1fceaddb LE |
227 | \r |
228 | Status = QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize);\r | |
229 | if (EFI_ERROR (Status)) {\r | |
230 | return Status;\r | |
231 | }\r | |
ac0a286f | 232 | \r |
1fceaddb LE |
233 | if (FwCfgSize % sizeof E820Entry != 0) {\r |
234 | return EFI_PROTOCOL_ERROR;\r | |
235 | }\r | |
236 | \r | |
237 | if (MaxAddress != NULL) {\r | |
238 | *MaxAddress = BASE_4GB;\r | |
239 | }\r | |
240 | \r | |
241 | QemuFwCfgSelectItem (FwCfgItem);\r | |
242 | for (Processed = 0; Processed < FwCfgSize; Processed += sizeof E820Entry) {\r | |
243 | QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry);\r | |
244 | DEBUG ((\r | |
245 | DEBUG_VERBOSE,\r | |
246 | "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",\r | |
247 | __FUNCTION__,\r | |
248 | E820Entry.BaseAddr,\r | |
249 | E820Entry.Length,\r | |
250 | E820Entry.Type\r | |
251 | ));\r | |
ac0a286f MK |
252 | if ((E820Entry.Type == EfiAcpiAddressRangeMemory) &&\r |
253 | (E820Entry.BaseAddr >= BASE_4GB))\r | |
254 | {\r | |
1fceaddb | 255 | if (MaxAddress == NULL) {\r |
ac0a286f MK |
256 | UINT64 Base;\r |
257 | UINT64 End;\r | |
1fceaddb LE |
258 | \r |
259 | //\r | |
260 | // Round up the start address, and round down the end address.\r | |
261 | //\r | |
262 | Base = ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE);\r | |
ac0a286f MK |
263 | End = (E820Entry.BaseAddr + E820Entry.Length) &\r |
264 | ~(UINT64)EFI_PAGE_MASK;\r | |
1fceaddb LE |
265 | if (Base < End) {\r |
266 | AddMemoryRangeHob (Base, End);\r | |
267 | DEBUG ((\r | |
268 | DEBUG_VERBOSE,\r | |
269 | "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",\r | |
270 | __FUNCTION__,\r | |
271 | Base,\r | |
272 | End\r | |
273 | ));\r | |
274 | }\r | |
275 | } else {\r | |
ac0a286f | 276 | UINT64 Candidate;\r |
1fceaddb LE |
277 | \r |
278 | Candidate = E820Entry.BaseAddr + E820Entry.Length;\r | |
279 | if (Candidate > *MaxAddress) {\r | |
280 | *MaxAddress = Candidate;\r | |
281 | DEBUG ((\r | |
282 | DEBUG_VERBOSE,\r | |
283 | "%a: MaxAddress=0x%Lx\n",\r | |
284 | __FUNCTION__,\r | |
285 | *MaxAddress\r | |
286 | ));\r | |
287 | }\r | |
288 | }\r | |
289 | }\r | |
290 | }\r | |
ac0a286f | 291 | \r |
1fceaddb LE |
292 | return EFI_SUCCESS;\r |
293 | }\r | |
294 | \r | |
4b455f7b | 295 | UINT32\r |
c0e10976 | 296 | GetSystemMemorySizeBelow4gb (\r |
4b455f7b | 297 | VOID\r |
49ba9447 | 298 | )\r |
299 | {\r | |
ac0a286f MK |
300 | UINT8 Cmos0x34;\r |
301 | UINT8 Cmos0x35;\r | |
49ba9447 | 302 | \r |
303 | //\r | |
304 | // CMOS 0x34/0x35 specifies the system memory above 16 MB.\r | |
305 | // * CMOS(0x35) is the high byte\r | |
306 | // * CMOS(0x34) is the low byte\r | |
307 | // * The size is specified in 64kb chunks\r | |
308 | // * Since this is memory above 16MB, the 16MB must be added\r | |
309 | // into the calculation to get the total memory size.\r | |
310 | //\r | |
311 | \r | |
ac0a286f MK |
312 | Cmos0x34 = (UINT8)CmosRead8 (0x34);\r |
313 | Cmos0x35 = (UINT8)CmosRead8 (0x35);\r | |
49ba9447 | 314 | \r |
ac0a286f | 315 | return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r |
49ba9447 | 316 | }\r |
317 | \r | |
c0e10976 | 318 | STATIC\r |
319 | UINT64\r | |
320 | GetSystemMemorySizeAbove4gb (\r | |
321 | )\r | |
322 | {\r | |
ac0a286f MK |
323 | UINT32 Size;\r |
324 | UINTN CmosIndex;\r | |
c0e10976 | 325 | \r |
326 | //\r | |
327 | // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.\r | |
328 | // * CMOS(0x5d) is the most significant size byte\r | |
329 | // * CMOS(0x5c) is the middle size byte\r | |
330 | // * CMOS(0x5b) is the least significant size byte\r | |
331 | // * The size is specified in 64kb chunks\r | |
332 | //\r | |
333 | \r | |
334 | Size = 0;\r | |
335 | for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {\r | |
ac0a286f | 336 | Size = (UINT32)(Size << 8) + (UINT32)CmosRead8 (CmosIndex);\r |
c0e10976 | 337 | }\r |
338 | \r | |
339 | return LShiftU64 (Size, 16);\r | |
340 | }\r | |
341 | \r | |
d5371680 LE |
342 | /**\r |
343 | Return the highest address that DXE could possibly use, plus one.\r | |
344 | **/\r | |
345 | STATIC\r | |
346 | UINT64\r | |
347 | GetFirstNonAddress (\r | |
348 | VOID\r | |
349 | )\r | |
350 | {\r | |
ac0a286f MK |
351 | UINT64 FirstNonAddress;\r |
352 | UINT64 Pci64Base, Pci64Size;\r | |
353 | UINT32 FwCfgPciMmio64Mb;\r | |
354 | EFI_STATUS Status;\r | |
355 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
356 | UINTN FwCfgSize;\r | |
357 | UINT64 HotPlugMemoryEnd;\r | |
358 | RETURN_STATUS PcdStatus;\r | |
d5371680 | 359 | \r |
1fceaddb LE |
360 | //\r |
361 | // set FirstNonAddress to suppress incorrect compiler/analyzer warnings\r | |
362 | //\r | |
363 | FirstNonAddress = 0;\r | |
364 | \r | |
365 | //\r | |
366 | // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM\r | |
367 | // address from it. This can express an address >= 4GB+1TB.\r | |
368 | //\r | |
369 | // Otherwise, get the flat size of the memory above 4GB from the CMOS (which\r | |
370 | // can only express a size smaller than 1TB), and add it to 4GB.\r | |
371 | //\r | |
372 | Status = ScanOrAdd64BitE820Ram (&FirstNonAddress);\r | |
373 | if (EFI_ERROR (Status)) {\r | |
374 | FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r | |
375 | }\r | |
7e5b1b67 LE |
376 | \r |
377 | //\r | |
378 | // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r | |
379 | // resources to 32-bit anyway. See DegradeResource() in\r | |
380 | // "PciResourceSupport.c".\r | |
381 | //\r | |
ac0a286f | 382 | #ifdef MDE_CPU_IA32\r |
7e5b1b67 LE |
383 | if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r |
384 | return FirstNonAddress;\r | |
385 | }\r | |
ac0a286f MK |
386 | \r |
387 | #endif\r | |
7e5b1b67 LE |
388 | \r |
389 | //\r | |
390 | // Otherwise, in order to calculate the highest address plus one, we must\r | |
391 | // consider the 64-bit PCI host aperture too. Fetch the default size.\r | |
392 | //\r | |
393 | Pci64Size = PcdGet64 (PcdPciMmio64Size);\r | |
394 | \r | |
395 | //\r | |
396 | // See if the user specified the number of megabytes for the 64-bit PCI host\r | |
98800cce | 397 | // aperture. Accept an aperture size up to 16TB.\r |
7e5b1b67 LE |
398 | //\r |
399 | // As signaled by the "X-" prefix, this knob is experimental, and might go\r | |
400 | // away at any time.\r | |
401 | //\r | |
ac0a286f MK |
402 | Status = QemuFwCfgParseUint32 (\r |
403 | "opt/ovmf/X-PciMmio64Mb",\r | |
404 | FALSE,\r | |
405 | &FwCfgPciMmio64Mb\r | |
406 | );\r | |
98800cce | 407 | switch (Status) {\r |
ac0a286f MK |
408 | case EFI_UNSUPPORTED:\r |
409 | case EFI_NOT_FOUND:\r | |
98800cce | 410 | break;\r |
ac0a286f MK |
411 | case EFI_SUCCESS:\r |
412 | if (FwCfgPciMmio64Mb <= 0x1000000) {\r | |
413 | Pci64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);\r | |
414 | break;\r | |
415 | }\r | |
416 | \r | |
98800cce LE |
417 | //\r |
418 | // fall through\r | |
419 | //\r | |
ac0a286f MK |
420 | default:\r |
421 | DEBUG ((\r | |
422 | DEBUG_WARN,\r | |
423 | "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",\r | |
424 | __FUNCTION__\r | |
425 | ));\r | |
426 | break;\r | |
7e5b1b67 LE |
427 | }\r |
428 | \r | |
429 | if (Pci64Size == 0) {\r | |
430 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
ac0a286f MK |
431 | DEBUG ((\r |
432 | DEBUG_INFO,\r | |
433 | "%a: disabling 64-bit PCI host aperture\n",\r | |
434 | __FUNCTION__\r | |
435 | ));\r | |
32e083c7 LE |
436 | PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r |
437 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
7e5b1b67 LE |
438 | }\r |
439 | \r | |
440 | //\r | |
441 | // There's nothing more to do; the amount of memory above 4GB fully\r | |
442 | // determines the highest address plus one. The memory hotplug area (see\r | |
443 | // below) plays no role for the firmware in this case.\r | |
444 | //\r | |
445 | return FirstNonAddress;\r | |
446 | }\r | |
447 | \r | |
448 | //\r | |
449 | // The "etc/reserved-memory-end" fw_cfg file, when present, contains an\r | |
450 | // absolute, exclusive end address for the memory hotplug area. This area\r | |
451 | // starts right at the end of the memory above 4GB. The 64-bit PCI host\r | |
452 | // aperture must be placed above it.\r | |
453 | //\r | |
ac0a286f MK |
454 | Status = QemuFwCfgFindFile (\r |
455 | "etc/reserved-memory-end",\r | |
456 | &FwCfgItem,\r | |
457 | &FwCfgSize\r | |
458 | );\r | |
459 | if (!EFI_ERROR (Status) && (FwCfgSize == sizeof HotPlugMemoryEnd)) {\r | |
7e5b1b67 LE |
460 | QemuFwCfgSelectItem (FwCfgItem);\r |
461 | QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd);\r | |
ac0a286f MK |
462 | DEBUG ((\r |
463 | DEBUG_VERBOSE,\r | |
464 | "%a: HotPlugMemoryEnd=0x%Lx\n",\r | |
465 | __FUNCTION__,\r | |
466 | HotPlugMemoryEnd\r | |
467 | ));\r | |
7e5b1b67 LE |
468 | \r |
469 | ASSERT (HotPlugMemoryEnd >= FirstNonAddress);\r | |
470 | FirstNonAddress = HotPlugMemoryEnd;\r | |
471 | }\r | |
472 | \r | |
473 | //\r | |
474 | // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so\r | |
475 | // that the host can map it with 1GB hugepages. Follow suit.\r | |
476 | //\r | |
477 | Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);\r | |
478 | Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);\r | |
479 | \r | |
480 | //\r | |
481 | // The 64-bit PCI host aperture should also be "naturally" aligned. The\r | |
482 | // alignment is determined by rounding the size of the aperture down to the\r | |
483 | // next smaller or equal power of two. That is, align the aperture by the\r | |
484 | // largest BAR size that can fit into it.\r | |
485 | //\r | |
486 | Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));\r | |
487 | \r | |
488 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
489 | //\r | |
490 | // The core PciHostBridgeDxe driver will automatically add this range to\r | |
491 | // the GCD memory space map through our PciHostBridgeLib instance; here we\r | |
492 | // only need to set the PCDs.\r | |
493 | //\r | |
32e083c7 LE |
494 | PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);\r |
495 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
496 | PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);\r | |
497 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
498 | \r | |
ac0a286f MK |
499 | DEBUG ((\r |
500 | DEBUG_INFO,\r | |
501 | "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r | |
502 | __FUNCTION__,\r | |
503 | Pci64Base,\r | |
504 | Pci64Size\r | |
505 | ));\r | |
7e5b1b67 LE |
506 | }\r |
507 | \r | |
508 | //\r | |
509 | // The useful address space ends with the 64-bit PCI host aperture.\r | |
510 | //\r | |
511 | FirstNonAddress = Pci64Base + Pci64Size;\r | |
d5371680 LE |
512 | return FirstNonAddress;\r |
513 | }\r | |
514 | \r | |
bc89fe48 LE |
515 | /**\r |
516 | Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r | |
517 | **/\r | |
518 | VOID\r | |
519 | AddressWidthInitialization (\r | |
520 | VOID\r | |
521 | )\r | |
522 | {\r | |
ac0a286f | 523 | UINT64 FirstNonAddress;\r |
bc89fe48 LE |
524 | \r |
525 | //\r | |
526 | // As guest-physical memory size grows, the permanent PEI RAM requirements\r | |
527 | // are dominated by the identity-mapping page tables built by the DXE IPL.\r | |
528 | // The DXL IPL keys off of the physical address bits advertized in the CPU\r | |
529 | // HOB. To conserve memory, we calculate the minimum address width here.\r | |
530 | //\r | |
d5371680 | 531 | FirstNonAddress = GetFirstNonAddress ();\r |
bc89fe48 LE |
532 | mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r |
533 | \r | |
534 | //\r | |
535 | // If FirstNonAddress is not an integral power of two, then we need an\r | |
536 | // additional bit.\r | |
537 | //\r | |
538 | if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {\r | |
539 | ++mPhysMemAddressWidth;\r | |
540 | }\r | |
541 | \r | |
542 | //\r | |
543 | // The minimum address width is 36 (covers up to and excluding 64 GB, which\r | |
544 | // is the maximum for Ia32 + PAE). The theoretical architecture maximum for\r | |
545 | // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We\r | |
546 | // can simply assert that here, since 48 bits are good enough for 256 TB.\r | |
547 | //\r | |
548 | if (mPhysMemAddressWidth <= 36) {\r | |
549 | mPhysMemAddressWidth = 36;\r | |
550 | }\r | |
ac0a286f | 551 | \r |
bc89fe48 LE |
552 | ASSERT (mPhysMemAddressWidth <= 48);\r |
553 | }\r | |
554 | \r | |
bc89fe48 LE |
555 | /**\r |
556 | Calculate the cap for the permanent PEI memory.\r | |
557 | **/\r | |
558 | STATIC\r | |
559 | UINT32\r | |
560 | GetPeiMemoryCap (\r | |
561 | VOID\r | |
562 | )\r | |
563 | {\r | |
ac0a286f MK |
564 | BOOLEAN Page1GSupport;\r |
565 | UINT32 RegEax;\r | |
566 | UINT32 RegEdx;\r | |
567 | UINT32 Pml4Entries;\r | |
568 | UINT32 PdpEntries;\r | |
569 | UINTN TotalPages;\r | |
bc89fe48 LE |
570 | \r |
571 | //\r | |
572 | // If DXE is 32-bit, then just return the traditional 64 MB cap.\r | |
573 | //\r | |
ac0a286f | 574 | #ifdef MDE_CPU_IA32\r |
bc89fe48 LE |
575 | if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r |
576 | return SIZE_64MB;\r | |
577 | }\r | |
ac0a286f MK |
578 | \r |
579 | #endif\r | |
bc89fe48 LE |
580 | \r |
581 | //\r | |
582 | // Dependent on physical address width, PEI memory allocations can be\r | |
583 | // dominated by the page tables built for 64-bit DXE. So we key the cap off\r | |
584 | // of those. The code below is based on CreateIdentityMappingPageTables() in\r | |
585 | // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".\r | |
586 | //\r | |
587 | Page1GSupport = FALSE;\r | |
588 | if (PcdGetBool (PcdUse1GPageTable)) {\r | |
589 | AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r | |
590 | if (RegEax >= 0x80000001) {\r | |
591 | AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r | |
592 | if ((RegEdx & BIT26) != 0) {\r | |
593 | Page1GSupport = TRUE;\r | |
594 | }\r | |
595 | }\r | |
596 | }\r | |
597 | \r | |
598 | if (mPhysMemAddressWidth <= 39) {\r | |
599 | Pml4Entries = 1;\r | |
ac0a286f | 600 | PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r |
bc89fe48 LE |
601 | ASSERT (PdpEntries <= 0x200);\r |
602 | } else {\r | |
603 | Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r | |
604 | ASSERT (Pml4Entries <= 0x200);\r | |
605 | PdpEntries = 512;\r | |
606 | }\r | |
607 | \r | |
608 | TotalPages = Page1GSupport ? Pml4Entries + 1 :\r | |
ac0a286f | 609 | (PdpEntries + 1) * Pml4Entries + 1;\r |
bc89fe48 LE |
610 | ASSERT (TotalPages <= 0x40201);\r |
611 | \r | |
612 | //\r | |
613 | // Add 64 MB for miscellaneous allocations. Note that for\r | |
614 | // mPhysMemAddressWidth values close to 36, the cap will actually be\r | |
615 | // dominated by this increment.\r | |
616 | //\r | |
617 | return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r | |
618 | }\r | |
619 | \r | |
36658fff WL |
620 | /**\r |
621 | Publish PEI core memory\r | |
622 | \r | |
623 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
624 | \r | |
625 | **/\r | |
626 | EFI_STATUS\r | |
627 | PublishPeiMemory (\r | |
628 | VOID\r | |
629 | )\r | |
630 | {\r | |
ac0a286f MK |
631 | EFI_STATUS Status;\r |
632 | EFI_PHYSICAL_ADDRESS MemoryBase;\r | |
633 | UINT64 MemorySize;\r | |
634 | UINT32 LowerMemorySize;\r | |
635 | UINT32 PeiMemoryCap;\r | |
36658fff | 636 | \r |
45d87081 LE |
637 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r |
638 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
639 | //\r | |
640 | // TSEG is chipped from the end of low RAM\r | |
641 | //\r | |
23bfb5c0 | 642 | LowerMemorySize -= mQ35TsegMbytes * SIZE_1MB;\r |
45d87081 LE |
643 | }\r |
644 | \r | |
645 | //\r | |
646 | // If S3 is supported, then the S3 permanent PEI memory is placed next,\r | |
647 | // downwards. Its size is primarily dictated by CpuMpPei. The formula below\r | |
648 | // is an approximation.\r | |
649 | //\r | |
650 | if (mS3Supported) {\r | |
651 | mS3AcpiReservedMemorySize = SIZE_512KB +\r | |
ac0a286f MK |
652 | mMaxCpuCount *\r |
653 | PcdGet32 (PcdCpuApStackSize);\r | |
45d87081 | 654 | mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;\r |
ac0a286f | 655 | LowerMemorySize = mS3AcpiReservedMemoryBase;\r |
45d87081 LE |
656 | }\r |
657 | \r | |
8e54500f | 658 | if (mBootMode == BOOT_ON_S3_RESUME) {\r |
45d87081 LE |
659 | MemoryBase = mS3AcpiReservedMemoryBase;\r |
660 | MemorySize = mS3AcpiReservedMemorySize;\r | |
8e54500f | 661 | } else {\r |
bc89fe48 | 662 | PeiMemoryCap = GetPeiMemoryCap ();\r |
ac0a286f MK |
663 | DEBUG ((\r |
664 | DEBUG_INFO,\r | |
665 | "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r | |
666 | __FUNCTION__,\r | |
667 | mPhysMemAddressWidth,\r | |
668 | PeiMemoryCap >> 10\r | |
669 | ));\r | |
bc89fe48 | 670 | \r |
8e54500f JJ |
671 | //\r |
672 | // Determine the range of memory to use during PEI\r | |
673 | //\r | |
efb0f16e LE |
674 | // Technically we could lay the permanent PEI RAM over SEC's temporary\r |
675 | // decompression and scratch buffer even if "secure S3" is needed, since\r | |
676 | // their lifetimes don't overlap. However, PeiFvInitialization() will cover\r | |
677 | // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory\r | |
678 | // allocation HOB, and other allocations served from the permanent PEI RAM\r | |
679 | // shouldn't overlap with that HOB.\r | |
680 | //\r | |
681 | MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?\r | |
ac0a286f MK |
682 | PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r |
683 | PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r | |
8e54500f | 684 | MemorySize = LowerMemorySize - MemoryBase;\r |
bc89fe48 LE |
685 | if (MemorySize > PeiMemoryCap) {\r |
686 | MemoryBase = LowerMemorySize - PeiMemoryCap;\r | |
687 | MemorySize = PeiMemoryCap;\r | |
8e54500f | 688 | }\r |
36658fff WL |
689 | }\r |
690 | \r | |
adec2bd5 LE |
691 | //\r |
692 | // MEMFD_BASE_ADDRESS separates the SMRAM at the default SMBASE from the\r | |
693 | // normal boot permanent PEI RAM. Regarding the S3 boot path, the S3\r | |
694 | // permanent PEI RAM is located even higher.\r | |
695 | //\r | |
696 | if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {\r | |
697 | ASSERT (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE <= MemoryBase);\r | |
698 | }\r | |
699 | \r | |
36658fff WL |
700 | //\r |
701 | // Publish this memory to the PEI Core\r | |
702 | //\r | |
ac0a286f | 703 | Status = PublishSystemMemory (MemoryBase, MemorySize);\r |
36658fff WL |
704 | ASSERT_EFI_ERROR (Status);\r |
705 | \r | |
706 | return Status;\r | |
707 | }\r | |
708 | \r | |
84b223c1 LE |
709 | STATIC\r |
710 | VOID\r | |
711 | QemuInitializeRamBelow1gb (\r | |
712 | VOID\r | |
713 | )\r | |
714 | {\r | |
715 | if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {\r | |
716 | AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);\r | |
ac0a286f MK |
717 | AddReservedMemoryBaseSizeHob (\r |
718 | SMM_DEFAULT_SMBASE,\r | |
719 | MCH_DEFAULT_SMBASE_SIZE,\r | |
720 | TRUE /* Cacheable */\r | |
721 | );\r | |
84b223c1 LE |
722 | STATIC_ASSERT (\r |
723 | SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128KB,\r | |
724 | "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"\r | |
725 | );\r | |
ac0a286f MK |
726 | AddMemoryRangeHob (\r |
727 | SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,\r | |
728 | BASE_512KB + BASE_128KB\r | |
729 | );\r | |
84b223c1 LE |
730 | } else {\r |
731 | AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r | |
732 | }\r | |
733 | }\r | |
734 | \r | |
49ba9447 | 735 | /**\r |
c034906e | 736 | Peform Memory Detection for QEMU / KVM\r |
49ba9447 | 737 | \r |
738 | **/\r | |
c034906e JJ |
739 | STATIC\r |
740 | VOID\r | |
741 | QemuInitializeRam (\r | |
742 | VOID\r | |
49ba9447 | 743 | )\r |
744 | {\r | |
ac0a286f MK |
745 | UINT64 LowerMemorySize;\r |
746 | UINT64 UpperMemorySize;\r | |
747 | MTRR_SETTINGS MtrrSettings;\r | |
748 | EFI_STATUS Status;\r | |
49ba9447 | 749 | \r |
70d5086c | 750 | DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__));\r |
49ba9447 | 751 | \r |
752 | //\r | |
753 | // Determine total memory size available\r | |
754 | //\r | |
c0e10976 | 755 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r |
756 | UpperMemorySize = GetSystemMemorySizeAbove4gb ();\r | |
49ba9447 | 757 | \r |
e3e3090a LE |
758 | if (mBootMode == BOOT_ON_S3_RESUME) {\r |
759 | //\r | |
760 | // Create the following memory HOB as an exception on the S3 boot path.\r | |
761 | //\r | |
762 | // Normally we'd create memory HOBs only on the normal boot path. However,\r | |
763 | // CpuMpPei specifically needs such a low-memory HOB on the S3 path as\r | |
764 | // well, for "borrowing" a subset of it temporarily, for the AP startup\r | |
765 | // vector.\r | |
766 | //\r | |
767 | // CpuMpPei saves the original contents of the borrowed area in permanent\r | |
768 | // PEI RAM, in a backup buffer allocated with the normal PEI services.\r | |
769 | // CpuMpPei restores the original contents ("returns" the borrowed area) at\r | |
770 | // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before\r | |
8c0b0b34 | 771 | // transferring control to the OS's wakeup vector in the FACS.\r |
e3e3090a LE |
772 | //\r |
773 | // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to\r | |
774 | // restore the original contents. Furthermore, we expect all such PEIMs\r | |
775 | // (CpuMpPei included) to claim the borrowed areas by producing memory\r | |
776 | // allocation HOBs, and to honor preexistent memory allocation HOBs when\r | |
777 | // looking for an area to borrow.\r | |
778 | //\r | |
84b223c1 | 779 | QemuInitializeRamBelow1gb ();\r |
e3e3090a | 780 | } else {\r |
bd386eaf JJ |
781 | //\r |
782 | // Create memory HOBs\r | |
783 | //\r | |
84b223c1 | 784 | QemuInitializeRamBelow1gb ();\r |
b09c1c6f LE |
785 | \r |
786 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
ac0a286f | 787 | UINT32 TsegSize;\r |
b09c1c6f | 788 | \r |
23bfb5c0 | 789 | TsegSize = mQ35TsegMbytes * SIZE_1MB;\r |
b09c1c6f | 790 | AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r |
ac0a286f MK |
791 | AddReservedMemoryBaseSizeHob (\r |
792 | LowerMemorySize - TsegSize,\r | |
793 | TsegSize,\r | |
794 | TRUE\r | |
795 | );\r | |
b09c1c6f LE |
796 | } else {\r |
797 | AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r | |
798 | }\r | |
799 | \r | |
1fceaddb LE |
800 | //\r |
801 | // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM\r | |
802 | // entries. Otherwise, create a single memory HOB with the flat >=4GB\r | |
803 | // memory size read from the CMOS.\r | |
804 | //\r | |
805 | Status = ScanOrAdd64BitE820Ram (NULL);\r | |
ac0a286f | 806 | if (EFI_ERROR (Status) && (UpperMemorySize != 0)) {\r |
035ce3b3 | 807 | AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r |
cfc80e2e | 808 | }\r |
bd386eaf | 809 | }\r |
49ba9447 | 810 | \r |
79d274b8 LE |
811 | //\r |
812 | // We'd like to keep the following ranges uncached:\r | |
813 | // - [640 KB, 1 MB)\r | |
814 | // - [LowerMemorySize, 4 GB)\r | |
815 | //\r | |
816 | // Everything else should be WB. Unfortunately, programming the inverse (ie.\r | |
817 | // keeping the default UC, and configuring the complement set of the above as\r | |
818 | // WB) is not reliable in general, because the end of the upper RAM can have\r | |
819 | // practically any alignment, and we may not have enough variable MTRRs to\r | |
820 | // cover it exactly.\r | |
821 | //\r | |
822 | if (IsMtrrSupported ()) {\r | |
823 | MtrrGetAllMtrrs (&MtrrSettings);\r | |
824 | \r | |
825 | //\r | |
826 | // MTRRs disabled, fixed MTRRs disabled, default type is uncached\r | |
827 | //\r | |
828 | ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);\r | |
829 | ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);\r | |
830 | ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);\r | |
831 | \r | |
832 | //\r | |
833 | // flip default type to writeback\r | |
834 | //\r | |
835 | SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);\r | |
836 | ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);\r | |
837 | MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;\r | |
838 | MtrrSetAllMtrrs (&MtrrSettings);\r | |
e8e5cd4a | 839 | \r |
79d274b8 LE |
840 | //\r |
841 | // Set memory range from 640KB to 1MB to uncacheable\r | |
842 | //\r | |
ac0a286f MK |
843 | Status = MtrrSetMemoryAttribute (\r |
844 | BASE_512KB + BASE_128KB,\r | |
845 | BASE_1MB - (BASE_512KB + BASE_128KB),\r | |
846 | CacheUncacheable\r | |
847 | );\r | |
79d274b8 | 848 | ASSERT_EFI_ERROR (Status);\r |
e8e5cd4a | 849 | \r |
79d274b8 | 850 | //\r |
49edde15 LE |
851 | // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI\r |
852 | // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.\r | |
79d274b8 | 853 | //\r |
ac0a286f MK |
854 | Status = MtrrSetMemoryAttribute (\r |
855 | mQemuUc32Base,\r | |
856 | SIZE_4GB - mQemuUc32Base,\r | |
857 | CacheUncacheable\r | |
858 | );\r | |
79d274b8 | 859 | ASSERT_EFI_ERROR (Status);\r |
c0e10976 | 860 | }\r |
49ba9447 | 861 | }\r |
862 | \r | |
c034906e JJ |
863 | /**\r |
864 | Publish system RAM and reserve memory regions\r | |
865 | \r | |
866 | **/\r | |
867 | VOID\r | |
868 | InitializeRamRegions (\r | |
869 | VOID\r | |
870 | )\r | |
871 | {\r | |
d06eb2d1 | 872 | QemuInitializeRam ();\r |
8e54500f | 873 | \r |
ac0a286f | 874 | if (mS3Supported && (mBootMode != BOOT_ON_S3_RESUME)) {\r |
8e54500f JJ |
875 | //\r |
876 | // This is the memory range that will be used for PEI on S3 resume\r | |
877 | //\r | |
878 | BuildMemoryAllocationHob (\r | |
45d87081 LE |
879 | mS3AcpiReservedMemoryBase,\r |
880 | mS3AcpiReservedMemorySize,\r | |
8e54500f JJ |
881 | EfiACPIMemoryNVS\r |
882 | );\r | |
e249f906 LE |
883 | \r |
884 | //\r | |
885 | // Cover the initial RAM area used as stack and temporary PEI heap.\r | |
886 | //\r | |
887 | // This is reserved as ACPI NVS so it can be used on S3 resume.\r | |
888 | //\r | |
889 | BuildMemoryAllocationHob (\r | |
890 | PcdGet32 (PcdOvmfSecPeiTempRamBase),\r | |
891 | PcdGet32 (PcdOvmfSecPeiTempRamSize),\r | |
892 | EfiACPIMemoryNVS\r | |
893 | );\r | |
78a38b73 | 894 | \r |
ad43bc6b LE |
895 | //\r |
896 | // SEC stores its table of GUIDed section handlers here.\r | |
897 | //\r | |
898 | BuildMemoryAllocationHob (\r | |
899 | PcdGet64 (PcdGuidedExtractHandlerTableAddress),\r | |
900 | PcdGet32 (PcdGuidedExtractHandlerTableSize),\r | |
901 | EfiACPIMemoryNVS\r | |
902 | );\r | |
903 | \r | |
ac0a286f | 904 | #ifdef MDE_CPU_X64\r |
78a38b73 LE |
905 | //\r |
906 | // Reserve the initial page tables built by the reset vector code.\r | |
907 | //\r | |
908 | // Since this memory range will be used by the Reset Vector on S3\r | |
909 | // resume, it must be reserved as ACPI NVS.\r | |
910 | //\r | |
911 | BuildMemoryAllocationHob (\r | |
ac0a286f MK |
912 | (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecPageTablesBase),\r |
913 | (UINT64)(UINTN)PcdGet32 (PcdOvmfSecPageTablesSize),\r | |
78a38b73 LE |
914 | EfiACPIMemoryNVS\r |
915 | );\r | |
0bbed066 TL |
916 | \r |
917 | if (MemEncryptSevEsIsEnabled ()) {\r | |
918 | //\r | |
919 | // If SEV-ES is enabled, reserve the GHCB-related memory area. This\r | |
920 | // includes the extra page table used to break down the 2MB page\r | |
921 | // mapping into 4KB page entries where the GHCB resides and the\r | |
922 | // GHCB area itself.\r | |
923 | //\r | |
924 | // Since this memory range will be used by the Reset Vector on S3\r | |
925 | // resume, it must be reserved as ACPI NVS.\r | |
926 | //\r | |
927 | BuildMemoryAllocationHob (\r | |
ac0a286f MK |
928 | (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableBase),\r |
929 | (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableSize),\r | |
0bbed066 TL |
930 | EfiACPIMemoryNVS\r |
931 | );\r | |
932 | BuildMemoryAllocationHob (\r | |
ac0a286f MK |
933 | (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBase),\r |
934 | (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbSize),\r | |
0bbed066 TL |
935 | EfiACPIMemoryNVS\r |
936 | );\r | |
36265424 | 937 | BuildMemoryAllocationHob (\r |
ac0a286f MK |
938 | (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupBase),\r |
939 | (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupSize),\r | |
36265424 TL |
940 | EfiACPIMemoryNVS\r |
941 | );\r | |
0bbed066 | 942 | }\r |
ac0a286f MK |
943 | \r |
944 | #endif\r | |
0e8a31f5 | 945 | }\r |
6a7cba79 | 946 | \r |
0e8a31f5 | 947 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
1a7edbbc LE |
948 | if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r |
949 | //\r | |
950 | // Reserve the lock box storage area\r | |
951 | //\r | |
952 | // Since this memory range will be used on S3 resume, it must be\r | |
953 | // reserved as ACPI NVS.\r | |
954 | //\r | |
955 | // If S3 is unsupported, then various drivers might still write to the\r | |
956 | // LockBox area. We ought to prevent DXE from serving allocation requests\r | |
957 | // such that they would overlap the LockBox storage.\r | |
958 | //\r | |
959 | ZeroMem (\r | |
ac0a286f MK |
960 | (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r |
961 | (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize)\r | |
1a7edbbc LE |
962 | );\r |
963 | BuildMemoryAllocationHob (\r | |
ac0a286f MK |
964 | (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r |
965 | (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),\r | |
1a7edbbc LE |
966 | mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r |
967 | );\r | |
968 | }\r | |
b09c1c6f LE |
969 | \r |
970 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
ac0a286f | 971 | UINT32 TsegSize;\r |
b09c1c6f LE |
972 | \r |
973 | //\r | |
974 | // Make sure the TSEG area that we reported as a reserved memory resource\r | |
975 | // cannot be used for reserved memory allocations.\r | |
976 | //\r | |
23bfb5c0 | 977 | TsegSize = mQ35TsegMbytes * SIZE_1MB;\r |
b09c1c6f | 978 | BuildMemoryAllocationHob (\r |
ac0a286f | 979 | GetSystemMemorySizeBelow4gb () - TsegSize,\r |
b09c1c6f LE |
980 | TsegSize,\r |
981 | EfiReservedMemoryType\r | |
982 | );\r | |
84b223c1 LE |
983 | //\r |
984 | // Similarly, allocate away the (already reserved) SMRAM at the default\r | |
985 | // SMBASE, if it exists.\r | |
986 | //\r | |
987 | if (mQ35SmramAtDefaultSmbase) {\r | |
988 | BuildMemoryAllocationHob (\r | |
989 | SMM_DEFAULT_SMBASE,\r | |
990 | MCH_DEFAULT_SMBASE_SIZE,\r | |
991 | EfiReservedMemoryType\r | |
992 | );\r | |
993 | }\r | |
b09c1c6f | 994 | }\r |
0731236f | 995 | \r |
ac0a286f | 996 | #ifdef MDE_CPU_X64\r |
80e67af9 | 997 | if (FixedPcdGet32 (PcdOvmfWorkAreaSize) != 0) {\r |
0731236f | 998 | //\r |
80e67af9 | 999 | // Reserve the work area.\r |
0731236f TL |
1000 | //\r |
1001 | // Since this memory range will be used by the Reset Vector on S3\r | |
1002 | // resume, it must be reserved as ACPI NVS.\r | |
1003 | //\r | |
1004 | // If S3 is unsupported, then various drivers might still write to the\r | |
1005 | // work area. We ought to prevent DXE from serving allocation requests\r | |
1006 | // such that they would overlap the work area.\r | |
1007 | //\r | |
1008 | BuildMemoryAllocationHob (\r | |
ac0a286f MK |
1009 | (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase),\r |
1010 | (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize),\r | |
0731236f TL |
1011 | mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r |
1012 | );\r | |
1013 | }\r | |
ac0a286f MK |
1014 | \r |
1015 | #endif\r | |
8e54500f | 1016 | }\r |
c034906e | 1017 | }\r |