]>
Commit | Line | Data |
---|---|---|
1767877a LE |
1 | /** @file\r |
2 | OVMF support for QEMU system firmware flash device: functions specific to the\r | |
3 | runtime DXE driver build.\r | |
4 | \r | |
5 | Copyright (C) 2015, Red Hat, Inc.\r | |
6 | Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>\r | |
7 | \r | |
b26f0cf9 | 8 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1767877a LE |
9 | \r |
10 | **/\r | |
11 | \r | |
12 | #include <Library/UefiRuntimeLib.h>\r | |
437eb3f7 TL |
13 | #include <Library/MemEncryptSevLib.h>\r |
14 | #include <Library/VmgExitLib.h>\r | |
15 | #include <Register/Amd/Msr.h>\r | |
1767877a LE |
16 | \r |
17 | #include "QemuFlash.h"\r | |
18 | \r | |
ac0a286f | 19 | STATIC EFI_PHYSICAL_ADDRESS mSevEsFlashPhysBase;\r |
3a350186 | 20 | \r |
1767877a LE |
21 | VOID\r |
22 | QemuFlashConvertPointers (\r | |
23 | VOID\r | |
24 | )\r | |
25 | {\r | |
3a350186 | 26 | if (MemEncryptSevEsIsEnabled ()) {\r |
ac0a286f | 27 | mSevEsFlashPhysBase = (UINTN)mFlashBase;\r |
3a350186 TL |
28 | }\r |
29 | \r | |
ac0a286f | 30 | EfiConvertPointer (0x0, (VOID **)&mFlashBase);\r |
1767877a | 31 | }\r |
e4a1d5a7 BS |
32 | \r |
33 | VOID\r | |
34 | QemuFlashBeforeProbe (\r | |
ac0a286f MK |
35 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r |
36 | IN UINTN FdBlockSize,\r | |
37 | IN UINTN FdBlockCount\r | |
e4a1d5a7 BS |
38 | )\r |
39 | {\r | |
40 | //\r | |
41 | // Do nothing\r | |
42 | //\r | |
43 | }\r | |
437eb3f7 TL |
44 | \r |
45 | /**\r | |
46 | Write to QEMU Flash\r | |
47 | \r | |
48 | @param[in] Ptr Pointer to the location to write.\r | |
49 | @param[in] Value The value to write.\r | |
50 | \r | |
51 | **/\r | |
52 | VOID\r | |
53 | QemuFlashPtrWrite (\r | |
ac0a286f MK |
54 | IN volatile UINT8 *Ptr,\r |
55 | IN UINT8 Value\r | |
437eb3f7 TL |
56 | )\r |
57 | {\r | |
58 | if (MemEncryptSevEsIsEnabled ()) {\r | |
59 | MSR_SEV_ES_GHCB_REGISTER Msr;\r | |
60 | GHCB *Ghcb;\r | |
3a350186 | 61 | EFI_PHYSICAL_ADDRESS PhysAddr;\r |
1b0db1ec | 62 | BOOLEAN InterruptState;\r |
437eb3f7 TL |
63 | \r |
64 | Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);\r | |
ac0a286f | 65 | Ghcb = Msr.Ghcb;\r |
437eb3f7 | 66 | \r |
3a350186 TL |
67 | //\r |
68 | // The MMIO write needs to be to the physical address of the flash pointer.\r | |
69 | // Since this service is available as part of the EFI runtime services,\r | |
70 | // account for a non-identity mapped VA after SetVirtualAddressMap().\r | |
71 | //\r | |
72 | if (mSevEsFlashPhysBase == 0) {\r | |
ac0a286f | 73 | PhysAddr = (UINTN)Ptr;\r |
3a350186 TL |
74 | } else {\r |
75 | PhysAddr = mSevEsFlashPhysBase + (Ptr - mFlashBase);\r | |
76 | }\r | |
77 | \r | |
437eb3f7 TL |
78 | //\r |
79 | // Writing to flash is emulated by the hypervisor through the use of write\r | |
80 | // protection. This won't work for an SEV-ES guest because the write won't\r | |
81 | // be recognized as a true MMIO write, which would result in the required\r | |
82 | // #VC exception. Instead, use the the VMGEXIT MMIO write support directly\r | |
83 | // to perform the update.\r | |
84 | //\r | |
1b0db1ec | 85 | VmgInit (Ghcb, &InterruptState);\r |
ac0a286f MK |
86 | Ghcb->SharedBuffer[0] = Value;\r |
87 | Ghcb->SaveArea.SwScratch = (UINT64)(UINTN)Ghcb->SharedBuffer;\r | |
f714fd67 | 88 | VmgSetOffsetValid (Ghcb, GhcbSwScratch);\r |
3a350186 | 89 | VmgExit (Ghcb, SVM_EXIT_MMIO_WRITE, PhysAddr, 1);\r |
1b0db1ec | 90 | VmgDone (Ghcb, InterruptState);\r |
437eb3f7 TL |
91 | } else {\r |
92 | *Ptr = Value;\r | |
93 | }\r | |
94 | }\r |