OvmfPkg/ResetVector: Set C-bit when building initial page table

[mirror_edk2.git] / OvmfPkg / ResetVector / Ia32 / PageTables64.asm

;------------------------------------------------------------------------------\r
; @file\r
; Sets the CR3 register for 64-bit paging\r
;\r
; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution.  The full text of the license may be found at\r
; http://opensource.org/licenses/bsd-license.php\r
;\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
;------------------------------------------------------------------------------\r
\r
BITS    32\r
\r
%define PAGE_PRESENT            0x01\r
%define PAGE_READ_WRITE         0x02\r
%define PAGE_USER_SUPERVISOR    0x04\r
%define PAGE_WRITE_THROUGH      0x08\r
%define PAGE_CACHE_DISABLE     0x010\r
%define PAGE_ACCESSED          0x020\r
%define PAGE_DIRTY             0x040\r
%define PAGE_PAT               0x080\r
%define PAGE_GLOBAL           0x0100\r
%define PAGE_2M_MBO            0x080\r
%define PAGE_2M_PAT          0x01000\r
\r
%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \\r
                          PAGE_ACCESSED + \\r
                          PAGE_DIRTY + \\r
                          PAGE_READ_WRITE + \\r
                          PAGE_PRESENT)\r
\r
%define PAGE_PDP_ATTR (PAGE_ACCESSED + \\r
                       PAGE_READ_WRITE + \\r
                       PAGE_PRESENT)\r
\r
; Check if Secure Encrypted Virtualization (SEV) feature is enabled\r
;\r
; If SEV is enabled then EAX will be at least 32\r
; If SEV is disabled then EAX will be zero.\r
;\r
CheckSevFeature:\r
    ; Check if we have a valid (0x8000_001F) CPUID leaf\r
    mov       eax, 0x80000000\r
    cpuid\r
\r
    ; This check should fail on Intel or Non SEV AMD CPUs. In future if\r
    ; Intel CPUs supports this CPUID leaf then we are guranteed to have exact\r
    ; same bit definition.\r
    cmp       eax, 0x8000001f\r
    jl        NoSev\r
\r
    ; Check for memory encryption feature:\r
    ;  CPUID  Fn8000_001F[EAX] - Bit 1\r
    ;\r
    mov       eax,  0x8000001f\r
    cpuid\r
    bt        eax, 1\r
    jnc       NoSev\r
\r
    ; Check if memory encryption is enabled\r
    ;  MSR_0xC0010131 - Bit 0 (SEV enabled)\r
    mov       ecx, 0xc0010131\r
    rdmsr\r
    bt        eax, 0\r
    jnc       NoSev\r
\r
    ; Get pte bit position to enable memory encryption\r
    ; CPUID Fn8000_001F[EBX] - Bits 5:0\r
    ;\r
    mov       eax, ebx\r
    and       eax, 0x3f\r
    jmp       SevExit\r
\r
NoSev:\r
    xor       eax, eax\r
\r
SevExit:\r
    OneTimeCallRet CheckSevFeature\r
\r
;\r
; Modified:  EAX, EBX, ECX, EDX\r
;\r
SetCr3ForPageTables64:\r
\r
    OneTimeCall   CheckSevFeature\r
    xor     edx, edx\r
    test    eax, eax\r
    jz      SevNotActive\r
\r
    ; If SEV is enabled, C-bit is always above 31\r
    sub     eax, 32\r
    bts     edx, eax\r
\r
SevNotActive:\r
\r
    ;\r
    ; For OVMF, build some initial page tables at\r
    ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).\r
    ;\r
    ; This range should match with PcdOvmfSecPageTablesSize which is\r
    ; declared in the FDF files.\r
    ;\r
    ; At the end of PEI, the pages tables will be rebuilt into a\r
    ; more permanent location by DxeIpl.\r
    ;\r
\r
    mov     ecx, 6 * 0x1000 / 4\r
    xor     eax, eax\r
clearPageTablesMemoryLoop:\r
    mov     dword[ecx * 4 + PT_ADDR (0) - 4], eax\r
    loop    clearPageTablesMemoryLoop\r
\r
    ;\r
    ; Top level Page Directory Pointers (1 * 512GB entry)\r
    ;\r
    mov     dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR\r
    mov     dword[PT_ADDR (4)], edx\r
\r
    ;\r
    ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)\r
    ;\r
    mov     dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR\r
    mov     dword[PT_ADDR (0x1004)], edx\r
    mov     dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR\r
    mov     dword[PT_ADDR (0x100C)], edx\r
    mov     dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR\r
    mov     dword[PT_ADDR (0x1014)], edx\r
    mov     dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR\r
    mov     dword[PT_ADDR (0x101C)], edx\r
\r
    ;\r
    ; Page Table Entries (2048 * 2MB entries => 4GB)\r
    ;\r
    mov     ecx, 0x800\r
pageTableEntriesLoop:\r
    mov     eax, ecx\r
    dec     eax\r
    shl     eax, 21\r
    add     eax, PAGE_2M_PDE_ATTR\r
    mov     [ecx * 8 + PT_ADDR (0x2000 - 8)], eax\r
    mov     [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx\r
    loop    pageTableEntriesLoop\r
\r
    ;\r
    ; Set CR3 now that the paging structures are available\r
    ;\r
    mov     eax, PT_ADDR (0)\r
    mov     cr3, eax\r
\r
    OneTimeCallRet SetCr3ForPageTables64\r