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Commit | Line | Data |
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49ba9447 | 1 | ;------------------------------------------------------------------------------\r |
2 | ;*\r | |
7cb6b0e0 | 3 | ;* Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r |
b26f0cf9 | 4 | ;* SPDX-License-Identifier: BSD-2-Clause-Patent\r |
49ba9447 | 5 | ;*\r |
6 | ;* CpuAsm.asm\r | |
7 | ;*\r | |
8 | ;* Abstract:\r | |
9 | ;*\r | |
10 | ;------------------------------------------------------------------------------\r | |
11 | \r | |
42a83e80 | 12 | #include <Base.h>\r |
49ba9447 | 13 | \r |
d8cfdb5f JJ |
14 | DEFAULT REL\r |
15 | SECTION .text\r | |
49ba9447 | 16 | \r |
d8cfdb5f | 17 | extern ASM_PFX(SecCoreStartupWithStack)\r |
49ba9447 | 18 | \r |
2b80269d MX |
19 | %macro tdcall 0\r |
20 | db 0x66, 0x0f, 0x01, 0xcc\r | |
21 | %endmacro\r | |
22 | \r | |
49ba9447 | 23 | ;\r |
0913fadc | 24 | ; SecCore Entry Point\r |
49ba9447 | 25 | ;\r |
0913fadc | 26 | ; Processor is in flat protected mode\r |
49ba9447 | 27 | ;\r |
0913fadc | 28 | ; @param[in] RAX Initial value of the EAX register (BIST: Built-in Self Test)\r |
29 | ; @param[in] DI 'BP': boot-strap processor, or 'AP': application processor\r | |
30 | ; @param[in] RBP Pointer to the start of the Boot Firmware Volume\r | |
2278b8a8 LE |
31 | ; @param[in] DS Selector allowing flat access to all addresses\r |
32 | ; @param[in] ES Selector allowing flat access to all addresses\r | |
33 | ; @param[in] FS Selector allowing flat access to all addresses\r | |
34 | ; @param[in] GS Selector allowing flat access to all addresses\r | |
35 | ; @param[in] SS Selector allowing flat access to all addresses\r | |
49ba9447 | 36 | ;\r |
0913fadc | 37 | ; @return None This routine does not return\r |
49ba9447 | 38 | ;\r |
d8cfdb5f JJ |
39 | global ASM_PFX(_ModuleEntryPoint)\r |
40 | ASM_PFX(_ModuleEntryPoint):\r | |
49ba9447 | 41 | \r |
2b80269d MX |
42 | ;\r |
43 | ; Guest type is stored in OVMF_WORK_AREA\r | |
44 | ;\r | |
45 | %define OVMF_WORK_AREA FixedPcdGet32 (PcdOvmfWorkAreaBase)\r | |
46 | %define VM_GUEST_TYPE_TDX 2\r | |
47 | mov eax, OVMF_WORK_AREA\r | |
48 | cmp byte[eax], VM_GUEST_TYPE_TDX\r | |
49 | jne InitStack\r | |
50 | \r | |
0547ffbf | 51 | %define TDCALL_TDINFO 1\r |
2b80269d MX |
52 | mov rax, TDCALL_TDINFO\r |
53 | tdcall\r | |
54 | \r | |
55 | ;\r | |
56 | ; R8 [31:0] NUM_VCPUS\r | |
57 | ; [63:32] MAX_VCPUS\r | |
58 | ; R9 [31:0] VCPU_INDEX\r | |
59 | ; Td Guest set the VCPU0 as the BSP, others are the APs\r | |
60 | ; APs jump to spinloop and get released by DXE's MpInitLib\r | |
61 | ;\r | |
62 | mov rax, r9\r | |
63 | and rax, 0xffff\r | |
64 | test rax, rax\r | |
0547ffbf MX |
65 | jz InitStack\r |
66 | mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase)\r | |
67 | jmp ParkAp\r | |
2b80269d MX |
68 | \r |
69 | InitStack:\r | |
70 | \r | |
2278b8a8 LE |
71 | ;\r |
72 | ; Fill the temporary RAM with the initial stack value.\r | |
73 | ; The loop below will seed the heap as well, but that's harmless.\r | |
74 | ;\r | |
46c6b956 RN |
75 | mov rax, (FixedPcdGet32 (PcdInitValueInTempStack) << 32) | FixedPcdGet32 (PcdInitValueInTempStack)\r |
76 | ; qword to store\r | |
2278b8a8 LE |
77 | mov rdi, FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) ; base address,\r |
78 | ; relative to\r | |
79 | ; ES\r | |
80 | mov rcx, FixedPcdGet32 (PcdOvmfSecPeiTempRamSize) / 8 ; qword count\r | |
81 | cld ; store from base\r | |
82 | ; up\r | |
83 | rep stosq\r | |
84 | \r | |
49ba9447 | 85 | ;\r |
7cb6b0e0 | 86 | ; Load temporary RAM stack based on PCDs\r |
49ba9447 | 87 | ;\r |
d8cfdb5f | 88 | %define SEC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + \\r |
7cb6b0e0 JJ |
89 | FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))\r |
90 | mov rsp, SEC_TOP_OF_STACK\r | |
49ba9447 | 91 | nop\r |
92 | \r | |
93 | ;\r | |
94 | ; Setup parameters and call SecCoreStartupWithStack\r | |
95 | ; rcx: BootFirmwareVolumePtr\r | |
0913fadc | 96 | ; rdx: TopOfCurrentStack\r |
49ba9447 | 97 | ;\r |
98 | mov rcx, rbp\r | |
0913fadc | 99 | mov rdx, rsp\r |
d8cfdb5f JJ |
100 | sub rsp, 0x20\r |
101 | call ASM_PFX(SecCoreStartupWithStack)\r | |
49ba9447 | 102 | \r |
0547ffbf | 103 | %include "../../IntelTdx/Sec/X64/IntelTdxAPs.nasm"\r |