[mirror_edk2.git] / OvmfPkg / SmmAccess / SmmAccessPei.c

/** @file\r
\r
  A PEIM with the following responsibilities:\r
\r
  - verify & configure the Q35 TSEG in the entry point,\r
  - provide SMRAM access by producing PEI_SMM_ACCESS_PPI,\r
  - set aside the SMM_S3_RESUME_STATE object at the bottom of TSEG, and expose\r
    it via the gEfiAcpiVariableGuid GUID HOB.\r
\r
  This PEIM runs from RAM, so we can write to variables with static storage\r
  duration.\r
\r
  Copyright (C) 2013, 2015, Red Hat, Inc.<BR>\r
  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Guid/AcpiS3Context.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Ppi/SmmAccess.h>\r
\r
#include <OvmfPlatforms.h>\r
\r
#include "SmramInternal.h"\r
\r
//\r
// PEI_SMM_ACCESS_PPI implementation.\r
//\r
\r
/**\r
  Opens the SMRAM area to be accessible by a PEIM driver.\r
\r
  This function "opens" SMRAM so that it is visible while not inside of SMM.\r
  The function should return EFI_UNSUPPORTED if the hardware does not support\r
  hiding of SMRAM. The function should return EFI_DEVICE_ERROR if the SMRAM\r
  configuration is locked.\r
\r
  @param  PeiServices            General purpose services available to every\r
                                 PEIM.\r
  @param  This                   The pointer to the SMM Access Interface.\r
  @param  DescriptorIndex        The region of SMRAM to Open.\r
\r
  @retval EFI_SUCCESS            The region was successfully opened.\r
  @retval EFI_DEVICE_ERROR       The region could not be opened because locked\r
                                 by chipset.\r
  @retval EFI_INVALID_PARAMETER  The descriptor index was out of bounds.\r
\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiOpen (\r
  IN EFI_PEI_SERVICES                **PeiServices,\r
  IN PEI_SMM_ACCESS_PPI              *This,\r
  IN UINTN                           DescriptorIndex\r
  )\r
{\r
  if (DescriptorIndex >= DescIdxCount) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // According to current practice, DescriptorIndex is not considered at all,\r
  // beyond validating it.\r
  //\r
  return SmramAccessOpen (&This->LockState, &This->OpenState);\r
}\r
\r
/**\r
  Inhibits access to the SMRAM.\r
\r
  This function "closes" SMRAM so that it is not visible while outside of SMM.\r
  The function should return EFI_UNSUPPORTED if the hardware does not support\r
  hiding of SMRAM.\r
\r
  @param  PeiServices              General purpose services available to every\r
                                   PEIM.\r
  @param  This                     The pointer to the SMM Access Interface.\r
  @param  DescriptorIndex          The region of SMRAM to Close.\r
\r
  @retval EFI_SUCCESS              The region was successfully closed.\r
  @retval EFI_DEVICE_ERROR         The region could not be closed because\r
                                   locked by chipset.\r
  @retval EFI_INVALID_PARAMETER    The descriptor index was out of bounds.\r
\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiClose (\r
  IN EFI_PEI_SERVICES                **PeiServices,\r
  IN PEI_SMM_ACCESS_PPI              *This,\r
  IN UINTN                           DescriptorIndex\r
  )\r
{\r
  if (DescriptorIndex >= DescIdxCount) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // According to current practice, DescriptorIndex is not considered at all,\r
  // beyond validating it.\r
  //\r
  return SmramAccessClose (&This->LockState, &This->OpenState);\r
}\r
\r
/**\r
  Inhibits access to the SMRAM.\r
\r
  This function prohibits access to the SMRAM region.  This function is usually\r
  implemented such that it is a write-once operation.\r
\r
  @param  PeiServices              General purpose services available to every\r
                                   PEIM.\r
  @param  This                     The pointer to the SMM Access Interface.\r
  @param  DescriptorIndex          The region of SMRAM to Close.\r
\r
  @retval EFI_SUCCESS            The region was successfully locked.\r
  @retval EFI_DEVICE_ERROR       The region could not be locked because at\r
                                 least one range is still open.\r
  @retval EFI_INVALID_PARAMETER  The descriptor index was out of bounds.\r
\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiLock (\r
  IN EFI_PEI_SERVICES                **PeiServices,\r
  IN PEI_SMM_ACCESS_PPI              *This,\r
  IN UINTN                           DescriptorIndex\r
  )\r
{\r
  if (DescriptorIndex >= DescIdxCount) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // According to current practice, DescriptorIndex is not considered at all,\r
  // beyond validating it.\r
  //\r
  return SmramAccessLock (&This->LockState, &This->OpenState);\r
}\r
\r
/**\r
  Queries the memory controller for the possible regions that will support\r
  SMRAM.\r
\r
  @param  PeiServices           General purpose services available to every\r
                                PEIM.\r
  @param This                   The pointer to the SmmAccessPpi Interface.\r
  @param SmramMapSize           The pointer to the variable containing size of\r
                                the buffer to contain the description\r
                                information.\r
  @param SmramMap               The buffer containing the data describing the\r
                                Smram region descriptors.\r
\r
  @retval EFI_BUFFER_TOO_SMALL  The user did not provide a sufficient buffer.\r
  @retval EFI_SUCCESS           The user provided a sufficiently-sized buffer.\r
\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiGetCapabilities (\r
  IN EFI_PEI_SERVICES                **PeiServices,\r
  IN PEI_SMM_ACCESS_PPI              *This,\r
  IN OUT UINTN                       *SmramMapSize,\r
  IN OUT EFI_SMRAM_DESCRIPTOR        *SmramMap\r
  )\r
{\r
  return SmramAccessGetCapabilities (This->LockState, This->OpenState,\r
           SmramMapSize, SmramMap);\r
}\r
\r
//\r
// LockState and OpenState will be filled in by the entry point.\r
//\r
STATIC PEI_SMM_ACCESS_PPI mAccess = {\r
  &SmmAccessPeiOpen,\r
  &SmmAccessPeiClose,\r
  &SmmAccessPeiLock,\r
  &SmmAccessPeiGetCapabilities\r
};\r
\r
\r
STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {\r
  {\r
    EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
    &gPeiSmmAccessPpiGuid, &mAccess\r
  }\r
};\r
\r
\r
//\r
// Utility functions.\r
//\r
STATIC\r
UINT8\r
CmosRead8 (\r
  IN UINT8 Index\r
  )\r
{\r
  IoWrite8 (0x70, Index);\r
  return IoRead8 (0x71);\r
}\r
\r
STATIC\r
UINT32\r
GetSystemMemorySizeBelow4gb (\r
  VOID\r
  )\r
{\r
  UINT32 Cmos0x34;\r
  UINT32 Cmos0x35;\r
\r
  Cmos0x34 = CmosRead8 (0x34);\r
  Cmos0x35 = CmosRead8 (0x35);\r
\r
  return ((Cmos0x35 << 8 | Cmos0x34) << 16) + SIZE_16MB;\r
}\r
\r
\r
//\r
// Entry point of this driver.\r
//\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiEntryPoint (\r
  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
  IN CONST EFI_PEI_SERVICES     **PeiServices\r
  )\r
{\r
  UINT16               HostBridgeDevId;\r
  UINT8                EsmramcVal;\r
  UINT8                RegMask8;\r
  UINT32               TopOfLowRam, TopOfLowRamMb;\r
  EFI_STATUS           Status;\r
  UINTN                SmramMapSize;\r
  EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount];\r
  VOID                 *GuidHob;\r
\r
  //\r
  // This module should only be included if SMRAM support is required.\r
  //\r
  ASSERT (FeaturePcdGet (PcdSmmSmramRequire));\r
\r
  //\r
  // Verify if we're running on a Q35 machine type.\r
  //\r
  HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
  if (HostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
    DEBUG ((EFI_D_ERROR, "%a: no SMRAM with host bridge DID=0x%04x; only "\r
      "DID=0x%04x (Q35) is supported\n", __FUNCTION__, HostBridgeDevId,\r
      INTEL_Q35_MCH_DEVICE_ID));\r
    goto WrongConfig;\r
  }\r
\r
  //\r
  // Confirm if QEMU supports SMRAM.\r
  //\r
  // With no support for it, the ESMRAMC (Extended System Management RAM\r
  // Control) register reads as zero. If there is support, the cache-enable\r
  // bits are hard-coded as 1 by QEMU.\r
  //\r
  EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));\r
  RegMask8 = MCH_ESMRAMC_SM_CACHE | MCH_ESMRAMC_SM_L1 | MCH_ESMRAMC_SM_L2;\r
  if ((EsmramcVal & RegMask8) != RegMask8) {\r
    DEBUG ((EFI_D_ERROR, "%a: this Q35 implementation lacks SMRAM\n",\r
      __FUNCTION__));\r
    goto WrongConfig;\r
  }\r
\r
  TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
  ASSERT ((TopOfLowRam & (SIZE_1MB - 1)) == 0);\r
  TopOfLowRamMb = TopOfLowRam >> 20;\r
\r
  //\r
  // Some of the following registers are no-ops for QEMU at the moment, but it\r
  // is recommended to set them correctly, since the ESMRAMC that we ultimately\r
  // care about is in the same set of registers.\r
  //\r
  // First, we disable the integrated VGA, and set both the GTT Graphics Memory\r
  // Size and the Graphics Mode Select memory pre-allocation fields to zero.\r
  // This takes just one write to the Graphics Control Register.\r
  //\r
  PciWrite16 (DRAMC_REGISTER_Q35 (MCH_GGC), MCH_GGC_IVD);\r
\r
  //\r
  // Set Top of Low Usable DRAM.\r
  //\r
  PciWrite16 (DRAMC_REGISTER_Q35 (MCH_TOLUD),\r
    (UINT16)(TopOfLowRamMb << MCH_TOLUD_MB_SHIFT));\r
\r
  //\r
  // Given the zero graphics memory sizes configured above, set the\r
  // graphics-related stolen memory bases to the same as TOLUD.\r
  //\r
  PciWrite32 (DRAMC_REGISTER_Q35 (MCH_GBSM),\r
    TopOfLowRamMb << MCH_GBSM_MB_SHIFT);\r
  PciWrite32 (DRAMC_REGISTER_Q35 (MCH_BGSM),\r
    TopOfLowRamMb << MCH_BGSM_MB_SHIFT);\r
\r
  //\r
  // Set TSEG Memory Base.\r
  //\r
  InitQ35TsegMbytes ();\r
  PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB),\r
    (TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT);\r
\r
  //\r
  // Set TSEG size, and disable TSEG visibility outside of SMM. Note that the\r
  // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility is\r
  // *restricted* to SMM.\r
  //\r
  EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK;\r
  EsmramcVal |= mQ35TsegMbytes == 8 ? MCH_ESMRAMC_TSEG_8MB :\r
                mQ35TsegMbytes == 2 ? MCH_ESMRAMC_TSEG_2MB :\r
                mQ35TsegMbytes == 1 ? MCH_ESMRAMC_TSEG_1MB :\r
                MCH_ESMRAMC_TSEG_EXT;\r
  EsmramcVal |= MCH_ESMRAMC_T_EN;\r
  PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal);\r
\r
  //\r
  // TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME\r
  // (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it.\r
  //\r
  PciAndThenOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM),\r
    (UINT8)((~(UINT32)MCH_SMRAM_D_LCK) & 0xff), MCH_SMRAM_G_SMRAME);\r
\r
  //\r
  // Create the GUID HOB and point it to the first SMRAM range.\r
  //\r
  GetStates (&mAccess.LockState, &mAccess.OpenState);\r
  SmramMapSize = sizeof SmramMap;\r
  Status = SmramAccessGetCapabilities (mAccess.LockState, mAccess.OpenState,\r
             &SmramMapSize, SmramMap);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  DEBUG_CODE_BEGIN ();\r
  {\r
    UINTN Count;\r
    UINTN Idx;\r
\r
    Count = SmramMapSize / sizeof SmramMap[0];\r
    DEBUG ((EFI_D_VERBOSE, "%a: SMRAM map follows, %d entries\n", __FUNCTION__,\r
      (INT32)Count));\r
    DEBUG ((EFI_D_VERBOSE, "% 20a % 20a % 20a % 20a\n", "PhysicalStart(0x)",\r
      "PhysicalSize(0x)", "CpuStart(0x)", "RegionState(0x)"));\r
    for (Idx = 0; Idx < Count; ++Idx) {\r
      DEBUG ((EFI_D_VERBOSE, "% 20Lx % 20Lx % 20Lx % 20Lx\n",\r
        SmramMap[Idx].PhysicalStart, SmramMap[Idx].PhysicalSize,\r
        SmramMap[Idx].CpuStart, SmramMap[Idx].RegionState));\r
    }\r
  }\r
  DEBUG_CODE_END ();\r
\r
  GuidHob = BuildGuidHob (&gEfiAcpiVariableGuid,\r
    sizeof SmramMap[DescIdxSmmS3ResumeState]);\r
  if (GuidHob == NULL) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  CopyMem (GuidHob, &SmramMap[DescIdxSmmS3ResumeState],\r
    sizeof SmramMap[DescIdxSmmS3ResumeState]);\r
\r
  //\r
  // We're done. The next step should succeed, but even if it fails, we can't\r
  // roll back the above BuildGuidHob() allocation, because PEI doesn't support\r
  // releasing memory.\r
  //\r
  return PeiServicesInstallPpi (mPpiList);\r
\r
WrongConfig:\r
  //\r
  // We really don't want to continue in this case.\r
  //\r
  ASSERT (FALSE);\r
  CpuDeadLoop ();\r
  return EFI_UNSUPPORTED;\r
}\r
Commit	Line	Data
9d560947 LE	1	/** @file\r
	2	\r
	3	A PEIM with the following responsibilities:\r
	4	\r
	5	- verify & configure the Q35 TSEG in the entry point,\r
	6	- provide SMRAM access by producing PEI_SMM_ACCESS_PPI,\r
	7	- set aside the SMM_S3_RESUME_STATE object at the bottom of TSEG, and expose\r
	8	it via the gEfiAcpiVariableGuid GUID HOB.\r
	9	\r
	10	This PEIM runs from RAM, so we can write to variables with static storage\r
	11	duration.\r
	12	\r
	13	Copyright (C) 2013, 2015, Red Hat, Inc.<BR>\r
	14	Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
	15	\r
b26f0cf9	16	SPDX-License-Identifier: BSD-2-Clause-Patent\r
9d560947 LE	17	\r
	18	**/\r
	19	\r
	20	#include <Guid/AcpiS3Context.h>\r
	21	#include <Library/BaseLib.h>\r
	22	#include <Library/BaseMemoryLib.h>\r
	23	#include <Library/DebugLib.h>\r
	24	#include <Library/HobLib.h>\r
	25	#include <Library/IoLib.h>\r
	26	#include <Library/PcdLib.h>\r
	27	#include <Library/PciLib.h>\r
	28	#include <Library/PeiServicesLib.h>\r
	29	#include <Ppi/SmmAccess.h>\r
	30	\r
	31	#include <OvmfPlatforms.h>\r
	32	\r
	33	#include "SmramInternal.h"\r
	34	\r
	35	//\r
	36	// PEI_SMM_ACCESS_PPI implementation.\r
	37	//\r
	38	\r
	39	/**\r
	40	Opens the SMRAM area to be accessible by a PEIM driver.\r
	41	\r
	42	This function "opens" SMRAM so that it is visible while not inside of SMM.\r
	43	The function should return EFI_UNSUPPORTED if the hardware does not support\r
	44	hiding of SMRAM. The function should return EFI_DEVICE_ERROR if the SMRAM\r
	45	configuration is locked.\r
	46	\r
	47	@param PeiServices General purpose services available to every\r
	48	PEIM.\r
	49	@param This The pointer to the SMM Access Interface.\r
	50	@param DescriptorIndex The region of SMRAM to Open.\r
	51	\r
	52	@retval EFI_SUCCESS The region was successfully opened.\r
	53	@retval EFI_DEVICE_ERROR The region could not be opened because locked\r
	54	by chipset.\r
	55	@retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r
	56	\r
	57	**/\r
	58	STATIC\r
	59	EFI_STATUS\r
	60	EFIAPI\r
	61	SmmAccessPeiOpen (\r
	62	IN EFI_PEI_SERVICES **PeiServices,\r
	63	IN PEI_SMM_ACCESS_PPI *This,\r
	64	IN UINTN DescriptorIndex\r
	65	)\r
	66	{\r
	67	if (DescriptorIndex >= DescIdxCount) {\r
	68	return EFI_INVALID_PARAMETER;\r
	69	}\r
	70	\r
	71	//\r
	72	// According to current practice, DescriptorIndex is not considered at all,\r
	73	// beyond validating it.\r
	74	//\r
	75	return SmramAccessOpen (&This->LockState, &This->OpenState);\r
	76	}\r
	77	\r
	78	/**\r
	79	Inhibits access to the SMRAM.\r
	80	\r
81	This function "closes" SMRAM so that it is not visible while outside of SMM.\r
82	The function should return EFI_UNSUPPORTED if the hardware does not support\r
83	hiding of SMRAM.\r
84	\r
85	@param PeiServices General purpose services available to every\r
86	PEIM.\r
87	@param This The pointer to the SMM Access Interface.\r
88	@param DescriptorIndex The region of SMRAM to Close.\r
89	\r
90	@retval EFI_SUCCESS The region was successfully closed.\r
91	@retval EFI_DEVICE_ERROR The region could not be closed because\r
92	locked by chipset.\r
93	@retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r
94	\r
95	**/\r
96	STATIC\r
97	EFI_STATUS\r
98	EFIAPI\r
99	SmmAccessPeiClose (\r
100	IN EFI_PEI_SERVICES **PeiServices,\r
101	IN PEI_SMM_ACCESS_PPI *This,\r
102	IN UINTN DescriptorIndex\r
103	)\r
104	{\r
105	if (DescriptorIndex >= DescIdxCount) {\r
106	return EFI_INVALID_PARAMETER;\r
107	}\r
108	\r
109	//\r
110	// According to current practice, DescriptorIndex is not considered at all,\r
111	// beyond validating it.\r
112	//\r
113	return SmramAccessClose (&This->LockState, &This->OpenState);\r
114	}\r
115	\r
116	/**\r
117	Inhibits access to the SMRAM.\r
118	\r
119	This function prohibits access to the SMRAM region. This function is usually\r
120	implemented such that it is a write-once operation.\r
121	\r
122	@param PeiServices General purpose services available to every\r
123	PEIM.\r
124	@param This The pointer to the SMM Access Interface.\r
125	@param DescriptorIndex The region of SMRAM to Close.\r
126	\r
127	@retval EFI_SUCCESS The region was successfully locked.\r
128	@retval EFI_DEVICE_ERROR The region could not be locked because at\r
129	least one range is still open.\r
130	@retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r
131	\r
132	**/\r
133	STATIC\r
134	EFI_STATUS\r
135	EFIAPI\r
136	SmmAccessPeiLock (\r
137	IN EFI_PEI_SERVICES **PeiServices,\r
138	IN PEI_SMM_ACCESS_PPI *This,\r
139	IN UINTN DescriptorIndex\r
140	)\r
141	{\r
142	if (DescriptorIndex >= DescIdxCount) {\r
143	return EFI_INVALID_PARAMETER;\r
144	}\r
145	\r
146	//\r
147	// According to current practice, DescriptorIndex is not considered at all,\r
148	// beyond validating it.\r
149	//\r
150	return SmramAccessLock (&This->LockState, &This->OpenState);\r
151	}\r
152	\r
153	/**\r
154	Queries the memory controller for the possible regions that will support\r
155	SMRAM.\r
156	\r
157	@param PeiServices General purpose services available to every\r
158	PEIM.\r
159	@param This The pointer to the SmmAccessPpi Interface.\r
160	@param SmramMapSize The pointer to the variable containing size of\r
161	the buffer to contain the description\r
162	information.\r
163	@param SmramMap The buffer containing the data describing the\r
164	Smram region descriptors.\r
165	\r
166	@retval EFI_BUFFER_TOO_SMALL The user did not provide a sufficient buffer.\r
167	@retval EFI_SUCCESS The user provided a sufficiently-sized buffer.\r
168	\r
169	**/\r
170	STATIC\r
171	EFI_STATUS\r
172	EFIAPI\r
173	SmmAccessPeiGetCapabilities (\r
174	IN EFI_PEI_SERVICES **PeiServices,\r
175	IN PEI_SMM_ACCESS_PPI *This,\r
176	IN OUT UINTN *SmramMapSize,\r
177	IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap\r
178	)\r
179	{\r
180	return SmramAccessGetCapabilities (This->LockState, This->OpenState,\r
181	SmramMapSize, SmramMap);\r
182	}\r
183	\r
184	//\r
185	// LockState and OpenState will be filled in by the entry point.\r
186	//\r
187	STATIC PEI_SMM_ACCESS_PPI mAccess = {\r
188	&SmmAccessPeiOpen,\r
189	&SmmAccessPeiClose,\r
190	&SmmAccessPeiLock,\r
191	&SmmAccessPeiGetCapabilities\r
192	};\r
193	\r
194	\r
195	STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {\r
196	{\r
197	EFI_PEI_PPI_DESCRIPTOR_PPI \| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
198	&gPeiSmmAccessPpiGuid, &mAccess\r
199	}\r
200	};\r
201	\r
202	\r
203	//\r
204	// Utility functions.\r
205	//\r
206	STATIC\r
207	UINT8\r
208	CmosRead8 (\r
209	IN UINT8 Index\r
210	)\r
211	{\r
212	IoWrite8 (0x70, Index);\r
213	return IoRead8 (0x71);\r
214	}\r
215	\r
216	STATIC\r
217	UINT32\r
218	GetSystemMemorySizeBelow4gb (\r
219	VOID\r
220	)\r
221	{\r
222	UINT32 Cmos0x34;\r
223	UINT32 Cmos0x35;\r
224	\r
225	Cmos0x34 = CmosRead8 (0x34);\r
226	Cmos0x35 = CmosRead8 (0x35);\r
227	\r
228	return ((Cmos0x35 << 8 \| Cmos0x34) << 16) + SIZE_16MB;\r
229	}\r
230	\r
231	\r
232	//\r
233	// Entry point of this driver.\r
234	//\r
235	EFI_STATUS\r
236	EFIAPI\r
237	SmmAccessPeiEntryPoint (\r
238	IN EFI_PEI_FILE_HANDLE FileHandle,\r
239	IN CONST EFI_PEI_SERVICES **PeiServices\r
240	)\r
241	{\r
242	UINT16 HostBridgeDevId;\r
243	UINT8 EsmramcVal;\r
244	UINT8 RegMask8;\r
245	UINT32 TopOfLowRam, TopOfLowRamMb;\r
246	EFI_STATUS Status;\r
247	UINTN SmramMapSize;\r
248	EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount];\r
249	VOID *GuidHob;\r
250	\r
251	//\r
252	// This module should only be included if SMRAM support is required.\r
253	//\r
254	ASSERT (FeaturePcdGet (PcdSmmSmramRequire));\r
255	\r
256	//\r
257	// Verify if we're running on a Q35 machine type.\r
258	//\r
259	HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
260	if (HostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
261	DEBUG ((EFI_D_ERROR, "%a: no SMRAM with host bridge DID=0x%04x; only "\r
262	"DID=0x%04x (Q35) is supported\n", __FUNCTION__, HostBridgeDevId,\r
263	INTEL_Q35_MCH_DEVICE_ID));\r
264	goto WrongConfig;\r
265	}\r
266	\r
267	//\r
268	// Confirm if QEMU supports SMRAM.\r
269	//\r
270	// With no support for it, the ESMRAMC (Extended System Management RAM\r
271	// Control) register reads as zero. If there is support, the cache-enable\r
272	// bits are hard-coded as 1 by QEMU.\r
273	//\r
274	EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));\r
275	RegMask8 = MCH_ESMRAMC_SM_CACHE \| MCH_ESMRAMC_SM_L1 \| MCH_ESMRAMC_SM_L2;\r
276	if ((EsmramcVal & RegMask8) != RegMask8) {\r
277	DEBUG ((EFI_D_ERROR, "%a: this Q35 implementation lacks SMRAM\n",\r
278	__FUNCTION__));\r
279	goto WrongConfig;\r
280	}\r
281	\r
282	TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
283	ASSERT ((TopOfLowRam & (SIZE_1MB - 1)) == 0);\r
284	TopOfLowRamMb = TopOfLowRam >> 20;\r
285	\r
286	//\r
287	// Some of the following registers are no-ops for QEMU at the moment, but it\r
288	// is recommended to set them correctly, since the ESMRAMC that we ultimately\r
289	// care about is in the same set of registers.\r
290	//\r
291	// First, we disable the integrated VGA, and set both the GTT Graphics Memory\r
292	// Size and the Graphics Mode Select memory pre-allocation fields to zero.\r
293	// This takes just one write to the Graphics Control Register.\r
294	//\r
295	PciWrite16 (DRAMC_REGISTER_Q35 (MCH_GGC), MCH_GGC_IVD);\r
296	\r
297	//\r
298	// Set Top of Low Usable DRAM.\r
299	//\r
300	PciWrite16 (DRAMC_REGISTER_Q35 (MCH_TOLUD),\r
301	(UINT16)(TopOfLowRamMb << MCH_TOLUD_MB_SHIFT));\r
302	\r
303	//\r
304	// Given the zero graphics memory sizes configured above, set the\r
305	// graphics-related stolen memory bases to the same as TOLUD.\r
306	//\r
307	PciWrite32 (DRAMC_REGISTER_Q35 (MCH_GBSM),\r
308	TopOfLowRamMb << MCH_GBSM_MB_SHIFT);\r
309	PciWrite32 (DRAMC_REGISTER_Q35 (MCH_BGSM),\r
310	TopOfLowRamMb << MCH_BGSM_MB_SHIFT);\r
311	\r
312	//\r
313	// Set TSEG Memory Base.\r
314	//\r
1372f8d3	315	InitQ35TsegMbytes ();\r
9d560947	316	PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB),\r
1372f8d3	317	(TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT);\r
9d560947 LE	318	\r
	319	//\r
	320	// Set TSEG size, and disable TSEG visibility outside of SMM. Note that the\r
	321	// T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility is\r
	322	// restricted to SMM.\r
	323	//\r
	324	EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK;\r
1372f8d3 LE	325	EsmramcVal \|= mQ35TsegMbytes == 8 ? MCH_ESMRAMC_TSEG_8MB :\r
1372f8d3 LE	326	mQ35TsegMbytes == 2 ? MCH_ESMRAMC_TSEG_2MB :\r
6812bb7b LE	327	mQ35TsegMbytes == 1 ? MCH_ESMRAMC_TSEG_1MB :\r
6812bb7b LE	328	MCH_ESMRAMC_TSEG_EXT;\r
9d560947 LE	329	EsmramcVal \|= MCH_ESMRAMC_T_EN;\r
	330	PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal);\r
	331	\r
	332	//\r
	333	// TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME\r
	334	// (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it.\r
	335	//\r
	336	PciAndThenOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM),\r
	337	(UINT8)((~(UINT32)MCH_SMRAM_D_LCK) & 0xff), MCH_SMRAM_G_SMRAME);\r
	338	\r
	339	//\r
	340	// Create the GUID HOB and point it to the first SMRAM range.\r
	341	//\r
	342	GetStates (&mAccess.LockState, &mAccess.OpenState);\r
	343	SmramMapSize = sizeof SmramMap;\r
	344	Status = SmramAccessGetCapabilities (mAccess.LockState, mAccess.OpenState,\r
	345	&SmramMapSize, SmramMap);\r
	346	ASSERT_EFI_ERROR (Status);\r
	347	\r
	348	DEBUG_CODE_BEGIN ();\r
	349	{\r
	350	UINTN Count;\r
	351	UINTN Idx;\r
	352	\r
	353	Count = SmramMapSize / sizeof SmramMap[0];\r
	354	DEBUG ((EFI_D_VERBOSE, "%a: SMRAM map follows, %d entries\n", __FUNCTION__,\r
	355	(INT32)Count));\r
	356	DEBUG ((EFI_D_VERBOSE, "% 20a % 20a % 20a % 20a\n", "PhysicalStart(0x)",\r
	357	"PhysicalSize(0x)", "CpuStart(0x)", "RegionState(0x)"));\r
	358	for (Idx = 0; Idx < Count; ++Idx) {\r
	359	DEBUG ((EFI_D_VERBOSE, "% 20Lx % 20Lx % 20Lx % 20Lx\n",\r
	360	SmramMap[Idx].PhysicalStart, SmramMap[Idx].PhysicalSize,\r
	361	SmramMap[Idx].CpuStart, SmramMap[Idx].RegionState));\r
	362	}\r
	363	}\r
	364	DEBUG_CODE_END ();\r
	365	\r
	366	GuidHob = BuildGuidHob (&gEfiAcpiVariableGuid,\r
	367	sizeof SmramMap[DescIdxSmmS3ResumeState]);\r
	368	if (GuidHob == NULL) {\r
	369	return EFI_OUT_OF_RESOURCES;\r
	370	}\r
	371	\r
	372	CopyMem (GuidHob, &SmramMap[DescIdxSmmS3ResumeState],\r
	373	sizeof SmramMap[DescIdxSmmS3ResumeState]);\r
	374	\r
	375	//\r
	376	// We're done. The next step should succeed, but even if it fails, we can't\r
	377	// roll back the above BuildGuidHob() allocation, because PEI doesn't support\r
	378	// releasing memory.\r
	379	//\r
	380	return PeiServicesInstallPpi (mPpiList);\r
	381	\r
	382	WrongConfig:\r
	383	//\r
	384	// We really don't want to continue in this case.\r
	385	//\r
	386	ASSERT (FALSE);\r
	387	CpuDeadLoop ();\r
	388	return EFI_UNSUPPORTED;\r
	389	}\r