OvmfPkg: implement EFI_SMM_CONTROL2_PROTOCOL with a DXE_RUNTIME_DRIVER

[mirror_edk2.git] / OvmfPkg / SmmControl2Dxe / SmmControl2Dxe.c

/** @file\r
\r
  A DXE_RUNTIME_DRIVER providing synchronous SMI activations via the\r
  EFI_SMM_CONTROL2_PROTOCOL.\r
\r
  We expect the PEI phase to have covered the following:\r
  - ensure that the underlying QEMU machine type be Q35\r
    (responsible: OvmfPkg/SmmAccess/SmmAccessPei.inf)\r
  - ensure that the ACPI PM IO space be configured\r
    (responsible: OvmfPkg/PlatformPei/PlatformPei.inf)\r
\r
  Our own entry point is responsible for confirming the SMI feature and for\r
  configuring it.\r
\r
  Copyright (C) 2013, 2015, Red Hat, Inc.<BR>\r
  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
\r
  This program and the accompanying materials are licensed and made available\r
  under the terms and conditions of the BSD License which accompanies this\r
  distribution. The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Protocol/S3SaveState.h>\r
#include <Protocol/SmmControl2.h>\r
\r
//\r
// Forward declaration.\r
//\r
STATIC\r
VOID\r
EFIAPI\r
OnS3SaveStateInstalled (\r
  IN EFI_EVENT Event,\r
  IN VOID      *Context\r
  );\r
\r
//\r
// The absolute IO port address of the SMI Control and Enable Register. It is\r
// only used to carry information from the entry point function to the\r
// S3SaveState protocol installation callback, strictly before the runtime\r
// phase.\r
//\r
STATIC UINTN mSmiEnable;\r
\r
//\r
// Event signaled when an S3SaveState protocol interface is installed.\r
//\r
STATIC EFI_EVENT mS3SaveStateInstalled;\r
\r
/**\r
  Invokes SMI activation from either the preboot or runtime environment.\r
\r
  This function generates an SMI.\r
\r
  @param[in]     This                The EFI_SMM_CONTROL2_PROTOCOL instance.\r
  @param[in,out] CommandPort         The value written to the command port.\r
  @param[in,out] DataPort            The value written to the data port.\r
  @param[in]     Periodic            Optional mechanism to engender a periodic\r
                                     stream.\r
  @param[in]     ActivationInterval  Optional parameter to repeat at this\r
                                     period one time or, if the Periodic\r
                                     Boolean is set, periodically.\r
\r
  @retval EFI_SUCCESS            The SMI/PMI has been engendered.\r
  @retval EFI_DEVICE_ERROR       The timing is unsupported.\r
  @retval EFI_INVALID_PARAMETER  The activation period is unsupported.\r
  @retval EFI_INVALID_PARAMETER  The last periodic activation has not been\r
                                 cleared.\r
  @retval EFI_NOT_STARTED        The SMM base service has not been initialized.\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
SmmControl2DxeTrigger (\r
  IN CONST EFI_SMM_CONTROL2_PROTOCOL  *This,\r
  IN OUT UINT8                        *CommandPort       OPTIONAL,\r
  IN OUT UINT8                        *DataPort          OPTIONAL,\r
  IN BOOLEAN                          Periodic           OPTIONAL,\r
  IN UINTN                            ActivationInterval OPTIONAL\r
  )\r
{\r
  //\r
  // No support for queued or periodic activation.\r
  //\r
  if (Periodic || ActivationInterval > 0) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  //\r
  // The so-called "Advanced Power Management Status Port Register" is in fact\r
  // a generic data passing register, between the caller and the SMI\r
  // dispatcher. The ICH9 spec calls it "scratchpad register" --  calling it\r
  // "status" elsewhere seems quite the misnomer. Status registers usually\r
  // report about hardware status, while this register is fully governed by\r
  // software.\r
  //\r
  // Write to the status register first, as this won't trigger the SMI just\r
  // yet. Then write to the control register.\r
  //\r
  IoWrite8 (ICH9_APM_STS, DataPort    == NULL ? 0 : *DataPort);\r
  IoWrite8 (ICH9_APM_CNT, CommandPort == NULL ? 0 : *CommandPort);\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Clears any system state that was created in response to the Trigger() call.\r
\r
  This function acknowledges and causes the deassertion of the SMI activation\r
  source.\r
\r
  @param[in] This                The EFI_SMM_CONTROL2_PROTOCOL instance.\r
  @param[in] Periodic            Optional parameter to repeat at this period\r
                                 one time\r
\r
  @retval EFI_SUCCESS            The SMI/PMI has been engendered.\r
  @retval EFI_DEVICE_ERROR       The source could not be cleared.\r
  @retval EFI_INVALID_PARAMETER  The service did not support the Periodic input\r
                                 argument.\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
SmmControl2DxeClear (\r
  IN CONST EFI_SMM_CONTROL2_PROTOCOL  *This,\r
  IN BOOLEAN                          Periodic OPTIONAL\r
  )\r
{\r
  if (Periodic) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // The PI spec v1.4 explains that Clear() is only supposed to clear software\r
  // status; it is not in fact responsible for deasserting the SMI. It gives\r
  // two reasons for this: (a) many boards clear the SMI automatically when\r
  // entering SMM, (b) if Clear() actually deasserted the SMI, then it could\r
  // incorrectly suppress an SMI that was asynchronously asserted between the\r
  // last return of the SMI handler and the call made to Clear().\r
  //\r
  // In fact QEMU automatically deasserts CPU_INTERRUPT_SMI in:\r
  // - x86_cpu_exec_interrupt() [target-i386/seg_helper.c], and\r
  // - kvm_arch_pre_run() [target-i386/kvm.c].\r
  //\r
  // So, nothing to do here.\r
  //\r
  return EFI_SUCCESS;\r
}\r
\r
STATIC EFI_SMM_CONTROL2_PROTOCOL mControl2 = {\r
  &SmmControl2DxeTrigger,\r
  &SmmControl2DxeClear,\r
  MAX_UINTN // MinimumTriggerPeriod -- we don't support periodic SMIs\r
};\r
\r
//\r
// Entry point of this driver.\r
//\r
EFI_STATUS\r
EFIAPI\r
SmmControl2DxeEntryPoint (\r
  IN EFI_HANDLE       ImageHandle,\r
  IN EFI_SYSTEM_TABLE *SystemTable\r
  )\r
{\r
  UINT32     PmBase;\r
  UINT32     SmiEnableVal;\r
  EFI_STATUS Status;\r
\r
  //\r
  // This module should only be included if SMRAM support is required.\r
  //\r
  ASSERT (FeaturePcdGet (PcdSmmSmramRequire));\r
\r
  //\r
  // Calculate the absolute IO port address of the SMI Control and Enable\r
  // Register. (As noted at the top, the PEI phase has left us with a working\r
  // ACPI PM IO space.)\r
  //\r
  PmBase = PciRead32 (POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE)) &\r
    ICH9_PMBASE_MASK;\r
  mSmiEnable = PmBase + ICH9_PMBASE_OFS_SMI_EN;\r
\r
  //\r
  // If APMC_EN is pre-set in SMI_EN, that's QEMU's way to tell us that SMI\r
  // support is not available. (For example due to KVM lacking it.) Otherwise,\r
  // this bit is clear after each reset.\r
  //\r
  SmiEnableVal = IoRead32 (mSmiEnable);\r
  if ((SmiEnableVal & ICH9_SMI_EN_APMC_EN) != 0) {\r
    DEBUG ((EFI_D_ERROR, "%a: this Q35 implementation lacks SMI\n",\r
      __FUNCTION__));\r
    goto FatalError;\r
  }\r
\r
  //\r
  // Otherwise, configure the board to inject an SMI when ICH9_APM_CNT is\r
  // written to. (See the Trigger() method above.)\r
  //\r
  SmiEnableVal |= ICH9_SMI_EN_APMC_EN | ICH9_SMI_EN_GBL_SMI_EN;\r
  IoWrite32 (mSmiEnable, SmiEnableVal);\r
\r
  //\r
  // Prevent software from undoing the above (until platform reset).\r
  //\r
  PciOr16 (POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1),\r
    ICH9_GEN_PMCON_1_SMI_LOCK);\r
\r
  //\r
  // If we can clear GBL_SMI_EN now, that means QEMU's SMI support is not\r
  // appropriate.\r
  //\r
  IoWrite32 (mSmiEnable, SmiEnableVal & ~(UINT32)ICH9_SMI_EN_GBL_SMI_EN);\r
  if (IoRead32 (mSmiEnable) != SmiEnableVal) {\r
    DEBUG ((EFI_D_ERROR, "%a: failed to lock down GBL_SMI_EN\n",\r
      __FUNCTION__));\r
    goto FatalError;\r
  }\r
\r
  if (QemuFwCfgS3Enabled ()) {\r
    VOID *Registration;\r
\r
    //\r
    // On S3 resume the above register settings have to be repeated. Register a\r
    // protocol notify callback that, when boot script saving becomes\r
    // available, saves operations equivalent to the above to the boot script.\r
    //\r
    Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,\r
                    OnS3SaveStateInstalled, NULL /* Context */,\r
                    &mS3SaveStateInstalled);\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((EFI_D_ERROR, "%a: CreateEvent: %r\n", __FUNCTION__, Status));\r
      goto FatalError;\r
    }\r
\r
    Status = gBS->RegisterProtocolNotify (&gEfiS3SaveStateProtocolGuid,\r
                    mS3SaveStateInstalled, &Registration);\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((EFI_D_ERROR, "%a: RegisterProtocolNotify: %r\n", __FUNCTION__,\r
        Status));\r
      goto ReleaseEvent;\r
    }\r
\r
    //\r
    // Kick the event right now -- maybe the boot script is already saveable.\r
    //\r
    Status = gBS->SignalEvent (mS3SaveStateInstalled);\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((EFI_D_ERROR, "%a: SignalEvent: %r\n", __FUNCTION__, Status));\r
      goto ReleaseEvent;\r
    }\r
  }\r
\r
  //\r
  // We have no pointers to convert to virtual addresses. The handle itself\r
  // doesn't matter, as protocol services are not accessible at runtime.\r
  //\r
  Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,\r
                  &gEfiSmmControl2ProtocolGuid, &mControl2,\r
                  NULL);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "%a: InstallMultipleProtocolInterfaces: %r\n",\r
      __FUNCTION__, Status));\r
    goto ReleaseEvent;\r
  }\r
\r
  return EFI_SUCCESS;\r
\r
ReleaseEvent:\r
  if (mS3SaveStateInstalled != NULL) {\r
    gBS->CloseEvent (mS3SaveStateInstalled);\r
  }\r
\r
FatalError:\r
  //\r
  // We really don't want to continue in this case.\r
  //\r
  ASSERT (FALSE);\r
  CpuDeadLoop ();\r
  return EFI_UNSUPPORTED;\r
}\r
\r
/**\r
  Notification callback for S3SaveState installation.\r
\r
  @param[in] Event    Event whose notification function is being invoked.\r
\r
  @param[in] Context  The pointer to the notification function's context, which\r
                      is implementation-dependent.\r
**/\r
STATIC\r
VOID\r
EFIAPI\r
OnS3SaveStateInstalled (\r
  IN EFI_EVENT Event,\r
  IN VOID      *Context\r
  )\r
{\r
  EFI_STATUS                 Status;\r
  EFI_S3_SAVE_STATE_PROTOCOL *S3SaveState;\r
  UINT32                     SmiEnOrMask, SmiEnAndMask;\r
  UINT16                     GenPmCon1OrMask, GenPmCon1AndMask;\r
\r
  ASSERT (Event == mS3SaveStateInstalled);\r
\r
  Status = gBS->LocateProtocol (&gEfiS3SaveStateProtocolGuid,\r
                  NULL /* Registration */, (VOID **)&S3SaveState);\r
  if (EFI_ERROR (Status)) {\r
    return;\r
  }\r
\r
  //\r
  // These operations were originally done, verified and explained in the entry\r
  // point function of the driver.\r
  //\r
  SmiEnOrMask  = ICH9_SMI_EN_APMC_EN | ICH9_SMI_EN_GBL_SMI_EN;\r
  SmiEnAndMask = MAX_UINT32;\r
  Status = S3SaveState->Write (\r
                          S3SaveState,\r
                          EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE,\r
                          EfiBootScriptWidthUint32,\r
                          (UINT64)mSmiEnable,\r
                          &SmiEnOrMask,\r
                          &SmiEnAndMask\r
                          );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "%a: EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE: %r\n",\r
      __FUNCTION__, Status));\r
    ASSERT (FALSE);\r
    CpuDeadLoop ();\r
  }\r
\r
  GenPmCon1OrMask  = ICH9_GEN_PMCON_1_SMI_LOCK;\r
  GenPmCon1AndMask = MAX_UINT16;\r
  Status = S3SaveState->Write (\r
                          S3SaveState,\r
                          EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE,\r
                          EfiBootScriptWidthUint16,\r
                          (UINT64)POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1),\r
                          &GenPmCon1OrMask,\r
                          &GenPmCon1AndMask\r
                          );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR,\r
      "%a: EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE: %r\n", __FUNCTION__,\r
      Status));\r
    ASSERT (FALSE);\r
    CpuDeadLoop ();\r
  }\r
\r
  DEBUG ((EFI_D_VERBOSE, "%a: boot script fragment saved\n", __FUNCTION__));\r
  gBS->CloseEvent (Event);\r
  mS3SaveStateInstalled = NULL;\r
}\r