OvmfPkg: Apply uncrustify changes

[mirror_edk2.git] / OvmfPkg / XenPlatformPei / MemDetect.c

/**@file\r
  Memory Detection for Virtual Machines.\r
\r
  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
  Copyright (c) 2019, Citrix Systems, Inc.\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
Module Name:\r
\r
  MemDetect.c\r
\r
**/\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <PiPei.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/ResourcePublicationLib.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
\r
UINT8  mPhysMemAddressWidth;\r
\r
STATIC UINT32  mS3AcpiReservedMemoryBase;\r
STATIC UINT32  mS3AcpiReservedMemorySize;\r
\r
STATIC UINT16  mQ35TsegMbytes;\r
\r
VOID\r
Q35TsegMbytesInitialization (\r
  VOID\r
  )\r
{\r
  UINT16         ExtendedTsegMbytes;\r
  RETURN_STATUS  PcdStatus;\r
\r
  if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
    DEBUG ((\r
      DEBUG_ERROR,\r
      "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r
      "only DID=0x%04x (Q35) is supported\n",\r
      __FUNCTION__,\r
      mHostBridgeDevId,\r
      INTEL_Q35_MCH_DEVICE_ID\r
      ));\r
    ASSERT (FALSE);\r
    CpuDeadLoop ();\r
  }\r
\r
  //\r
  // Check if QEMU offers an extended TSEG.\r
  //\r
  // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB\r
  // register, and reading back the register.\r
  //\r
  // On a QEMU machine type that does not offer an extended TSEG, the initial\r
  // write overwrites whatever value a malicious guest OS may have placed in\r
  // the (unimplemented) register, before entering S3 or rebooting.\r
  // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.\r
  //\r
  // On a QEMU machine type that offers an extended TSEG, the initial write\r
  // triggers an update to the register. Subsequently, the value read back\r
  // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the\r
  // number of megabytes.\r
  //\r
  PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);\r
  ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));\r
  if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {\r
    mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r
    return;\r
  }\r
\r
  DEBUG ((\r
    DEBUG_INFO,\r
    "%a: QEMU offers an extended TSEG (%d MB)\n",\r
    __FUNCTION__,\r
    ExtendedTsegMbytes\r
    ));\r
  PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
  mQ35TsegMbytes = ExtendedTsegMbytes;\r
}\r
\r
STATIC\r
UINT64\r
GetHighestSystemMemoryAddress (\r
  BOOLEAN  Below4gb\r
  )\r
{\r
  EFI_E820_ENTRY64  *E820Map;\r
  UINT32            E820EntriesCount;\r
  EFI_E820_ENTRY64  *Entry;\r
  EFI_STATUS        Status;\r
  UINT32            Loop;\r
  UINT64            HighestAddress;\r
  UINT64            EntryEnd;\r
\r
  HighestAddress = 0;\r
\r
  Status = XenGetE820Map (&E820Map, &E820EntriesCount);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  for (Loop = 0; Loop < E820EntriesCount; Loop++) {\r
    Entry    = E820Map + Loop;\r
    EntryEnd = Entry->BaseAddr + Entry->Length;\r
\r
    if ((Entry->Type == EfiAcpiAddressRangeMemory) &&\r
        (EntryEnd > HighestAddress))\r
    {\r
      if (Below4gb && (EntryEnd <= BASE_4GB)) {\r
        HighestAddress = EntryEnd;\r
      } else if (!Below4gb && (EntryEnd >= BASE_4GB)) {\r
        HighestAddress = EntryEnd;\r
      }\r
    }\r
  }\r
\r
  //\r
  // Round down the end address.\r
  //\r
  return HighestAddress & ~(UINT64)EFI_PAGE_MASK;\r
}\r
\r
UINT32\r
GetSystemMemorySizeBelow4gb (\r
  VOID\r
  )\r
{\r
  UINT8  Cmos0x34;\r
  UINT8  Cmos0x35;\r
\r
  //\r
  // In PVH case, there is no CMOS, we have to calculate the memory size\r
  // from parsing the E820\r
  //\r
  if (XenPvhDetected ()) {\r
    UINT64  HighestAddress;\r
\r
    HighestAddress = GetHighestSystemMemoryAddress (TRUE);\r
    ASSERT (HighestAddress > 0 && HighestAddress <= BASE_4GB);\r
\r
    return (UINT32)HighestAddress;\r
  }\r
\r
  //\r
  // CMOS 0x34/0x35 specifies the system memory above 16 MB.\r
  // * CMOS(0x35) is the high byte\r
  // * CMOS(0x34) is the low byte\r
  // * The size is specified in 64kb chunks\r
  // * Since this is memory above 16MB, the 16MB must be added\r
  //   into the calculation to get the total memory size.\r
  //\r
\r
  Cmos0x34 = (UINT8)CmosRead8 (0x34);\r
  Cmos0x35 = (UINT8)CmosRead8 (0x35);\r
\r
  return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r
}\r
\r
/**\r
  Initialize the mPhysMemAddressWidth variable, based on CPUID data.\r
**/\r
VOID\r
AddressWidthInitialization (\r
  VOID\r
  )\r
{\r
  UINT32  RegEax;\r
\r
  AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
  if (RegEax >= 0x80000008) {\r
    AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
    mPhysMemAddressWidth = (UINT8)RegEax;\r
  } else {\r
    mPhysMemAddressWidth = 36;\r
  }\r
\r
  //\r
  // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.\r
  //\r
  ASSERT (mPhysMemAddressWidth <= 52);\r
  if (mPhysMemAddressWidth > 48) {\r
    mPhysMemAddressWidth = 48;\r
  }\r
}\r
\r
/**\r
  Calculate the cap for the permanent PEI memory.\r
**/\r
STATIC\r
UINT32\r
GetPeiMemoryCap (\r
  VOID\r
  )\r
{\r
  BOOLEAN  Page1GSupport;\r
  UINT32   RegEax;\r
  UINT32   RegEdx;\r
  UINT32   Pml4Entries;\r
  UINT32   PdpEntries;\r
  UINTN    TotalPages;\r
\r
  //\r
  // If DXE is 32-bit, then just return the traditional 64 MB cap.\r
  //\r
 #ifdef MDE_CPU_IA32\r
  if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
    return SIZE_64MB;\r
  }\r
\r
 #endif\r
\r
  //\r
  // Dependent on physical address width, PEI memory allocations can be\r
  // dominated by the page tables built for 64-bit DXE. So we key the cap off\r
  // of those. The code below is based on CreateIdentityMappingPageTables() in\r
  // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".\r
  //\r
  Page1GSupport = FALSE;\r
  if (PcdGetBool (PcdUse1GPageTable)) {\r
    AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
    if (RegEax >= 0x80000001) {\r
      AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
      if ((RegEdx & BIT26) != 0) {\r
        Page1GSupport = TRUE;\r
      }\r
    }\r
  }\r
\r
  if (mPhysMemAddressWidth <= 39) {\r
    Pml4Entries = 1;\r
    PdpEntries  = 1 << (mPhysMemAddressWidth - 30);\r
    ASSERT (PdpEntries <= 0x200);\r
  } else {\r
    Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r
    ASSERT (Pml4Entries <= 0x200);\r
    PdpEntries = 512;\r
  }\r
\r
  TotalPages = Page1GSupport ? Pml4Entries + 1 :\r
               (PdpEntries + 1) * Pml4Entries + 1;\r
  ASSERT (TotalPages <= 0x40201);\r
\r
  //\r
  // Add 64 MB for miscellaneous allocations. Note that for\r
  // mPhysMemAddressWidth values close to 36, the cap will actually be\r
  // dominated by this increment.\r
  //\r
  return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r
}\r
\r
/**\r
  Publish PEI core memory\r
\r
  @return EFI_SUCCESS     The PEIM initialized successfully.\r
\r
**/\r
EFI_STATUS\r
PublishPeiMemory (\r
  VOID\r
  )\r
{\r
  EFI_STATUS            Status;\r
  EFI_PHYSICAL_ADDRESS  MemoryBase;\r
  UINT64                MemorySize;\r
  UINT32                LowerMemorySize;\r
  UINT32                PeiMemoryCap;\r
\r
  LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
\r
  if (mBootMode == BOOT_ON_S3_RESUME) {\r
    MemoryBase = mS3AcpiReservedMemoryBase;\r
    MemorySize = mS3AcpiReservedMemorySize;\r
  } else {\r
    PeiMemoryCap = GetPeiMemoryCap ();\r
    DEBUG ((\r
      DEBUG_INFO,\r
      "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
      __FUNCTION__,\r
      mPhysMemAddressWidth,\r
      PeiMemoryCap >> 10\r
      ));\r
\r
    //\r
    // Determine the range of memory to use during PEI\r
    //\r
    MemoryBase =\r
      PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r
    MemorySize = LowerMemorySize - MemoryBase;\r
    if (MemorySize > PeiMemoryCap) {\r
      MemoryBase = LowerMemorySize - PeiMemoryCap;\r
      MemorySize = PeiMemoryCap;\r
    }\r
  }\r
\r
  //\r
  // Publish this memory to the PEI Core\r
  //\r
  Status = PublishSystemMemory (MemoryBase, MemorySize);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return Status;\r
}\r
\r
/**\r
  Publish system RAM and reserve memory regions\r
\r
**/\r
VOID\r
InitializeRamRegions (\r
  VOID\r
  )\r
{\r
  XenPublishRamRegions ();\r
\r
  if (mBootMode != BOOT_ON_S3_RESUME) {\r
    //\r
    // Reserve the lock box storage area\r
    //\r
    // Since this memory range will be used on S3 resume, it must be\r
    // reserved as ACPI NVS.\r
    //\r
    // If S3 is unsupported, then various drivers might still write to the\r
    // LockBox area. We ought to prevent DXE from serving allocation requests\r
    // such that they would overlap the LockBox storage.\r
    //\r
    ZeroMem (\r
      (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r
      (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize)\r
      );\r
    BuildMemoryAllocationHob (\r
      (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r
      (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),\r
      EfiBootServicesData\r
      );\r
  }\r
}\r