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986d1dfb | 1 | /** @file\r |
2 | Public include file for I/O APIC library.\r | |
3 | \r | |
4 | I/O APIC library assumes I/O APIC is enabled. It does not\r | |
5 | handles cases where I/O APIC is disabled.\r | |
6 | \r | |
5a702acd | 7 | Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r |
e1d302e5 | 8 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
986d1dfb | 9 | \r |
10 | **/\r | |
5220bd21 | 11 | \r |
8e22eab8 ED |
12 | #ifndef __IO_APIC_LIB_H__\r |
13 | #define __IO_APIC_LIB_H__\r | |
986d1dfb | 14 | \r |
15 | /**\r | |
16 | Read a 32-bit I/O APIC register.\r | |
17 | \r | |
18 | If Index is >= 0x100, then ASSERT().\r | |
5a702acd | 19 | \r |
986d1dfb | 20 | @param Index Specifies the I/O APIC register to read.\r |
21 | \r | |
22 | @return The 32-bit value read from the I/O APIC register specified by Index.\r | |
23 | **/\r | |
24 | UINT32\r | |
25 | EFIAPI\r | |
26 | IoApicRead (\r | |
27 | IN UINTN Index\r | |
28 | );\r | |
29 | \r | |
30 | /**\r | |
31 | Write a 32-bit I/O APIC register.\r | |
32 | \r | |
33 | If Index is >= 0x100, then ASSERT().\r | |
5a702acd | 34 | \r |
986d1dfb | 35 | @param Index Specifies the I/O APIC register to write.\r |
36 | @param Value Specifies the value to write to the I/O APIC register specified by Index.\r | |
37 | \r | |
38 | @return The 32-bit value written to I/O APIC register specified by Index.\r | |
39 | **/\r | |
40 | UINT32\r | |
41 | EFIAPI\r | |
42 | IoApicWrite (\r | |
43 | IN UINTN Index,\r | |
44 | IN UINT32 Value\r | |
45 | );\r | |
46 | \r | |
47 | /**\r | |
48 | Set the interrupt mask of an I/O APIC interrupt.\r | |
49 | \r | |
5a702acd LG |
50 | If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().\r |
51 | \r | |
986d1dfb | 52 | @param Irq Specifies the I/O APIC interrupt to enable or disable.\r |
53 | @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.\r | |
54 | If FALSE, then disable the I/O APIC interrupt specified by Irq.\r | |
55 | **/\r | |
56 | VOID\r | |
57 | EFIAPI\r | |
58 | IoApicEnableInterrupt (\r | |
59 | IN UINTN Irq,\r | |
60 | IN BOOLEAN Enable\r | |
61 | );\r | |
62 | \r | |
63 | /**\r | |
64 | Configures an I/O APIC interrupt.\r | |
5a702acd | 65 | \r |
986d1dfb | 66 | Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical\r |
53b1dd10 | 67 | mode to the Local APIC of the currently executing CPU. The default state of the\r |
986d1dfb | 68 | entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must\r |
69 | be used to enable(unmask) the I/O APIC Interrupt.\r | |
70 | \r | |
5a702acd | 71 | If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().\r |
986d1dfb | 72 | If Vector >= 0x100, then ASSERT().\r |
73 | If DeliveryMode is not supported, then ASSERT().\r | |
74 | \r | |
75 | @param Irq Specifies the I/O APIC interrupt to initialize.\r | |
76 | @param Vector The 8-bit interrupt vector associated with the I/O APIC\r | |
77 | Interrupt. Must be in the range 0x10..0xFE.\r | |
78 | @param DeliveryMode A 3-bit value that specifies how the recept of the I/O APIC\r | |
79 | interrupt is handled. The only supported values are:\r | |
80 | 0: IO_APIC_DELIVERY_MODE_FIXED\r | |
81 | 1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r | |
82 | 2: IO_APIC_DELIVERY_MODE_SMI\r | |
83 | 4: IO_APIC_DELIVERY_MODE_NMI\r | |
84 | 5: IO_APIC_DELIVERY_MODE_INIT\r | |
85 | 7: IO_APIC_DELIVERY_MODE_EXTINT\r | |
86 | @param LevelTriggered TRUE specifies a level triggered interrupt.\r | |
87 | FALSE specifies an edge triggered interrupt.\r | |
88 | @param AssertionLevel TRUE specified an active high interrupt.\r | |
89 | FALSE specifies an active low interrupt.\r | |
90 | **/\r | |
91 | VOID\r | |
92 | EFIAPI\r | |
93 | IoApicConfigureInterrupt (\r | |
94 | IN UINTN Irq,\r | |
95 | IN UINTN Vector,\r | |
96 | IN UINTN DeliveryMode,\r | |
97 | IN BOOLEAN LevelTriggered,\r | |
98 | IN BOOLEAN AssertionLevel\r | |
99 | );\r | |
5220bd21 | 100 | \r |
8e22eab8 | 101 | #endif\r |