projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 21b404d1 | 1 | /** @file\r |
| 90ac6ac2 | 2 | The Header file of the Pci Host Bridge Driver\r |
| 21b404d1 | 3 | \r |
| cac2ab95 | 4 | Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r |
| 90ac6ac2 LE |
5 | \r |
| 6 | This program and the accompanying materials are licensed and made available\r | |
| 7 | under the terms and conditions of the BSD License which accompanies this\r | |
| 8 | distribution. The full text of the license may be found at\r | |
| 21b404d1 | 9 | http://opensource.org/licenses/bsd-license.php\r |
| 90ac6ac2 | 10 | \r |
| 21b404d1 | 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 90ac6ac2 | 13 | **/\r |
| 21b404d1 | 14 | \r |
| 15 | #ifndef _PCI_HOST_BRIDGE_H_\r | |
| 16 | #define _PCI_HOST_BRIDGE_H_\r | |
| 17 | \r | |
| 18 | #include <PiDxe.h>\r | |
| 19 | \r | |
| 20 | #include <IndustryStandard/Pci.h>\r | |
| 21 | #include <IndustryStandard/Acpi.h>\r | |
| 22 | \r | |
| 23 | #include <Protocol/PciHostBridgeResourceAllocation.h>\r | |
| 24 | #include <Protocol/PciRootBridgeIo.h>\r | |
| 21b404d1 | 25 | #include <Protocol/Metronome.h>\r |
| 26 | #include <Protocol/DevicePath.h>\r | |
| 27 | \r | |
| 28 | \r | |
| 29 | #include <Library/BaseLib.h>\r | |
| 30 | #include <Library/DebugLib.h>\r | |
| 31 | #include <Library/BaseMemoryLib.h>\r | |
| 32 | #include <Library/MemoryAllocationLib.h>\r | |
| 33 | #include <Library/UefiLib.h>\r | |
| 34 | #include <Library/UefiBootServicesTableLib.h>\r | |
| 35 | #include <Library/DxeServicesTableLib.h>\r | |
| 36 | #include <Library/DevicePathLib.h>\r | |
| cac2ab95 | 37 | #include <Library/IoLib.h>\r |
| 38 | #include <Library/PciLib.h>\r | |
| 21b404d1 | 39 | \r |
| 40 | //\r | |
| 41 | // Hard code the host bridge number in the platform.\r | |
| 42 | // In this chipset, there is only one host bridge.\r | |
| 43 | //\r | |
| 44 | #define HOST_BRIDGE_NUMBER 1\r | |
| 45 | \r | |
| cac2ab95 | 46 | #define MAX_PCI_DEVICE_NUMBER 31\r |
| 47 | #define MAX_PCI_FUNCTION_NUMBER 7\r | |
| 48 | #define MAX_PCI_REG_ADDRESS 0xFF\r | |
| 49 | \r | |
| 50 | typedef enum {\r | |
| 51 | IoOperation,\r | |
| 52 | MemOperation,\r | |
| 53 | PciOperation\r | |
| 54 | } OPERATION_TYPE;\r | |
| 55 | \r | |
| 21b404d1 | 56 | #define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')\r |
| 57 | typedef struct {\r | |
| 58 | UINTN Signature;\r | |
| 59 | EFI_HANDLE HostBridgeHandle;\r | |
| 60 | UINTN RootBridgeNumber;\r | |
| 61 | LIST_ENTRY Head;\r | |
| 947b1f3c LE |
62 | BOOLEAN ResourceSubmited;\r |
| 63 | BOOLEAN CanRestarted;\r | |
| 21b404d1 | 64 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;\r |
| 65 | } PCI_HOST_BRIDGE_INSTANCE;\r | |
| 66 | \r | |
| 67 | #define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \\r | |
| 68 | CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r | |
| 947b1f3c | 69 | \r |
| 21b404d1 | 70 | //\r |
| 71 | // HostBridge Resource Allocation interface\r | |
| 72 | //\r | |
| 24115e44 ED |
73 | \r |
| 74 | /**\r | |
| 90ac6ac2 LE |
75 | These are the notifications from the PCI bus driver that it is about to enter\r |
| 76 | a certain phase of the PCI enumeration process.\r | |
| 77 | \r | |
| 78 | This member function can be used to notify the host bridge driver to perform\r | |
| 79 | specific actions, including any chipset-specific initialization, so that the\r | |
| 80 | chipset is ready to enter the next phase. Eight notification points are\r | |
| 81 | defined at this time. See belows:\r | |
| 82 | \r | |
| 83 | EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures\r | |
| 84 | and internal data structures. The PCI\r | |
| 85 | enumerator should issue this\r | |
| 86 | notification before starting a fresh\r | |
| 87 | enumeration process. Enumeration\r | |
| 88 | cannot be restarted after sending any\r | |
| 89 | other notification such as\r | |
| 90 | EfiPciHostBridgeBeginBusAllocation.\r | |
| 91 | \r | |
| 92 | EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to\r | |
| 93 | begin. No specific action is required\r | |
| 94 | here. This notification can be used to\r | |
| 95 | perform any chipset-specific\r | |
| 96 | programming.\r | |
| 97 | \r | |
| 98 | EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming\r | |
| 99 | phase is complete. No specific action\r | |
| 100 | is required here. This notification\r | |
| 101 | can be used to perform any\r | |
| 102 | chipset-specific programming.\r | |
| 103 | \r | |
| 104 | EfiPciHostBridgeBeginResourceAllocation\r | |
| 105 | The resource allocation phase is about\r | |
| 106 | to begin. No specific action is\r | |
| 107 | required here. This notification can\r | |
| 108 | be used to perform any\r | |
| 109 | chipset-specific programming.\r | |
| 110 | \r | |
| 111 | EfiPciHostBridgeAllocateResources Allocates resources per previously\r | |
| 112 | submitted requests for all the PCI\r | |
| 113 | root bridges. These resource settings\r | |
| 114 | are returned on the next call to\r | |
| 115 | GetProposedResources(). Before calling\r | |
| 116 | NotifyPhase() with a Phase of\r | |
| 117 | EfiPciHostBridgeAllocateResource, the\r | |
| 118 | PCI bus enumerator is responsible for\r | |
| 119 | gathering I/O and memory requests for\r | |
| 120 | all the PCI root bridges and\r | |
| 121 | submitting these requests using\r | |
| 122 | SubmitResources(). This function pads\r | |
| 123 | the resource amount to suit the root\r | |
| 124 | bridge hardware, takes care of\r | |
| 125 | dependencies between the PCI root\r | |
| 126 | bridges, and calls the Global\r | |
| 127 | Coherency Domain (GCD) with the\r | |
| 128 | allocation request. In the case of\r | |
| 129 | padding, the allocated range could be\r | |
| 130 | bigger than what was requested.\r | |
| 131 | \r | |
| 132 | EfiPciHostBridgeSetResources Programs the host bridge hardware to\r | |
| 133 | decode previously allocated resources\r | |
| 134 | (proposed resources) for all the PCI\r | |
| 135 | root bridges. After the hardware is\r | |
| 136 | programmed, reassigning resources will\r | |
| 137 | not be supported. The bus settings are\r | |
| 138 | not affected.\r | |
| 139 | \r | |
| 140 | EfiPciHostBridgeFreeResources Deallocates resources that were\r | |
| 141 | previously allocated for all the PCI\r | |
| 142 | root bridges and resets the I/O and\r | |
| 143 | memory apertures to their initial\r | |
| 144 | state. The bus settings are not\r | |
| 145 | affected. If the request to allocate\r | |
| 146 | resources fails, the PCI enumerator\r | |
| 147 | can use this notification to\r | |
| 148 | deallocate previous resources, adjust\r | |
| 149 | the requests, and retry allocation.\r | |
| 150 | \r | |
| 151 | EfiPciHostBridgeEndResourceAllocation The resource allocation phase is\r | |
| 152 | completed. No specific action is\r | |
| 153 | required here. This notification can\r | |
| 154 | be used to perform any chipsetspecific\r | |
| 155 | programming.\r | |
| 156 | \r | |
| 157 | @param[in] This The instance pointer of\r | |
| 158 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
| 159 | \r | |
| 160 | @param[in] Phase The phase during enumeration\r | |
| 161 | \r | |
| 162 | @retval EFI_NOT_READY This phase cannot be entered at this time. For\r | |
| 163 | example, this error is valid for a Phase of\r | |
| 164 | EfiPciHostBridgeAllocateResources if\r | |
| 165 | SubmitResources() has not been called for one\r | |
| 166 | or more PCI root bridges before this call\r | |
| 167 | \r | |
| 168 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r | |
| 169 | This error is valid for a Phase of\r | |
| 170 | EfiPciHostBridgeSetResources.\r | |
| 171 | \r | |
| 172 | @retval EFI_INVALID_PARAMETER Invalid phase parameter\r | |
| 173 | \r | |
| 174 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
| 175 | lack of resources. This error is valid for a\r | |
| 176 | Phase of EfiPciHostBridgeAllocateResources if\r | |
| 177 | the previously submitted resource requests\r | |
| 178 | cannot be fulfilled or were only partially\r | |
| 179 | fulfilled.\r | |
| 180 | \r | |
| 181 | @retval EFI_SUCCESS The notification was accepted without any\r | |
| 182 | errors.\r | |
| 24115e44 | 183 | **/\r |
| 21b404d1 | 184 | EFI_STATUS\r |
| 185 | EFIAPI\r | |
| 186 | NotifyPhase(\r | |
| 187 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 188 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r | |
| 189 | );\r | |
| 190 | \r | |
| 24115e44 | 191 | /**\r |
| 90ac6ac2 LE |
192 | Return the device handle of the next PCI root bridge that is associated with\r |
| 193 | this Host Bridge.\r | |
| 194 | \r | |
| 195 | This function is called multiple times to retrieve the device handles of all\r | |
| 196 | the PCI root bridges that are associated with this PCI host bridge. Each PCI\r | |
| 197 | host bridge is associated with one or more PCI root bridges. On each call,\r | |
| 198 | the handle that was returned by the previous call is passed into the\r | |
| 199 | interface, and on output the interface returns the device handle of the next\r | |
| 200 | PCI root bridge. The caller can use the handle to obtain the instance of the\r | |
| 201 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL for that root bridge. When there are no more\r | |
| 202 | PCI root bridges to report, the interface returns EFI_NOT_FOUND. A PCI\r | |
| 203 | enumerator must enumerate the PCI root bridges in the order that they are\r | |
| 204 | returned by this function.\r | |
| 205 | \r | |
| 206 | For D945 implementation, there is only one root bridge in PCI host bridge.\r | |
| 207 | \r | |
| 208 | @param[in] This The instance pointer of\r | |
| 209 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
| 210 | \r | |
| 211 | @param[in, out] RootBridgeHandle Returns the device handle of the next PCI\r | |
| 212 | root bridge.\r | |
| 213 | \r | |
| 214 | @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then\r | |
| 215 | return the first Rootbridge handle of the\r | |
| 216 | specific Host bridge and return EFI_SUCCESS.\r | |
| 217 | \r | |
| 218 | @retval EFI_NOT_FOUND Can not find the any more root bridge in\r | |
| 219 | specific host bridge.\r | |
| 220 | \r | |
| 221 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was\r | |
| 222 | returned on a previous call to\r | |
| 223 | GetNextRootBridge().\r | |
| 24115e44 | 224 | **/\r |
| 21b404d1 | 225 | EFI_STATUS\r |
| 226 | EFIAPI\r | |
| 227 | GetNextRootBridge(\r | |
| 228 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 229 | IN OUT EFI_HANDLE *RootBridgeHandle\r | |
| 230 | );\r | |
| 90ac6ac2 | 231 | \r |
| 24115e44 | 232 | /**\r |
| 90ac6ac2 LE |
233 | Returns the allocation attributes of a PCI root bridge.\r |
| 234 | \r | |
| 235 | The function returns the allocation attributes of a specific PCI root bridge.\r | |
| 236 | The attributes can vary from one PCI root bridge to another. These attributes\r | |
| 237 | are different from the decode-related attributes that are returned by the\r | |
| 238 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r | |
| 239 | RootBridgeHandle parameter is used to specify the instance of the PCI root\r | |
| 240 | bridge. The device handles of all the root bridges that are associated with\r | |
| 241 | this host bridge must be obtained by calling GetNextRootBridge(). The\r | |
| 242 | attributes are static in the sense that they do not change during or after\r | |
| 243 | the enumeration process. The hardware may provide mechanisms to change the\r | |
| 244 | attributes on the fly, but such changes must be completed before\r | |
| 245 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is installed. The permitted\r | |
| 246 | values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r | |
| 247 | "Related Definitions" below. The caller uses these attributes to combine\r | |
| 248 | multiple resource requests.\r | |
| 249 | \r | |
| 250 | For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI\r | |
| 251 | bus enumerator needs to include requests for the prefetchable memory in the\r | |
| 252 | nonprefetchable memory pool and not request any prefetchable memory.\r | |
| 253 | \r | |
| 254 | Attribute Description\r | |
| 255 | ------------------------------------ ---------------------------------------\r | |
| 256 | EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root\r | |
| 257 | bridge does not support separate\r | |
| 258 | windows for nonprefetchable and\r | |
| 259 | prefetchable memory. A PCI bus driver\r | |
| 260 | needs to include requests for\r | |
| 261 | prefetchable memory in the\r | |
| 262 | nonprefetchable memory pool.\r | |
| 263 | \r | |
| 264 | EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root\r | |
| 265 | bridge supports 64-bit memory windows.\r | |
| 266 | If this bit is not set, the PCI bus\r | |
| 267 | driver needs to include requests for a\r | |
| 268 | 64-bit memory address in the\r | |
| 269 | corresponding 32-bit memory pool.\r | |
| 270 | \r | |
| 271 | @param[in] This The instance pointer of\r | |
| 272 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
| 273 | \r | |
| 274 | @param[in] RootBridgeHandle The device handle of the PCI root bridge in\r | |
| 275 | which the caller is interested. Type\r | |
| 276 | EFI_HANDLE is defined in\r | |
| 277 | InstallProtocolInterface() in the UEFI 2.0\r | |
| 278 | Specification.\r | |
| 279 | \r | |
| 280 | @param[out] Attributes The pointer to attribte of root bridge, it is\r | |
| 281 | output parameter\r | |
| 282 | \r | |
| 283 | @retval EFI_INVALID_PARAMETER Attribute pointer is NULL\r | |
| 284 | \r | |
| 285 | @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.\r | |
| 286 | \r | |
| 287 | @retval EFI_SUCCESS Success to get attribute of interested root\r | |
| 288 | bridge.\r | |
| 289 | **/\r | |
| 21b404d1 | 290 | EFI_STATUS\r |
| 291 | EFIAPI\r | |
| 292 | GetAttributes(\r | |
| 293 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 294 | IN EFI_HANDLE RootBridgeHandle,\r | |
| 295 | OUT UINT64 *Attributes\r | |
| 296 | );\r | |
| 90ac6ac2 | 297 | \r |
| 24115e44 | 298 | /**\r |
| 90ac6ac2 LE |
299 | Sets up the specified PCI root bridge for the bus enumeration process.\r |
| 300 | \r | |
| 301 | This member function sets up the root bridge for bus enumeration and returns\r | |
| 302 | the PCI bus range over which the search should be performed in ACPI 2.0\r | |
| 303 | resource descriptor format.\r | |
| 304 | \r | |
| 305 | @param[in] This The\r | |
| 306 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
| 307 | instance.\r | |
| 24115e44 | 308 | \r |
| 90ac6ac2 | 309 | @param[in] RootBridgeHandle The PCI Root Bridge to be set up.\r |
| 24115e44 | 310 | \r |
| 90ac6ac2 LE |
311 | @param[out] Configuration Pointer to the pointer to the PCI bus resource\r |
| 312 | descriptor.\r | |
| 24115e44 | 313 | \r |
| 90ac6ac2 LE |
314 | @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r |
| 315 | \r | |
| 316 | @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.\r | |
| 317 | \r | |
| 318 | @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.\r | |
| 24115e44 | 319 | **/\r |
| 21b404d1 | 320 | EFI_STATUS\r |
| 321 | EFIAPI\r | |
| 322 | StartBusEnumeration(\r | |
| 323 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 324 | IN EFI_HANDLE RootBridgeHandle,\r | |
| 325 | OUT VOID **Configuration\r | |
| 326 | );\r | |
| 90ac6ac2 | 327 | \r |
| 24115e44 | 328 | /**\r |
| 90ac6ac2 LE |
329 | Programs the PCI root bridge hardware so that it decodes the specified PCI\r |
| 330 | bus range.\r | |
| 331 | \r | |
| 332 | This member function programs the specified PCI root bridge to decode the bus\r | |
| 333 | range that is specified by the input parameter Configuration.\r | |
| 334 | The bus range information is specified in terms of the ACPI 2.0 resource\r | |
| 335 | descriptor format.\r | |
| 336 | \r | |
| 337 | @param[in] This The\r | |
| 338 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
| 339 | instance\r | |
| 340 | \r | |
| 341 | @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be\r | |
| 342 | programmed\r | |
| 343 | \r | |
| 344 | @param[in] Configuration The pointer to the PCI bus resource descriptor\r | |
| 345 | \r | |
| 346 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r | |
| 347 | handle.\r | |
| 348 | \r | |
| 349 | @retval EFI_INVALID_PARAMETER Configuration is NULL.\r | |
| 350 | \r | |
| 351 | @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI\r | |
| 352 | 2.0 resource descriptor.\r | |
| 353 | \r | |
| 354 | @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI\r | |
| 355 | 2.0 bus resource descriptor.\r | |
| 24115e44 | 356 | \r |
| 90ac6ac2 LE |
357 | @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource\r |
| 358 | descriptors other than bus descriptors.\r | |
| 359 | \r | |
| 360 | @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid\r | |
| 361 | ACPI resource descriptors.\r | |
| 362 | \r | |
| 363 | @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this\r | |
| 364 | root bridge.\r | |
| 365 | \r | |
| 366 | @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this\r | |
| 367 | root bridge.\r | |
| 368 | \r | |
| 369 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r | |
| 370 | \r | |
| 371 | @retval EFI_SUCCESS The bus range for the PCI root bridge was\r | |
| 372 | programmed.\r | |
| 24115e44 | 373 | **/\r |
| 21b404d1 | 374 | EFI_STATUS\r |
| 375 | EFIAPI\r | |
| 376 | SetBusNumbers(\r | |
| 377 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 378 | IN EFI_HANDLE RootBridgeHandle,\r | |
| 379 | IN VOID *Configuration\r | |
| 380 | );\r | |
| 90ac6ac2 | 381 | \r |
| 24115e44 | 382 | /**\r |
| 90ac6ac2 LE |
383 | Submits the I/O and memory resource requirements for the specified PCI root\r |
| 384 | bridge.\r | |
| 24115e44 | 385 | \r |
| 90ac6ac2 LE |
386 | This function is used to submit all the I/O and memory resources that are\r |
| 387 | required by the specified PCI root bridge. The input parameter Configuration\r | |
| 388 | is used to specify the following:\r | |
| 389 | - The various types of resources that are required\r | |
| 390 | - The associated lengths in terms of ACPI 2.0 resource descriptor format\r | |
| 391 | \r | |
| 392 | @param[in] This Pointer to the\r | |
| 393 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
| 394 | instance.\r | |
| 395 | \r | |
| 396 | @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory\r | |
| 397 | resource requirements are being submitted.\r | |
| 398 | \r | |
| 399 | @param[in] Configuration The pointer to the PCI I/O and PCI memory\r | |
| 400 | resource descriptor.\r | |
| 401 | \r | |
| 402 | @retval EFI_SUCCESS The I/O and memory resource requests for a PCI\r | |
| 403 | root bridge were accepted.\r | |
| 404 | \r | |
| 405 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r | |
| 406 | handle.\r | |
| 24115e44 | 407 | \r |
| 90ac6ac2 | 408 | @retval EFI_INVALID_PARAMETER Configuration is NULL.\r |
| 24115e44 | 409 | \r |
| 90ac6ac2 LE |
410 | @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI\r |
| 411 | 2.0 resource descriptor.\r | |
| 412 | \r | |
| 413 | @retval EFI_INVALID_PARAMETER Configuration includes requests for one or\r | |
| 414 | more resource types that are not supported by\r | |
| 415 | this PCI root bridge. This error will happen\r | |
| 416 | if the caller did not combine resources\r | |
| 417 | according to Attributes that were returned by\r | |
| 418 | GetAllocAttributes().\r | |
| 419 | \r | |
| 420 | @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.\r | |
| 421 | \r | |
| 422 | @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI\r | |
| 423 | root bridge.\r | |
| 424 | \r | |
| 425 | @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for\r | |
| 426 | this PCI root bridge.\r | |
| 24115e44 | 427 | **/\r |
| 21b404d1 | 428 | EFI_STATUS\r |
| 429 | EFIAPI\r | |
| 430 | SubmitResources(\r | |
| 431 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 432 | IN EFI_HANDLE RootBridgeHandle,\r | |
| 433 | IN VOID *Configuration\r | |
| 434 | );\r | |
| 90ac6ac2 | 435 | \r |
| 24115e44 ED |
436 | /**\r |
| 437 | Returns the proposed resource settings for the specified PCI root bridge.\r | |
| 438 | \r | |
| 90ac6ac2 LE |
439 | This member function returns the proposed resource settings for the\r |
| 440 | specified PCI root bridge. The proposed resource settings are prepared when\r | |
| 441 | NotifyPhase() is called with a Phase of EfiPciHostBridgeAllocateResources.\r | |
| 442 | The output parameter Configuration specifies the following:\r | |
| 443 | - The various types of resources, excluding bus resources, that are\r | |
| 444 | allocated\r | |
| 24115e44 ED |
445 | - The associated lengths in terms of ACPI 2.0 resource descriptor format\r |
| 446 | \r | |
| 90ac6ac2 LE |
447 | @param[in] This Pointer to the\r |
| 448 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
| 449 | instance.\r | |
| 450 | \r | |
| 451 | @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is\r | |
| 452 | defined in InstallProtocolInterface() in the\r | |
| 453 | UEFI 2.0 Specification.\r | |
| 454 | \r | |
| 455 | @param[out] Configuration The pointer to the pointer to the PCI I/O and\r | |
| 456 | memory resource descriptor.\r | |
| 457 | \r | |
| 24115e44 | 458 | @retval EFI_SUCCESS The requested parameters were returned.\r |
| 90ac6ac2 LE |
459 | \r |
| 460 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r | |
| 461 | handle.\r | |
| 462 | \r | |
| 24115e44 | 463 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r |
| 24115e44 | 464 | \r |
| 90ac6ac2 LE |
465 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r |
| 466 | lack of resources.\r | |
| 24115e44 | 467 | **/\r |
| 21b404d1 | 468 | EFI_STATUS\r |
| 469 | EFIAPI\r | |
| 470 | GetProposedResources(\r | |
| 471 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 472 | IN EFI_HANDLE RootBridgeHandle,\r | |
| 473 | OUT VOID **Configuration\r | |
| 474 | );\r | |
| 475 | \r | |
| 24115e44 | 476 | /**\r |
| 90ac6ac2 LE |
477 | Provides the hooks from the PCI bus driver to every PCI controller\r |
| 478 | (device/function) at various stages of the PCI enumeration process that allow\r | |
| 479 | the host bridge driver to preinitialize individual PCI controllers before\r | |
| 480 | enumeration.\r | |
| 481 | \r | |
| 482 | This function is called during the PCI enumeration process. No specific\r | |
| 483 | action is expected from this member function. It allows the host bridge\r | |
| 484 | driver to preinitialize individual PCI controllers before enumeration.\r | |
| 485 | \r | |
| 486 | @param This Pointer to the\r | |
| 487 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
| 488 | instance.\r | |
| 489 | \r | |
| 490 | @param RootBridgeHandle The associated PCI root bridge handle. Type\r | |
| 491 | EFI_HANDLE is defined in InstallProtocolInterface()\r | |
| 492 | in the UEFI 2.0 Specification.\r | |
| 493 | \r | |
| 494 | @param PciAddress The address of the PCI device on the PCI bus. This\r | |
| 495 | address can be passed to the\r | |
| 496 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to\r | |
| 497 | access the PCI configuration space of the device.\r | |
| 498 | See Table 12-1 in the UEFI 2.0 Specification for the\r | |
| 499 | definition of\r | |
| 500 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r | |
| 501 | \r | |
| 502 | @param Phase The phase of the PCI device enumeration.\r | |
| 503 | \r | |
| 504 | @retval EFI_SUCCESS The requested parameters were returned.\r | |
| 505 | \r | |
| 506 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r | |
| 507 | handle.\r | |
| 508 | \r | |
| 509 | @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined\r | |
| 510 | in\r | |
| 511 | EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r | |
| 512 | \r | |
| 513 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r | |
| 514 | The PCI enumerator should not enumerate this\r | |
| 515 | device, including its child devices if it is\r | |
| 516 | a PCI-to-PCI bridge.\r | |
| 24115e44 | 517 | **/\r |
| 21b404d1 | 518 | EFI_STATUS\r |
| 519 | EFIAPI\r | |
| 520 | PreprocessController (\r | |
| 521 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 522 | IN EFI_HANDLE RootBridgeHandle,\r | |
| 523 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r | |
| 524 | IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r | |
| 525 | );\r | |
| 526 | \r | |
| 527 | \r | |
| 528 | //\r | |
| 90ac6ac2 | 529 | // Define resource status constant\r |
| 21b404d1 | 530 | //\r |
| 531 | #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r | |
| 532 | #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r | |
| 533 | \r | |
| 534 | \r | |
| 535 | //\r | |
| 536 | // Driver Instance Data Prototypes\r | |
| 537 | //\r | |
| 538 | \r | |
| 539 | typedef struct {\r | |
| 540 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;\r | |
| 541 | UINTN NumberOfBytes;\r | |
| 542 | UINTN NumberOfPages;\r | |
| 543 | EFI_PHYSICAL_ADDRESS HostAddress;\r | |
| 544 | EFI_PHYSICAL_ADDRESS MappedHostAddress;\r | |
| 545 | } MAP_INFO;\r | |
| 546 | \r | |
| 547 | typedef struct {\r | |
| 548 | ACPI_HID_DEVICE_PATH AcpiDevicePath;\r | |
| 549 | EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r | |
| 550 | } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r | |
| 551 | \r | |
| 552 | typedef struct {\r | |
| 553 | UINT64 BusBase;\r | |
| 947b1f3c LE |
554 | UINT64 BusLimit;\r |
| 555 | \r | |
| 556 | UINT64 MemBase;\r | |
| 557 | UINT64 MemLimit;\r | |
| 558 | \r | |
| 559 | UINT64 IoBase;\r | |
| 560 | UINT64 IoLimit;\r | |
| 0b7c6cd4 | 561 | } PCI_ROOT_BRIDGE_RESOURCE_APERTURE;\r |
| 21b404d1 | 562 | \r |
| 563 | typedef enum {\r | |
| 564 | TypeIo = 0,\r | |
| 565 | TypeMem32,\r | |
| 566 | TypePMem32,\r | |
| 567 | TypeMem64,\r | |
| 568 | TypePMem64,\r | |
| 569 | TypeBus,\r | |
| 570 | TypeMax\r | |
| 571 | } PCI_RESOURCE_TYPE;\r | |
| 572 | \r | |
| 573 | typedef enum {\r | |
| 574 | ResNone = 0,\r | |
| 575 | ResSubmitted,\r | |
| 576 | ResRequested,\r | |
| 577 | ResAllocated,\r | |
| 578 | ResStatusMax\r | |
| 579 | } RES_STATUS;\r | |
| 580 | \r | |
| 581 | typedef struct {\r | |
| 582 | PCI_RESOURCE_TYPE Type;\r | |
| 583 | UINT64 Base;\r | |
| 584 | UINT64 Length;\r | |
| 585 | UINT64 Alignment;\r | |
| 586 | RES_STATUS Status;\r | |
| 587 | } PCI_RES_NODE;\r | |
| 588 | \r | |
| 589 | #define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b')\r | |
| 590 | \r | |
| 591 | typedef struct {\r | |
| 592 | UINT32 Signature;\r | |
| 593 | LIST_ENTRY Link;\r | |
| 594 | EFI_HANDLE Handle;\r | |
| 595 | UINT64 RootBridgeAttrib;\r | |
| 596 | UINT64 Attributes;\r | |
| 597 | UINT64 Supports;\r | |
| 947b1f3c | 598 | \r |
| 21b404d1 | 599 | //\r |
| 600 | // Specific for this memory controller: Bus, I/O, Mem\r | |
| 601 | //\r | |
| 602 | PCI_RES_NODE ResAllocNode[6];\r | |
| 947b1f3c | 603 | \r |
| 21b404d1 | 604 | //\r |
| 605 | // Addressing for Memory and I/O and Bus arrange\r | |
| 606 | //\r | |
| 607 | UINT64 BusBase;\r | |
| 947b1f3c LE |
608 | UINT64 MemBase;\r |
| 609 | UINT64 IoBase;\r | |
| 610 | UINT64 BusLimit;\r | |
| 611 | UINT64 MemLimit;\r | |
| 612 | UINT64 IoLimit;\r | |
| 21b404d1 | 613 | \r |
| 21b404d1 | 614 | EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r |
| 615 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r | |
| 616 | \r | |
| 617 | } PCI_ROOT_BRIDGE_INSTANCE;\r | |
| 618 | \r | |
| 619 | \r | |
| 620 | //\r | |
| 621 | // Driver Instance Data Macros\r | |
| 622 | //\r | |
| 623 | #define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \\r | |
| 624 | CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)\r | |
| 625 | \r | |
| 626 | \r | |
| 627 | #define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \\r | |
| 628 | CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)\r | |
| 629 | \r | |
| 24115e44 ED |
630 | /**\r |
| 631 | \r | |
| 632 | Construct the Pci Root Bridge Io protocol\r | |
| 633 | \r | |
| 634 | @param Protocol Point to protocol instance\r | |
| 635 | @param HostBridgeHandle Handle of host bridge\r | |
| 636 | @param Attri Attribute of host bridge\r | |
| 0b7c6cd4 | 637 | @param ResAperture ResourceAperture for host bridge\r |
| 24115e44 ED |
638 | \r |
| 639 | @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r | |
| 24115e44 | 640 | **/\r |
| 21b404d1 | 641 | EFI_STATUS\r |
| 642 | RootBridgeConstructor (\r | |
| 643 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r | |
| 644 | IN EFI_HANDLE HostBridgeHandle,\r | |
| 645 | IN UINT64 Attri,\r | |
| 0b7c6cd4 | 646 | IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture\r |
| 21b404d1 | 647 | );\r |
| 648 | \r | |
| 649 | #endif\r |