[mirror_edk2.git] / PerformancePkg / Library / PeiTscTimerLib / PeiTscTimerLib.c

/** @file\r
  A Pei Timer Library implementation which uses the Time Stamp Counter in the processor.\r
\r
  For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]);\r
    for Intel Core Solo and Intel Core Duo processors (family [06H], model [0EH]);\r
    for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family [06H], model [0FH]);\r
    for Intel Core 2 and Intel Xeon processors (family [06H], display_model [17H]);\r
    for Intel Atom processors (family [06H], display_model [1CH]):\r
  the time-stamp counter increments at a constant rate.\r
  That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by\r
  the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may\r
  differ from the maximum qualified frequency of the processor.\r
\r
  The specific processor configuration determines the behavior. Constant TSC behavior ensures that the\r
  duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if\r
  the processor core changes frequency. This is the architectural behavior moving forward.\r
\r
  A Processor's support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].\r
\r
  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution. The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <PiPei.h>\r
#include <Ich/GenericIch.h>\r
\r
#include <Library/TimerLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/HobLib.h>\r
\r
#include <Guid/TscFrequency.h>\r
\r
/**  Get TSC frequency from TSC frequency GUID HOB, if the HOB is not found, build it.\r
\r
  The TSC counting frequency is determined by comparing how far it counts\r
  during a 1ms period as determined by the ACPI timer. The ACPI timer is\r
  used because it counts at a known frequency.\r
  If ACPI I/O space not enabled, this function will enable it. Then the\r
  TSC is sampled, followed by waiting for 3579 clocks of the ACPI timer, or 1ms.\r
  The TSC is then sampled again. The difference multiplied by 1000 is the TSC\r
  frequency. There will be a small error because of the overhead of reading\r
  the ACPI timer.\r
\r
  @return The number of TSC counts per second.\r
\r
**/\r
UINT64\r
InternalGetTscFrequency (\r
  VOID\r
  )\r
{\r
  EFI_HOB_GUID_TYPE       *GuidHob;\r
  VOID        *DataInHob;\r
  UINT64      StartTSC;\r
  UINT64      EndTSC;\r
  UINT32      TimerAddr;\r
  UINT32      Ticks;\r
  UINT64      TscFrequency;\r
\r
  //\r
  // Get TSC frequency from TSC frequency GUID HOB.\r
  //\r
  GuidHob = GetFirstGuidHob (&gEfiTscFrequencyGuid);\r
  if (GuidHob != NULL) {\r
    DataInHob = GET_GUID_HOB_DATA (GuidHob);\r
    TscFrequency = * (UINT64 *) DataInHob;\r
    return TscFrequency;\r
  }\r
\r
  //\r
  // TSC frequency GUID HOB is not found, build it.\r
  //\r
\r
  //\r
  // If ACPI I/O space is not enabled yet, program ACPI I/O base address and enable it.\r
  //\r
  if ((PciRead8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT)) & B_ICH_LPC_ACPI_CNT_ACPI_EN) == 0) {\r
    PciWrite16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE), PcdGet16 (PcdPerfPkgAcpiIoPortBaseAddress));\r
    PciOr8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT), B_ICH_LPC_ACPI_CNT_ACPI_EN);\r
  }\r
\r
  //\r
  // ACPI I/O space should be enabled now, locate the ACPI Timer.\r
  // ACPI I/O base address maybe have be initialized by other driver with different value,\r
  // So get it from PCI space directly.\r
  //\r
  TimerAddr = ((PciRead16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE))) & B_ICH_LPC_ACPI_BASE_BAR) + R_ACPI_PM1_TMR;\r
  Ticks    = IoRead32 (TimerAddr) + (3579);   // Set Ticks to 1ms in the future\r
  StartTSC = AsmReadTsc();                    // Get base value for the TSC\r
  //\r
  // Wait until the ACPI timer has counted 1ms.\r
  // Timer wrap-arounds are handled correctly by this function.\r
  // When the current ACPI timer value is greater than 'Ticks', the while loop will exit.\r
  //\r
  while (((Ticks - IoRead32 (TimerAddr)) & BIT23) == 0) {\r
    CpuPause();\r
  }\r
  EndTSC = AsmReadTsc();    // TSC value 1ms later\r
\r
  TscFrequency =   MultU64x32 (\r
                      (EndTSC - StartTSC),    // Number of TSC counts in 1ms\r
                      1000                    // Number of ms in a second\r
                    );\r
  //\r
  // TscFrequency is now equal to the number of TSC counts per second, build GUID HOB for it.\r
  //\r
  BuildGuidDataHob (\r
    &gEfiTscFrequencyGuid,\r
    &TscFrequency,\r
    sizeof (UINT64)\r
    );\r
\r
  return TscFrequency;\r
}\r
\r
/**  Stalls the CPU for at least the given number of ticks.\r
\r
  Stalls the CPU for at least the given number of ticks. It's invoked by\r
  MicroSecondDelay() and NanoSecondDelay().\r
\r
  @param[in]  Delay     A period of time to delay in ticks.\r
\r
**/\r
VOID\r
InternalX86Delay (\r
  IN      UINT64                    Delay\r
  )\r
{\r
  UINT64                             Ticks;\r
\r
  //\r
  // The target timer count is calculated here\r
  //\r
  Ticks = AsmReadTsc() + Delay;\r
\r
  //\r
  // Wait until time out\r
  // Timer wrap-arounds are NOT handled correctly by this function.\r
  // Thus, this function must be called within 10 years of reset since\r
  // Intel guarantees a minimum of 10 years before the TSC wraps.\r
  //\r
  while (AsmReadTsc() <= Ticks) CpuPause();\r
}\r
\r
/**  Stalls the CPU for at least the specified number of MicroSeconds.\r
\r
  @param[in]  MicroSeconds  The minimum number of microseconds to delay.\r
\r
  @return The value of MicroSeconds input.\r
\r
**/\r
UINTN\r
EFIAPI\r
MicroSecondDelay (\r
  IN      UINTN                     MicroSeconds\r
  )\r
{\r
  InternalX86Delay (\r
    DivU64x32 (\r
      MultU64x64 (\r
        InternalGetTscFrequency (),\r
        MicroSeconds\r
      ),\r
      1000000u\r
    )\r
  );\r
  return MicroSeconds;\r
}\r
\r
/**  Stalls the CPU for at least the specified number of NanoSeconds.\r
\r
  @param[in]  NanoSeconds The minimum number of nanoseconds to delay.\r
\r
  @return The value of NanoSeconds input.\r
\r
**/\r
UINTN\r
EFIAPI\r
NanoSecondDelay (\r
  IN      UINTN                     NanoSeconds\r
  )\r
{\r
  InternalX86Delay (\r
    DivU64x32 (\r
      MultU64x32 (\r
        InternalGetTscFrequency (),\r
        (UINT32)NanoSeconds\r
      ),\r
    1000000000u\r
    )\r
  );\r
  return NanoSeconds;\r
}\r
\r
/**  Retrieves the current value of the 64-bit free running Time-Stamp counter.\r
\r
  The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,\r
  Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors and\r
  later processors) is a 64-bit counter that is set to 0 following a RESET of\r
  the processor.  Following a RESET, the counter increments even when the\r
  processor is halted by the HLT instruction or the external STPCLK# pin. Note\r
  that the assertion of the external DPSLP# pin may cause the time-stamp\r
  counter to stop.\r
\r
  The properties of the counter can be retrieved by the\r
  GetPerformanceCounterProperties() function.\r
\r
  @return The current value of the free running performance counter.\r
\r
**/\r
UINT64\r
EFIAPI\r
GetPerformanceCounter (\r
  VOID\r
  )\r
{\r
  return AsmReadTsc();\r
}\r
\r
/**  Retrieves the 64-bit frequency in Hz and the range of performance counter\r
  values.\r
\r
  If StartValue is not NULL, then the value that the performance counter starts\r
  with, 0x0, is returned in StartValue. If EndValue is not NULL, then the value\r
  that the performance counter end with, 0xFFFFFFFFFFFFFFFF, is returned in\r
  EndValue.\r
\r
  The 64-bit frequency of the performance counter, in Hz, is always returned.\r
  To determine average processor clock frequency, Intel recommends the use of\r
  EMON logic to count processor core clocks over the period of time for which\r
  the average is required.\r
\r
\r
  @param[out]   StartValue  Pointer to where the performance counter's starting value is saved, or NULL.\r
  @param[out]   EndValue    Pointer to where the performance counter's ending value is saved, or NULL.\r
\r
  @return The frequency in Hz.\r
\r
**/\r
UINT64\r
EFIAPI\r
GetPerformanceCounterProperties (\r
  OUT      UINT64                    *StartValue,  OPTIONAL\r
  OUT      UINT64                    *EndValue     OPTIONAL\r
  )\r
{\r
  if (StartValue != NULL) {\r
    *StartValue = 0;\r
  }\r
  if (EndValue != NULL) {\r
    *EndValue = 0xFFFFFFFFFFFFFFFFull;\r
  }\r
\r
  return InternalGetTscFrequency ();\r
}\r
\r
/**\r
  Converts elapsed ticks of performance counter to time in nanoseconds.\r
\r
  This function converts the elapsed ticks of running performance counter to\r
  time value in unit of nanoseconds.\r
\r
  @param  Ticks     The number of elapsed ticks of running performance counter.\r
\r
  @return The elapsed time in nanoseconds.\r
\r
**/\r
UINT64\r
EFIAPI\r
GetTimeInNanoSecond (\r
  IN      UINT64                     Ticks\r
  )\r
{\r
  UINT64  Frequency;\r
  UINT64  NanoSeconds;\r
  UINT64  Remainder;\r
  INTN    Shift;\r
\r
  Frequency = GetPerformanceCounterProperties (NULL, NULL);\r
\r
  //\r
  //          Ticks\r
  // Time = --------- x 1,000,000,000\r
  //        Frequency\r
  //\r
  NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);\r
\r
  //\r
  // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.\r
  // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,\r
  // i.e. highest bit set in Remainder should <= 33.\r
  //\r
  Shift = MAX (0, HighBitSet64 (Remainder) - 33);\r
  Remainder = RShiftU64 (Remainder, (UINTN) Shift);\r
  Frequency = RShiftU64 (Frequency, (UINTN) Shift);\r
  NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);\r
\r
  return NanoSeconds;\r
}\r
Commit	Line	Data
c06ad33e	1	/** @file\r
d50f6f8b	2	A Pei Timer Library implementation which uses the Time Stamp Counter in the processor.\r
c06ad33e	3	\r
	4	For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]);\r
	5	for Intel Core Solo and Intel Core Duo processors (family [06H], model [0EH]);\r
	6	for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family [06H], model [0FH]);\r
	7	for Intel Core 2 and Intel Xeon processors (family [06H], display_model [17H]);\r
	8	for Intel Atom processors (family [06H], display_model [1CH]):\r
	9	the time-stamp counter increments at a constant rate.\r
	10	That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by\r
	11	the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may\r
	12	differ from the maximum qualified frequency of the processor.\r
	13	\r
	14	The specific processor configuration determines the behavior. Constant TSC behavior ensures that the\r
	15	duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if\r
d50f6f8b	16	the processor core changes frequency. This is the architectural behavior moving forward.\r
c06ad33e	17	\r
24cd83a7	18	A Processor's support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].\r
c06ad33e	19	\r
d50f6f8b	20	Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>\r
c06ad33e	21	This program and the accompanying materials\r
c06ad33e	22	are licensed and made available under the terms and conditions of the BSD License\r
d50f6f8b	23	which accompanies this distribution. The full text of the license may be found at\r
c06ad33e	24	http://opensource.org/licenses/bsd-license.php\r
	25	\r
	26	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	27	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	28	\r
	29	**/\r
	30	\r
d50f6f8b	31	#include <PiPei.h>\r
c06ad33e	32	#include <Ich/GenericIch.h>\r
	33	\r
	34	#include <Library/TimerLib.h>\r
	35	#include <Library/BaseLib.h>\r
	36	#include <Library/IoLib.h>\r
	37	#include <Library/PciLib.h>\r
	38	#include <Library/PcdLib.h>\r
d50f6f8b	39	#include <Library/HobLib.h>\r
c06ad33e	40	\r
d50f6f8b	41	#include <Guid/TscFrequency.h>\r
c06ad33e	42	\r
d50f6f8b	43	/** Get TSC frequency from TSC frequency GUID HOB, if the HOB is not found, build it.\r
c06ad33e	44	\r
c06ad33e	45	The TSC counting frequency is determined by comparing how far it counts\r
d50f6f8b	46	during a 1ms period as determined by the ACPI timer. The ACPI timer is\r
c06ad33e	47	used because it counts at a known frequency.\r
d50f6f8b	48	If ACPI I/O space not enabled, this function will enable it. Then the\r
c06ad33e	49	TSC is sampled, followed by waiting for 3579 clocks of the ACPI timer, or 1ms.\r
c06ad33e	50	The TSC is then sampled again. The difference multiplied by 1000 is the TSC\r
d50f6f8b SZ	51	frequency. There will be a small error because of the overhead of reading\r
d50f6f8b SZ	52	the ACPI timer.\r
c06ad33e	53	\r
d50f6f8b	54	@return The number of TSC counts per second.\r
c06ad33e	55	\r
c06ad33e	56	**/\r
d50f6f8b SZ	57	UINT64\r
d50f6f8b SZ	58	InternalGetTscFrequency (\r
c06ad33e	59	VOID\r
	60	)\r
	61	{\r
d50f6f8b SZ	62	EFI_HOB_GUID_TYPE *GuidHob;\r
d50f6f8b SZ	63	VOID *DataInHob;\r
c06ad33e	64	UINT64 StartTSC;\r
	65	UINT64 EndTSC;\r
	66	UINT32 TimerAddr;\r
	67	UINT32 Ticks;\r
d50f6f8b SZ	68	UINT64 TscFrequency;\r
	69	\r
	70	//\r
	71	// Get TSC frequency from TSC frequency GUID HOB.\r
	72	//\r
	73	GuidHob = GetFirstGuidHob (&gEfiTscFrequencyGuid);\r
	74	if (GuidHob != NULL) {\r
	75	DataInHob = GET_GUID_HOB_DATA (GuidHob);\r
	76	TscFrequency = * (UINT64 *) DataInHob;\r
	77	return TscFrequency;\r
	78	}\r
	79	\r
	80	//\r
	81	// TSC frequency GUID HOB is not found, build it.\r
	82	//\r
c06ad33e	83	\r
	84	//\r
	85	// If ACPI I/O space is not enabled yet, program ACPI I/O base address and enable it.\r
	86	//\r
	87	if ((PciRead8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT)) & B_ICH_LPC_ACPI_CNT_ACPI_EN) == 0) {\r
	88	PciWrite16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE), PcdGet16 (PcdPerfPkgAcpiIoPortBaseAddress));\r
	89	PciOr8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT), B_ICH_LPC_ACPI_CNT_ACPI_EN);\r
	90	}\r
	91	\r
d50f6f8b SZ	92	//\r
	93	// ACPI I/O space should be enabled now, locate the ACPI Timer.\r
	94	// ACPI I/O base address maybe have be initialized by other driver with different value,\r
	95	// So get it from PCI space directly.\r
	96	//\r
	97	TimerAddr = ((PciRead16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE))) & B_ICH_LPC_ACPI_BASE_BAR) + R_ACPI_PM1_TMR;\r
	98	Ticks = IoRead32 (TimerAddr) + (3579); // Set Ticks to 1ms in the future\r
c06ad33e	99	StartTSC = AsmReadTsc(); // Get base value for the TSC\r
	100	//\r
	101	// Wait until the ACPI timer has counted 1ms.\r
	102	// Timer wrap-arounds are handled correctly by this function.\r
	103	// When the current ACPI timer value is greater than 'Ticks', the while loop will exit.\r
	104	//\r
d50f6f8b	105	while (((Ticks - IoRead32 (TimerAddr)) & BIT23) == 0) {\r
c06ad33e	106	CpuPause();\r
	107	}\r
	108	EndTSC = AsmReadTsc(); // TSC value 1ms later\r
	109	\r
d50f6f8b	110	TscFrequency = MultU64x32 (\r
c06ad33e	111	(EndTSC - StartTSC), // Number of TSC counts in 1ms\r
	112	1000 // Number of ms in a second\r
	113	);\r
	114	//\r
d50f6f8b	115	// TscFrequency is now equal to the number of TSC counts per second, build GUID HOB for it.\r
c06ad33e	116	//\r
d50f6f8b SZ	117	BuildGuidDataHob (\r
	118	&gEfiTscFrequencyGuid,\r
	119	&TscFrequency,\r
	120	sizeof (UINT64)\r
	121	);\r
	122	\r
	123	return TscFrequency;\r
c06ad33e	124	}\r
	125	\r
	126	/** Stalls the CPU for at least the given number of ticks.\r
	127	\r
	128	Stalls the CPU for at least the given number of ticks. It's invoked by\r
	129	MicroSecondDelay() and NanoSecondDelay().\r
	130	\r
	131	@param[in] Delay A period of time to delay in ticks.\r
	132	\r
	133	**/\r
c06ad33e	134	VOID\r
	135	InternalX86Delay (\r
	136	IN UINT64 Delay\r
	137	)\r
	138	{\r
	139	UINT64 Ticks;\r
	140	\r
	141	//\r
	142	// The target timer count is calculated here\r
	143	//\r
	144	Ticks = AsmReadTsc() + Delay;\r
	145	\r
	146	//\r
	147	// Wait until time out\r
	148	// Timer wrap-arounds are NOT handled correctly by this function.\r
	149	// Thus, this function must be called within 10 years of reset since\r
	150	// Intel guarantees a minimum of 10 years before the TSC wraps.\r
	151	//\r
	152	while (AsmReadTsc() <= Ticks) CpuPause();\r
	153	}\r
	154	\r
	155	/** Stalls the CPU for at least the specified number of MicroSeconds.\r
	156	\r
	157	@param[in] MicroSeconds The minimum number of microseconds to delay.\r
	158	\r
	159	@return The value of MicroSeconds input.\r
	160	\r
	161	**/\r
	162	UINTN\r
	163	EFIAPI\r
	164	MicroSecondDelay (\r
	165	IN UINTN MicroSeconds\r
	166	)\r
	167	{\r
	168	InternalX86Delay (\r
	169	DivU64x32 (\r
	170	MultU64x64 (\r
d50f6f8b	171	InternalGetTscFrequency (),\r
c06ad33e	172	MicroSeconds\r
	173	),\r
	174	1000000u\r
	175	)\r
	176	);\r
	177	return MicroSeconds;\r
	178	}\r
	179	\r
	180	/** Stalls the CPU for at least the specified number of NanoSeconds.\r
	181	\r
	182	@param[in] NanoSeconds The minimum number of nanoseconds to delay.\r
	183	\r
	184	@return The value of NanoSeconds input.\r
	185	\r
	186	**/\r
	187	UINTN\r
	188	EFIAPI\r
	189	NanoSecondDelay (\r
	190	IN UINTN NanoSeconds\r
	191	)\r
	192	{\r
	193	InternalX86Delay (\r
	194	DivU64x32 (\r
	195	MultU64x32 (\r
d50f6f8b	196	InternalGetTscFrequency (),\r
c06ad33e	197	(UINT32)NanoSeconds\r
	198	),\r
	199	1000000000u\r
	200	)\r
	201	);\r
	202	return NanoSeconds;\r
	203	}\r
	204	\r
	205	/** Retrieves the current value of the 64-bit free running Time-Stamp counter.\r
	206	\r
	207	The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,\r
	208	Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors and\r
	209	later processors) is a 64-bit counter that is set to 0 following a RESET of\r
	210	the processor. Following a RESET, the counter increments even when the\r
	211	processor is halted by the HLT instruction or the external STPCLK# pin. Note\r
	212	that the assertion of the external DPSLP# pin may cause the time-stamp\r
	213	counter to stop.\r
	214	\r
	215	The properties of the counter can be retrieved by the\r
	216	GetPerformanceCounterProperties() function.\r
	217	\r
	218	@return The current value of the free running performance counter.\r
	219	\r
	220	**/\r
	221	UINT64\r
	222	EFIAPI\r
	223	GetPerformanceCounter (\r
	224	VOID\r
	225	)\r
	226	{\r
	227	return AsmReadTsc();\r
	228	}\r
	229	\r
	230	/** Retrieves the 64-bit frequency in Hz and the range of performance counter\r
	231	values.\r
	232	\r
	233	If StartValue is not NULL, then the value that the performance counter starts\r
	234	with, 0x0, is returned in StartValue. If EndValue is not NULL, then the value\r
	235	that the performance counter end with, 0xFFFFFFFFFFFFFFFF, is returned in\r
	236	EndValue.\r
	237	\r
	238	The 64-bit frequency of the performance counter, in Hz, is always returned.\r
	239	To determine average processor clock frequency, Intel recommends the use of\r
	240	EMON logic to count processor core clocks over the period of time for which\r
	241	the average is required.\r
	242	\r
	243	\r
	244	@param[out] StartValue Pointer to where the performance counter's starting value is saved, or NULL.\r
	245	@param[out] EndValue Pointer to where the performance counter's ending value is saved, or NULL.\r
	246	\r
	247	@return The frequency in Hz.\r
	248	\r
	249	**/\r
	250	UINT64\r
	251	EFIAPI\r
	252	GetPerformanceCounterProperties (\r
	253	OUT UINT64 *StartValue, OPTIONAL\r
	254	OUT UINT64 *EndValue OPTIONAL\r
	255	)\r
	256	{\r
	257	if (StartValue != NULL) {\r
	258	*StartValue = 0;\r
	259	}\r
	260	if (EndValue != NULL) {\r
261	*EndValue = 0xFFFFFFFFFFFFFFFFull;\r
262	}\r
263	\r
d50f6f8b	264	return InternalGetTscFrequency ();\r
c06ad33e	265	}\r
b9610b9c	266	\r
	267	/**\r
	268	Converts elapsed ticks of performance counter to time in nanoseconds.\r
	269	\r
	270	This function converts the elapsed ticks of running performance counter to\r
	271	time value in unit of nanoseconds.\r
	272	\r
	273	@param Ticks The number of elapsed ticks of running performance counter.\r
	274	\r
	275	@return The elapsed time in nanoseconds.\r
	276	\r
	277	**/\r
	278	UINT64\r
	279	EFIAPI\r
	280	GetTimeInNanoSecond (\r
	281	IN UINT64 Ticks\r
	282	)\r
	283	{\r
	284	UINT64 Frequency;\r
	285	UINT64 NanoSeconds;\r
	286	UINT64 Remainder;\r
	287	INTN Shift;\r
	288	\r
	289	Frequency = GetPerformanceCounterProperties (NULL, NULL);\r
	290	\r
	291	//\r
	292	// Ticks\r
	293	// Time = --------- x 1,000,000,000\r
	294	// Frequency\r
	295	//\r
	296	NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);\r
	297	\r
	298	//\r
	299	// Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.\r
	300	// Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,\r
	301	// i.e. highest bit set in Remainder should <= 33.\r
	302	//\r
	303	Shift = MAX (0, HighBitSet64 (Remainder) - 33);\r
	304	Remainder = RShiftU64 (Remainder, (UINTN) Shift);\r
	305	Frequency = RShiftU64 (Frequency, (UINTN) Shift);\r
	306	NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);\r
	307	\r
	308	return NanoSeconds;\r
	309	}\r