projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| b303605e MK |
1 | /** @file\r |
| 2 | CPU T-state control methods\r | |
| 3 | \r | |
| 4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
| 5 | \r | |
| 0eb3de2e | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| b303605e MK |
7 | \r |
| 8 | **/\r | |
| 9 | \r | |
| 10 | DefinitionBlock (\r | |
| 11 | "CPU0TST.aml",\r | |
| 12 | "SSDT",\r | |
| 13 | 0x01,\r | |
| 14 | "SsgPmm",\r | |
| 15 | "Cpu0Tst",\r | |
| 16 | 0x0013\r | |
| 17 | )\r | |
| 18 | {\r | |
| 19 | External (PDC0, IntObj)\r | |
| 20 | External (CFGD, FieldUnitObj)\r | |
| 21 | External(\_PR.CPU0, DeviceObj)\r | |
| 22 | External(_PSS)\r | |
| 23 | \r | |
| 24 | Scope(\_PR.CPU0)\r | |
| 25 | {\r | |
| 26 | Method(_TPC,0)\r | |
| 27 | {\r | |
| 28 | Return(ZERO) // Return All States Available.\r | |
| 29 | }\r | |
| 30 | \r | |
| 31 | Name(TPTC, ResourceTemplate()\r | |
| 32 | {\r | |
| 33 | Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC\r | |
| 34 | })\r | |
| 35 | \r | |
| 36 | //\r | |
| 37 | // If OSPM is capable of direct access to on demand throttling MSR,\r | |
| 38 | // we use MSR method;otherwise we use IO method.\r | |
| 39 | //\r | |
| 40 | //\r | |
| 41 | // PDCx[2] = Indicates whether OSPM is capable of direct access to\r | |
| 42 | // on demand throttling MSR.\r | |
| 43 | //\r | |
| 44 | Method(_PTC, 0)\r | |
| 45 | {\r | |
| 46 | If(And(PDC0, 0x0004))\r | |
| 47 | {\r | |
| 48 | Return(Package() // MSR Method\r | |
| 49 | {\r | |
| 50 | ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r | |
| 51 | ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}\r | |
| 52 | }\r | |
| 53 | )\r | |
| 54 | }\r | |
| 55 | Return(Package() // IO Method\r | |
| 56 | {\r | |
| 57 | //\r | |
| 58 | // PM IO base ("PMBALVL0" will be updated at runtime)\r | |
| 59 | //\r | |
| 60 | ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)},\r | |
| 61 | ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)}\r | |
| 62 | }\r | |
| 63 | )\r | |
| 64 | }\r | |
| 65 | \r | |
| 66 | //\r | |
| 67 | // _TSS returned package for IO Method\r | |
| 68 | //\r | |
| 69 | Name(TSSI, Package()\r | |
| 70 | {\r | |
| 71 | Package(){100, 1000, 0, 0x00, 0}\r | |
| 72 | }\r | |
| 73 | )\r | |
| 74 | //\r | |
| 75 | // _TSS returned package for MSR Method\r | |
| 76 | //\r | |
| 77 | Name(TSSM, Package()\r | |
| 78 | {\r | |
| 79 | Package(){100, 1000, 0, 0x00, 0}\r | |
| 80 | }\r | |
| 81 | )\r | |
| 82 | \r | |
| 83 | Method(_TSS, 0)\r | |
| 84 | {\r | |
| 85 | //\r | |
| 86 | // If OSPM is capable of direct access to on demand throttling MSR,\r | |
| 87 | // we report TSSM;otherwise report TSSI.\r | |
| 88 | //\r | |
| 89 | If(And(PDC0, 0x0004))\r | |
| 90 | {\r | |
| 91 | Return(TSSM)\r | |
| 92 | }\r | |
| 93 | Return(TSSI)\r | |
| 94 | }\r | |
| 95 | \r | |
| 96 | Method(_TSD, 0)\r | |
| 97 | {\r | |
| 98 | //\r | |
| 99 | // If CMP is suppored, we report the dependency with two processors\r | |
| 100 | //\r | |
| 101 | If(LAnd(And(CFGD, 0x1000000), LNot(And(PDC0, 4))))\r | |
| 102 | {\r | |
| 103 | Return(Package()\r | |
| 104 | {\r | |
| 105 | Package()\r | |
| 106 | {\r | |
| 107 | 5, // # entries.\r | |
| 108 | 0, // Revision.\r | |
| 109 | 0, // Domain #.\r | |
| 110 | 0xFD, // Coord Type- SW_ANY\r | |
| 111 | 2 // # processors.\r | |
| 112 | }\r | |
| 113 | }\r | |
| 114 | )\r | |
| 115 | }\r | |
| 116 | //\r | |
| 117 | // Otherwise, we report the dependency with one processor\r | |
| 118 | //\r | |
| 119 | Return(Package()\r | |
| 120 | {\r | |
| 121 | Package()\r | |
| 122 | {\r | |
| 123 | 5, // # entries.\r | |
| 124 | 0, // Revision.\r | |
| 125 | 0, // Domain #.\r | |
| 126 | 0xFC, // Coord Type- SW_ALL\r | |
| 127 | 1 // # processors.\r | |
| 128 | }\r | |
| 129 | }\r | |
| 130 | )\r | |
| 131 | }\r | |
| 132 | }\r | |
| 133 | }\r |