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QuarkPlatformPkg: Replace BSD License with BSD+Patent License
[mirror_edk2.git] / QuarkPlatformPkg / Acpi / AcpiTables / Dsdt / Platform.asl
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b303605e
MK		 1/** @file\r
2Contains root level name space objects for the platform\r
3\r
4Copyright (c) 2013-2015 Intel Corporation.\r
5\r
0eb3de2e 6SPDX-License-Identifier: BSD-2-Clause-Patent\r
b303605e
MK		 7\r
8**/\r
9\r
10//\r
11// OS TYPE DEFINITION\r
12//\r
13#define WINDOWS_XP 0x01\r
14#define WINDOWS_XP_SP1 0x02\r
15#define WINDOWS_XP_SP2 0x04\r
16#define WINDOWS_2003 0x08\r
17#define WINDOWS_Vista 0x10\r
18#define WINDOWS_WIN7 0x11\r
19#define WINDOWS_WIN8 0x12\r
20#define WINDOWS_WIN8_1 0x13\r
21#define LINUX 0xF0\r
22\r
23//\r
24// GPIO Interrupt Connection Resource Descriptor (GpioInt) usage.\r
25// GpioInt() descriptors maybe used in this file and included .asi files.\r
26//\r
27// The mapping below was provided by the first OS user that requested\r
28// GpioInt() support.\r
29// Other OS users that need GpioInt() support must use the following mapping.\r
30//\r
31#define QUARK_GPIO8_MAPPING 0x00\r
32#define QUARK_GPIO9_MAPPING 0x01\r
33#define QUARK_GPIO_SUS0_MAPPING 0x02\r
34#define QUARK_GPIO_SUS1_MAPPING 0x03\r
35#define QUARK_GPIO_SUS2_MAPPING 0x04\r
36#define QUARK_GPIO_SUS3_MAPPING 0x05\r
37#define QUARK_GPIO_SUS4_MAPPING 0x06\r
38#define QUARK_GPIO_SUS5_MAPPING 0x07\r
39#define QUARK_GPIO0_MAPPING 0x08\r
40#define QUARK_GPIO1_MAPPING 0x09\r
41#define QUARK_GPIO2_MAPPING 0x0A\r
42#define QUARK_GPIO3_MAPPING 0x0B\r
43#define QUARK_GPIO4_MAPPING 0x0C\r
44#define QUARK_GPIO5_MAPPING 0x0D\r
45#define QUARK_GPIO6_MAPPING 0x0E\r
46#define QUARK_GPIO7_MAPPING 0x0F\r
47\r
48DefinitionBlock (\r
49 "Platform.aml",\r
50 "DSDT",\r
51 1,\r
52 "INTEL ",\r
53 "QuarkNcSocId",\r
54 3)\r
55{\r
56 //\r
57 // Global Variables\r
58 //\r
59 Name(\GPIC, 0x0)\r
60\r
61 //\r
62 // Port 80\r
63 //\r
64 OperationRegion (DBG0, SystemIO, 0x80, 1)\r
65 Field (DBG0, ByteAcc, NoLock, Preserve)\r
66 { IO80,8 }\r
67\r
68 //\r
69 // Access CMOS range\r
70 //\r
71 OperationRegion (ACMS, SystemIO, 0x72, 2)\r
72 Field (ACMS, ByteAcc, NoLock, Preserve)\r
73 { INDX, 8, DATA, 8 }\r
74\r
75 //\r
76 // Global NVS Memory Block\r
77 //\r
78 OperationRegion (MNVS, SystemMemory, 0xFFFF0000, 512)\r
79 Field (MNVS, ByteAcc, NoLock, Preserve)\r
80 {\r
81 OSTP, 32,\r
82 CFGD, 32,\r
83 HPEA, 32, // HPET Enabled ?\r
84\r
85 P1BB, 32, // Pm1blkIoBaseAddress;\r
86 PBAB, 32, // PmbaIoBaseAddress;\r
87 GP0B, 32, // Gpe0blkIoBaseAddress;\r
88 GPAB, 32, // GbaIoBaseAddress;\r
89\r
90 SMBB, 32, // SmbaIoBaseAddress;\r
91 NRV1, 32, // GNVS reserved field 1.\r
92 WDTB, 32, // WdtbaIoBaseAddress;\r
93\r
94 HPTB, 32, // HpetBaseAddress;\r
95 HPTS, 32, // HpetSize;\r
96 PEXB, 32, // PciExpressBaseAddress;\r
97 PEXS, 32, // PciExpressSize;\r
98\r
99 RCBB, 32, // RcbaMmioBaseAddress;\r
100 RCBS, 32, // RcbaMmioSize;\r
101 APCB, 32, // IoApicBaseAddress;\r
102 APCS, 32, // IoApicSize;\r
103\r
104 TPMP, 32, // TpmPresent ?\r
105 DBGP, 32, // DBG2 Present?\r
106 PTYP, 32, // Set to one of EFI_PLATFORM_TYPE enums.\r
107 ALTS, 32, // Use alternate I2c SLA addresses.\r
108 }\r
109\r
110 OperationRegion (GPEB, SystemIO, 0x1100, 0x40) //GPE Block\r
111 Field (GPEB, AnyAcc, NoLock, Preserve)\r
112 {\r
113 Offset(0x10),\r
114 SMIE, 32, // SMI Enable\r
115 SMIS, 32, // SMI Status\r
116 }\r
117\r
118 //\r
119 // Processor Objects\r
120 //\r
121 Scope(\_PR) {\r
122 //\r
123 // IO base will be updated at runtime with search key "PRIO"\r
124 //\r
125 Processor (CPU0, 0x01, 0x4F495250, 0x06) {}\r
126 }\r
127\r
128 //\r
129 // System Sleep States\r
130 //\r
131 Name (\_S0,Package (){0,0,0,0})\r
132 Name (\_S3,Package (){5,0,0,0})\r
133 Name (\_S4,Package (){6,0,0,0})\r
134 Name (\_S5,Package (){7,0,0,0})\r
135\r
136 //\r
137 // General Purpose Event\r
138 //\r
139 Scope(\_GPE)\r
140 {\r
141 //\r
142 // EGPE generated GPE\r
143 //\r
144 Method(_L0D, 0x0, NotSerialized)\r
145 {\r
146 //\r
147 // Check EGPE for this wake event\r
148 //\r
149 Notify (\_SB.SLPB, 0x02)\r
150\r
151 }\r
152\r
153 //\r
154 // GPIO generated GPE\r
155 //\r
156 Method(_L0E, 0x0, NotSerialized)\r
157 {\r
158 //\r
159 // Check GPIO for this wake event\r
160 //\r
161 Notify (\_SB.PWRB, 0x02)\r
162\r
163 }\r
164\r
165 //\r
166 // SCLT generated GPE\r
167 //\r
168 Method(_L0F, 0x0, NotSerialized)\r
169 {\r
170 //\r
171 // Check SCLT for this wake event\r
172 //\r
173 Notify (\_SB.PCI0.SDIO, 0x02)\r
174 Notify (\_SB.PCI0.URT0, 0x02)\r
175 Notify (\_SB.PCI0.USBD, 0x02)\r
176 Notify (\_SB.PCI0.EHCI, 0x02)\r
177 Notify (\_SB.PCI0.OHCI, 0x02)\r
178 Notify (\_SB.PCI0.URT1, 0x02)\r
179 Notify (\_SB.PCI0.ENT0, 0x02)\r
180 Notify (\_SB.PCI0.ENT1, 0x02)\r
181 Notify (\_SB.PCI0.SPI0, 0x02)\r
182 Notify (\_SB.PCI0.SPI1, 0x02)\r
183 Notify (\_SB.PCI0.GIP0, 0x02)\r
184\r
185 }\r
186\r
187 //\r
188 // Remote Management Unit generated GPE\r
189 //\r
190 Method(_L10, 0x0, NotSerialized)\r
191 {\r
192 //\r
193 // Check Remote Management Unit for this wake event.\r
194 //\r
195 }\r
196\r
197 //\r
198 // PCIE generated GPE\r
199 //\r
200 Method(_L11, 0x0, NotSerialized)\r
201 {\r
202 //\r
203 // Check PCIE for this wake event\r
204 //\r
205 Notify (\_SB.PCI0.PEX0, 0x02)\r
206 Notify (\_SB.PCI0.PEX1, 0x02)\r
207 }\r
208 }\r
209\r
210 //\r
211 // define Sleeping button as mentioned in ACPI spec 2.0\r
212 //\r
213 Device (\_SB.SLPB)\r
214 {\r
215 Name (_HID, EISAID ("PNP0C0E"))\r
216 Method (_PRW, 0, NotSerialized)\r
217 {\r
218 Return (Package (0x02) {0x0D,0x04})\r
219 }\r
220 }\r
221\r
222 //\r
223 // define Power Button\r
224 //\r
225 Device (\_SB.PWRB)\r
226 {\r
227 Name (_HID, EISAID ("PNP0C0C"))\r
228 Method (_PRW, 0, NotSerialized)\r
229 {\r
230 Return (Package (0x02) {0x0E,0x04})\r
231 }\r
232 }\r
233 //\r
234 // System Wake up\r
235 //\r
236 Method(_WAK, 1, Serialized)\r
237 {\r
238 // Do nothing here\r
239 Return (0)\r
240 }\r
241\r
242 //\r
243 // System sleep down\r
244 //\r
245 Method (_PTS, 1, NotSerialized)\r
246 {\r
247 // Get ready for S3 sleep\r
248 if (Lequal(Arg0,3))\r
249 {\r
250 Store(0xffffffff,SMIS) // clear SMI status\r
251 Store(SMIE, Local0) // SMI Enable\r
252 Or(Local0,0x4,SMIE) // Generate SMI on sleep\r
253 }\r
254 }\r
255\r
256 //\r
257 // Determing PIC mode\r
258 //\r
259 Method(\_PIC, 1, NotSerialized)\r
260 {\r
261 Store(Arg0,\GPIC)\r
262 }\r
263\r
264 //\r
265 // System Bus\r
266 //\r
267 Scope(\_SB)\r
268 {\r
269 Device(PCI0)\r
270 {\r
271 Name(_HID,EISAID ("PNP0A08")) // PCI Express Root Bridge\r
272 Name(_CID,EISAID ("PNP0A03")) // Compatible PCI Root Bridge\r
273\r
274 Name(_ADR,0x00000000) // Device (HI WORD)=0, Func (LO WORD)=0\r
275 Method (_INI)\r
276 {\r
277 Store(LINUX, OSTP) // Set the default os is Linux\r
278 If (CondRefOf (_OSI, local0))\r
279 {\r
280 //\r
281 //_OSI is supported, so it is WinXp or Win2003Server\r
282 //\r
283 If (\_OSI("Windows 2001"))\r
284 {\r
285 Store (WINDOWS_XP, OSTP)\r
286 }\r
287 If (\_OSI("Windows 2001 SP1"))\r
288 {\r
289 Store (WINDOWS_XP_SP1, OSTP)\r
290 }\r
291 If (\_OSI("Windows 2001 SP2"))\r
292 {\r
293 Store (WINDOWS_XP_SP2, OSTP)\r
294 }\r
295 If (\_OSI("Windows 2001.1"))\r
296 {\r
297 Store (WINDOWS_2003, OSTP)\r
298 }\r
299 If (\_OSI("Windows 2006"))\r
300 {\r
301 Store (WINDOWS_Vista, OSTP)\r
302 }\r
303 If (\_OSI("Windows 2009"))\r
304 {\r
305 Store (WINDOWS_WIN7, OSTP)\r
306 }\r
307 If (\_OSI("Windows 2012"))\r
308 {\r
309 Store (WINDOWS_WIN8, OSTP)\r
310 }\r
311 If (\_OSI("Windows 2013"))\r
312 {\r
313 Store (WINDOWS_WIN8_1, OSTP)\r
314 }\r
315 If (\_OSI("Linux"))\r
316 {\r
317 Store (LINUX, OSTP)\r
318 }\r
319 }\r
320 }\r
321\r
322 Include ("PciHostBridge.asi") // PCI0 Host bridge\r
323 Include ("QNC.asi") // QNC miscellaneous\r
324 Include ("PcieExpansionPrt.asi") // PCIe expansion bridges/devices\r
325 Include ("QuarkSouthCluster.asi") // Quark South Cluster devices\r
326 Include ("QNCLpc.asi") // LPC bridge device\r
327 Include ("QNCApic.asi") // QNC I/O Apic device\r
328\r
329 }\r
330\r
331 //\r
332 // Include asi files for I2C and SPI onboard devices.\r
333 // Devices placed here instead of below relevant controllers.\r
334 // Hardware topology information is maintained by the\r
335 // ResourceSource arg to the I2CSerialBus/SPISerialBus macros\r
336 // within the device asi files.\r
337 //\r
338 Include ("Tpm.asi") // TPM device.\r
339 Include ("CY8C9540A.asi") // CY8C9540A 40Bit I/O Expander & EEPROM\r
340 Include ("PCAL9555A.asi") // NXP PCAL9555A I/O expander.\r
341 Include ("PCA9685.asi") // NXP PCA9685 PWM/LED controller.\r
342 Include ("CAT24C08.asi") // ONSEMI CAT24C08 I2C 8KB EEPROM.\r
343 Include ("AD7298.asi") // Analog devices AD7298 ADC.\r
344 Include ("ADC108S102.asi") // TI ADC108S102 ADC.\r
345 Include ("GpioClient.asi") // Software device to expose GPIO\r
346 }\r
347}\r
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