QuarkSocPkg/QncSmmDispatcher: Fix context passed to SMI handlers
[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Include / IntelQNCConfig.h
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9b6bbcdb
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1/** @file\r
2Some configuration of QNC Package\r
3\r
4Copyright (c) 2013-2015 Intel Corporation.\r
5\r
6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef __INTEL_QNC_CONFIG_H__\r
17#define __INTEL_QNC_CONFIG_H__\r
18\r
19//\r
20// QNC Fixed configurations.\r
21//\r
22\r
23//\r
24// Memory arbiter fixed config values.\r
25//\r
26#define QNC_FIXED_CONFIG_ASTATUS ((UINT32) (\\r
27 (ASTATUS_PRI_NORMAL << ASTATUS0_DEFAULT_BP) | \\r
28 (ASTATUS_PRI_NORMAL << ASTATUS1_DEFAULT_BP) | \\r
29 (ASTATUS_PRI_URGENT << ASTATUS0_RASISED_BP) | \\r
30 (ASTATUS_PRI_URGENT << ASTATUS1_RASISED_BP) \\r
31 ))\r
32\r
33//\r
34// Memory Manager fixed config values.\r
35//\r
36#define V_DRAM_NON_HOST_RQ_LIMIT 2\r
37\r
38//\r
39// RMU Thermal config fixed config values for TS in Vref Mode.\r
40//\r
41#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_VREF_MODE 0x04\r
42#define V_TSCGF2_CONFIG2_ISPARECTRL_VREF_MODE 0x01\r
43#define V_TSCGF1_CONFIG_IBGEN_VREF_MODE 1\r
44#define V_TSCGF2_CONFIG_IDSCONTROL_VREF_MODE 0x011b\r
45#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_VREF_MODE 0x34\r
46\r
47//\r
48// RMU Thermal config fixed config values for TS in Ratiometric mode.\r
49//\r
50#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE 0x04\r
51#define V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE 0x02\r
52#define V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE 1\r
53#define V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE 0x011f\r
54#define V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE 0x0001\r
55#define V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE 0x01\r
56#define V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE 0x00\r
57#define V_TSCGF1_CONFIG_IBGEN_RATIO_MODE 0\r
58#define V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE 0\r
59#define V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE 0xC8\r
60#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE 0x17\r
61\r
62//\r
63// iCLK fixed config values.\r
64//\r
65#define V_MUXTOP_FLEX2 3\r
66#define V_MUXTOP_FLEX1 1\r
67\r
68//\r
69// PCIe Root Port fixed config values.\r
70//\r
71#define V_PCIE_ROOT_PORT_SBIC_VALUE (B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER)\r
72\r
73//\r
74// QNC structures for configuration.\r
75//\r
76\r
77typedef union {\r
78 struct {\r
79 UINT32 PortErrorMask :8;\r
80 UINT32 SlotImplemented :1;\r
81 UINT32 Reserved1 :1;\r
82 UINT32 AspmEnable :1;\r
83 UINT32 AspmAutoEnable :1;\r
84 UINT32 AspmL0sEnable :2;\r
85 UINT32 AspmL1Enable :1;\r
86 UINT32 PmeInterruptEnable :1;\r
87 UINT32 PhysicalSlotNumber :13;\r
88 UINT32 Reserved2 :1;\r
89 UINT32 PmSciEnable :1;\r
90 UINT32 HotplugSciEnable :1;\r
91 } Bits;\r
92 UINT32 Uint32;\r
93} PCIEXP_ROOT_PORT_CONFIGURATION;\r
94\r
95typedef union {\r
96 UINT32 Uint32;\r
97 struct {\r
98 UINT32 Pcie_0 :1; // 0: Disabled; 1: Enabled*\r
99 UINT32 Pcie_1 :1; // 0: Disabled; 1: Enabled*\r
100 UINT32 Smbus :1; // 0: Disabled; 1: Enabled*\r
101 UINT32 Rsvd :29; // 0\r
102 } Bits;\r
103} QNC_DEVICE_ENABLES;\r
104\r
105#endif\r
106\r