QuarkSocPkg/QncSmmDispatcher: Fix context passed to SMI handlers
[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Include / QNCAccess.h
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1/** @file\r
2Macros to simplify and abstract the interface to PCI configuration.\r
3\r
4Copyright (c) 2013-2015 Intel Corporation.\r
5\r
6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14\r
15**/\r
16\r
17#ifndef _QNC_ACCESS_H_\r
18#define _QNC_ACCESS_H_\r
19\r
20#include "QuarkNcSocId.h"\r
21#include "QNCCommonDefinitions.h"\r
22\r
23#define EFI_LPC_PCI_ADDRESS( Register ) \\r
24 EFI_PCI_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, Register)\r
25\r
26//\r
27// QNC Controller PCI access macros\r
28//\r
29#define QNC_RCRB_BASE (QNCMmio32 (PciDeviceMmBase (0, PCI_DEVICE_NUMBER_QNC_LPC, 0), R_QNC_LPC_RCBA) & B_QNC_LPC_RCBA_MASK)\r
30\r
31//\r
32// Device 0x1f, Function 0\r
33//\r
34\r
35#define LpcPciCfg32( Register ) \\r
36 QNCMmPci32(0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )\r
37\r
38#define LpcPciCfg32Or( Register, OrData ) \\r
39 QNCMmPci32Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )\r
40\r
41#define LpcPciCfg32And( Register, AndData ) \\r
42 QNCMmPci32And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )\r
43\r
44#define LpcPciCfg32AndThenOr( Register, AndData, OrData ) \\r
45 QNCMmPci32AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )\r
46\r
47#define LpcPciCfg16( Register ) \\r
48 QNCMmPci16( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )\r
49\r
50#define LpcPciCfg16Or( Register, OrData ) \\r
51 QNCMmPci16Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )\r
52\r
53#define LpcPciCfg16And( Register, AndData ) \\r
54 QNCMmPci16And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )\r
55\r
56#define LpcPciCfg16AndThenOr( Register, AndData, OrData ) \\r
57 QNCMmPci16AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )\r
58\r
59#define LpcPciCfg8( Register ) \\r
60 QNCMmPci8( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )\r
61\r
62#define LpcPciCfg8Or( Register, OrData ) \\r
63 QNCMmPci8Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )\r
64\r
65#define LpcPciCfg8And( Register, AndData ) \\r
66 QNCMmPci8And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )\r
67\r
68#define LpcPciCfg8AndThenOr( Register, AndData, OrData ) \\r
69 QNCMmPci8AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )\r
70\r
71//\r
72// Root Complex Register Block\r
73//\r
74\r
75#define MmRcrb32( Register ) \\r
76 QNCMmio32( QNC_RCRB_BASE, Register )\r
77\r
78#define MmRcrb32Or( Register, OrData ) \\r
79 QNCMmio32Or( QNC_RCRB_BASE, Register, OrData )\r
80\r
81#define MmRcrb32And( Register, AndData ) \\r
82 QNCMmio32And( QNC_RCRB_BASE, Register, AndData )\r
83\r
84#define MmRcrb32AndThenOr( Register, AndData, OrData ) \\r
85 QNCMmio32AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )\r
86\r
87#define MmRcrb16( Register ) \\r
88 QNCMmio16( QNC_RCRB_BASE, Register )\r
89\r
90#define MmRcrb16Or( Register, OrData ) \\r
91 QNCMmio16Or( QNC_RCRB_BASE, Register, OrData )\r
92\r
93#define MmRcrb16And( Register, AndData ) \\r
94 QNCMmio16And( QNC_RCRB_BASE, Register, AndData )\r
95\r
96#define MmRcrb16AndThenOr( Register, AndData, OrData ) \\r
97 QNCMmio16AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )\r
98\r
99#define MmRcrb8( Register ) \\r
100 QNCMmio8( QNC_RCRB_BASE, Register )\r
101\r
102#define MmRcrb8Or( Register, OrData ) \\r
103 QNCMmio8Or( QNC_RCRB_BASE, Register, OrData )\r
104\r
105#define MmRcrb8And( Register, AndData ) \\r
106 QNCMmio8And( QNC_RCRB_BASE, Register, AndData )\r
107\r
108#define MmRcrb8AndThenOr( Register, AndData, OrData ) \\r
109 QNCMmio8AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )\r
110\r
111//\r
112// Memory Controller PCI access macros\r
113//\r
114\r
115//\r
116// Device 0, Function 0\r
117//\r
118\r
119#define McD0PciCfg64(Register) QNCMmPci32 (0, MC_BUS, 0, 0, Register)\r
120#define McD0PciCfg64Or(Register, OrData) QNCMmPci32Or (0, MC_BUS, 0, 0, Register, OrData)\r
121#define McD0PciCfg64And(Register, AndData) QNCMmPci32And (0, MC_BUS, 0, 0, Register, AndData)\r
122#define McD0PciCfg64AndThenOr(Register, AndData, OrData) QNCMmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
123\r
124#define McD0PciCfg32(Register) QNCMmPci32 (0, MC_BUS, 0, 0, Register)\r
125#define McD0PciCfg32Or(Register, OrData) QNCMmPci32Or (0, MC_BUS, 0, 0, Register, OrData)\r
126#define McD0PciCfg32And(Register, AndData) QNCMmPci32And (0, MC_BUS, 0, 0, Register, AndData)\r
127#define McD0PciCfg32AndThenOr(Register, AndData, OrData) QNCMmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
128\r
129#define McD0PciCfg16(Register) QNCMmPci16 (0, MC_BUS, 0, 0, Register)\r
130#define McD0PciCfg16Or(Register, OrData) QNCMmPci16Or (0, MC_BUS, 0, 0, Register, OrData)\r
131#define McD0PciCfg16And(Register, AndData) QNCMmPci16And (0, MC_BUS, 0, 0, Register, AndData)\r
132#define McD0PciCfg16AndThenOr(Register, AndData, OrData) QNCMmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
133\r
134#define McD0PciCfg8(Register) QNCMmPci8 (0, MC_BUS, 0, 0, Register)\r
135#define McD0PciCfg8Or(Register, OrData) QNCMmPci8Or (0, MC_BUS, 0, 0, Register, OrData)\r
136#define McD0PciCfg8And(Register, AndData) QNCMmPci8And (0, MC_BUS, 0, 0, Register, AndData)\r
137#define McD0PciCfg8AndThenOr( Register, AndData, OrData ) QNCMmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
138\r
139\r
140//\r
141// Memory Controller Hub Memory Mapped IO register access ???\r
142//\r
143#define MCH_REGION_BASE (McD0PciCfg64 (MC_MCHBAR_OFFSET) & ~BIT0)\r
144#define McMmioAddress(Register) ((UINTN) MCH_REGION_BASE + (UINTN) (Register))\r
145\r
146#define McMmio32Ptr(Register) ((volatile UINT32*) McMmioAddress (Register))\r
147#define McMmio64Ptr(Register) ((volatile UINT64*) McMmioAddress (Register))\r
148\r
149#define McMmio64(Register) *McMmio64Ptr( Register )\r
150#define McMmio64Or(Register, OrData) (McMmio64 (Register) |= (UINT64)(OrData))\r
151#define McMmio64And(Register, AndData) (McMmio64 (Register) &= (UINT64)(AndData))\r
152#define McMmio64AndThenOr(Register, AndData, OrData) (McMmio64 ( Register ) = (McMmio64( Register ) & (UINT64)(AndData)) | (UINT64)(OrData))\r
153\r
154#define McMmio32(Register) *McMmio32Ptr (Register)\r
155#define McMmio32Or(Register, OrData) (McMmio32 (Register) |= (UINT32)(OrData))\r
156#define McMmio32And(Register, AndData) (McMmio32 (Register) &= (UINT32)(AndData))\r
157#define McMmio32AndThenOr(Register, AndData, OrData) (McMmio32 (Register) = (McMmio32 (Register) & (UINT32) (AndData)) | (UINT32) (OrData))\r
158\r
159#define McMmio16Ptr(Register) ((volatile UINT16*) McMmioAddress (Register))\r
160#define McMmio16(Register) *McMmio16Ptr (Register)\r
161#define McMmio16Or(Register, OrData) (McMmio16 (Register) |= (UINT16) (OrData))\r
162#define McMmio16And(Register, AndData) (McMmio16 (Register) &= (UINT16) (AndData))\r
163#define McMmio16AndThenOr(Register, AndData, OrData) (McMmio16 (Register) = (McMmio16 (Register) & (UINT16) (AndData)) | (UINT16) (OrData))\r
164\r
165#define McMmio8Ptr(Register) ((volatile UINT8 *)McMmioAddress (Register))\r
166#define McMmio8(Register) *McMmio8Ptr (Register)\r
167#define McMmio8Or(Register, OrData) (McMmio8 (Register) |= (UINT8) (OrData))\r
168#define McMmio8And(Register, AndData) (McMmio8 (Register) &= (UINT8) (AndData))\r
169#define McMmio8AndThenOr(Register, AndData, OrData) (McMmio8 (Register) = (McMmio8 (Register) & (UINT8) (AndData)) | (UINT8) (OrData))\r
170\r
171//\r
172// QNC memory mapped related data structure deifinition\r
173//\r
174typedef enum {\r
175 QNCMmioWidthUint8 = 0,\r
176 QNCMmioWidthUint16 = 1,\r
177 QNCMmioWidthUint32 = 2,\r
178 QNCMmioWidthUint64 = 3,\r
179 QNCMmioWidthMaximum\r
180} QNC_MEM_IO_WIDTH;\r
181\r
182#endif\r
183\r