[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c

/** @file\r
The Quark CPU specific programming for PiSmmCpuDxeSmm module.\r
\r
Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <PiSmm.h>\r
#include <Library/SmmCpuFeaturesLib.h>\r
#include <Register/SmramSaveStateMap.h>\r
#include <Library/QNCAccessLib.h>\r
\r
#define  EFI_MSR_SMRR_PHYS_MASK_VALID          BIT11\r
#define  EFI_MSR_SMRR_MASK                     0xFFFFF000\r
\r
/**\r
  Called during the very first SMI into System Management Mode to initialize\r
  CPU features, including SMBASE, for the currently executing CPU.  Since this\r
  is the first SMI, the SMRAM Save State Map is at the default address of\r
  SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET.  The currently executing\r
  CPU is specified by CpuIndex and CpuIndex can be used to access information\r
  about the currently executing CPU in the ProcessorInfo array and the\r
  HotPlugCpuData data structure.\r
\r
  @param[in] CpuIndex        The index of the CPU to initialize.  The value\r
                             must be between 0 and the NumberOfCpus field in\r
                             the System Management System Table (SMST).\r
  @param[in] IsMonarch       TRUE if the CpuIndex is the index of the CPU that\r
                             was elected as monarch during System Management\r
                             Mode initialization.\r
                             FALSE if the CpuIndex is not the index of the CPU\r
                             that was elected as monarch during System\r
                             Management Mode initialization.\r
  @param[in] ProcessorInfo   Pointer to an array of EFI_PROCESSOR_INFORMATION\r
                             structures.  ProcessorInfo[CpuIndex] contains the\r
                             information for the currently executing CPU.\r
  @param[in] CpuHotPlugData  Pointer to the CPU_HOT_PLUG_DATA structure that\r
                             contains the ApidId and SmBase arrays.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesInitializeProcessor (\r
  IN UINTN                      CpuIndex,\r
  IN BOOLEAN                    IsMonarch,\r
  IN EFI_PROCESSOR_INFORMATION  *ProcessorInfo,\r
  IN CPU_HOT_PLUG_DATA          *CpuHotPlugData\r
  )\r
{\r
  SMRAM_SAVE_STATE_MAP  *CpuState;\r
\r
  //\r
  // Configure SMBASE.\r
  //\r
  CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
  CpuState->x86.SMBASE = CpuHotPlugData->SmBase[CpuIndex];\r
\r
  //\r
  // Use QNC to initialize SMRR on Quark\r
  //\r
  QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE, CpuHotPlugData->SmrrBase);\r
  QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
}\r
\r
/**\r
  This function updates the SMRAM save state on the currently executing CPU\r
  to resume execution at a specific address after an RSM instruction.  This\r
  function must evaluate the SMRAM save state to determine the execution mode\r
  the RSM instruction resumes and update the resume execution address with\r
  either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart\r
  flag in the SMRAM save state must always be cleared.  This function returns\r
  the value of the instruction pointer from the SMRAM save state that was\r
  replaced.  If this function returns 0, then the SMRAM save state was not\r
  modified.\r
\r
  This function is called during the very first SMI on each CPU after\r
  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
  to signal that the SMBASE of each CPU has been updated before the default\r
  SMBASE address is used for the first SMI to the next CPU.\r
\r
  @param[in] CpuIndex                 The index of the CPU to hook.  The value\r
                                      must be between 0 and the NumberOfCpus\r
                                      field in the System Management System Table\r
                                      (SMST).\r
  @param[in] CpuState                 Pointer to SMRAM Save State Map for the\r
                                      currently executing CPU.\r
  @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to\r
                                      32-bit execution mode from 64-bit SMM.\r
  @param[in] NewInstructionPointer    Instruction pointer to use if resuming to\r
                                      same execution mode as SMM.\r
\r
  @retval 0    This function did modify the SMRAM save state.\r
  @retval > 0  The original instruction pointer value from the SMRAM save state\r
               before it was replaced.\r
**/\r
UINT64\r
EFIAPI\r
SmmCpuFeaturesHookReturnFromSmm (\r
  IN UINTN                 CpuIndex,\r
  IN SMRAM_SAVE_STATE_MAP  *CpuState,\r
  IN UINT64                NewInstructionPointer32,\r
  IN UINT64                NewInstructionPointer\r
  )\r
{\r
  return 0;\r
}\r
\r
/**\r
  Hook point in normal execution mode that allows the one CPU that was elected\r
  as monarch during System Management Mode initialization to perform additional\r
  initialization actions immediately after all of the CPUs have processed their\r
  first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
  into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesSmmRelocationComplete (\r
  VOID\r
  )\r
{\r
}\r
\r
/**\r
  Return the size, in bytes, of a custom SMI Handler in bytes.  If 0 is\r
  returned, then a custom SMI handler is not provided by this library,\r
  and the default SMI handler must be used.\r
\r
  @retval 0    Use the default SMI handler.\r
  @retval > 0  Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
               The caller is required to allocate enough SMRAM for each CPU to\r
               support the size of the custom SMI handler.\r
**/\r
UINTN\r
EFIAPI\r
SmmCpuFeaturesGetSmiHandlerSize (\r
  VOID\r
  )\r
{\r
  return 0;\r
}\r
\r
/**\r
  Install a custom SMI handler for the CPU specified by CpuIndex.  This function\r
  is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
  than zero and is called by the CPU that was elected as monarch during System\r
  Management Mode initialization.\r
\r
  @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.\r
                        The value must be between 0 and the NumberOfCpus field\r
                        in the System Management System Table (SMST).\r
  @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.\r
  @param[in] SmiStack   The stack to use when an SMI is processed by the\r
                        the CPU specified by CpuIndex.\r
  @param[in] StackSize  The size, in bytes, if the stack used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] GdtBase    The base address of the GDT to use when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] IdtBase    The base address of the IDT to use when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] Cr3        The base address of the page tables to use when an SMI\r
                        is processed by the CPU specified by CpuIndex.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesInstallSmiHandler (\r
  IN UINTN   CpuIndex,\r
  IN UINT32  SmBase,\r
  IN VOID    *SmiStack,\r
  IN UINTN   StackSize,\r
  IN UINTN   GdtBase,\r
  IN UINTN   GdtSize,\r
  IN UINTN   IdtBase,\r
  IN UINTN   IdtSize,\r
  IN UINT32  Cr3\r
  )\r
{\r
}\r
\r
/**\r
  Determines if MTRR registers must be configured to set SMRAM cache-ability\r
  when executing in System Management Mode.\r
\r
  @retval TRUE   MTRR registers must be configured to set SMRAM cache-ability.\r
  @retval FALSE  MTRR registers do not need to be configured to set SMRAM\r
                   cache-ability.\r
**/\r
BOOLEAN\r
EFIAPI\r
SmmCpuFeaturesNeedConfigureMtrrs (\r
  VOID\r
  )\r
{\r
  return TRUE;\r
}\r
\r
/**\r
  Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
  returns TRUE.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesDisableSmrr (\r
  VOID\r
  )\r
{\r
  //\r
  // Use QNC to disable SMRR on Quark\r
  //\r
  QNCPortWrite(\r
    QUARK_NC_HOST_BRIDGE_SB_PORT_ID,\r
    QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,\r
    QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) & ~EFI_MSR_SMRR_PHYS_MASK_VALID\r
    );\r
}\r
\r
/**\r
  Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
  returns TRUE.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesReenableSmrr (\r
  VOID\r
  )\r
{\r
  //\r
  // Use QNC to enable SMRR on Quark\r
  //\r
  QNCPortWrite(\r
    QUARK_NC_HOST_BRIDGE_SB_PORT_ID,\r
    QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,\r
    QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) | EFI_MSR_SMRR_PHYS_MASK_VALID\r
    );\r
}\r
\r
/**\r
  Processor specific hook point each time a CPU enters System Management Mode.\r
\r
  @param[in] CpuIndex  The index of the CPU that has entered SMM.  The value\r
                       must be between 0 and the NumberOfCpus field in the\r
                       System Management System Table (SMST).\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesRendezvousEntry (\r
  IN UINTN  CpuIndex\r
  )\r
{\r
}\r
\r
/**\r
  Processor specific hook point each time a CPU exits System Management Mode.\r
\r
  @param[in] CpuIndex  The index of the CPU that is exiting SMM.  The value must\r
                       be between 0 and the NumberOfCpus field in the System\r
                       Management System Table (SMST).\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesRendezvousExit (\r
  IN UINTN  CpuIndex\r
  )\r
{\r
}\r
\r
/**\r
  Check to see if an SMM register is supported by a specified CPU.\r
\r
  @param[in] CpuIndex  The index of the CPU to check for SMM register support.\r
                       The value must be between 0 and the NumberOfCpus field\r
                       in the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to check for support.\r
\r
  @retval TRUE   The SMM register specified by RegName is supported by the CPU\r
                 specified by CpuIndex.\r
  @retval FALSE  The SMM register specified by RegName is not supported by the\r
                 CPU specified by CpuIndex.\r
**/\r
BOOLEAN\r
EFIAPI\r
SmmCpuFeaturesIsSmmRegisterSupported (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName\r
  )\r
{\r
  return FALSE;\r
}\r
\r
/**\r
  Returns the current value of the SMM register for the specified CPU.\r
  If the SMM register is not supported, then 0 is returned.\r
\r
  @param[in] CpuIndex  The index of the CPU to read the SMM register.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to read.\r
\r
  @return  The value of the SMM register specified by RegName from the CPU\r
           specified by CpuIndex.\r
**/\r
UINT64\r
EFIAPI\r
SmmCpuFeaturesGetSmmRegister (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName\r
  )\r
{\r
  return 0;\r
}\r
\r
/**\r
  Sets the value of an SMM register on a specified CPU.\r
  If the SMM register is not supported, then no action is performed.\r
\r
  @param[in] CpuIndex  The index of the CPU to write the SMM register.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to write.\r
                       registers are read-only.\r
  @param[in] Value     The value to write to the SMM register.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesSetSmmRegister (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName,\r
  IN UINT64        Value\r
  )\r
{\r
}\r
\r
/**\r
  Read an SMM Save State register on the target processor.  If this function\r
  returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
  SMM Save Sate register.\r
\r
  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The\r
                        value must be between 0 and the NumberOfCpus field in\r
                        the System Management System Table (SMST).\r
  @param[in]  Register  The SMM Save State register to read.\r
  @param[in]  Width     The number of bytes to read from the CPU save state.\r
  @param[out] Buffer    Upon return, this holds the CPU register value read\r
                        from the save state.\r
\r
  @retval EFI_SUCCESS           The register was read from Save State.\r
  @retval EFI_INVALID_PARAMTER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED       This function does not support reading Register.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmCpuFeaturesReadSaveStateRegister (\r
  IN  UINTN                        CpuIndex,\r
  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN  UINTN                        Width,\r
  OUT VOID                         *Buffer\r
  )\r
{\r
  return EFI_UNSUPPORTED;\r
}\r
\r
/**\r
  Writes an SMM Save State register on the target processor.  If this function\r
  returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
  SMM Save Sate register.\r
\r
  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] Register  The SMM Save State register to write.\r
  @param[in] Width     The number of bytes to write to the CPU save state.\r
  @param[in] Buffer    Upon entry, this holds the new CPU register value.\r
\r
  @retval EFI_SUCCESS           The register was written to Save State.\r
  @retval EFI_INVALID_PARAMTER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED       This function does not support writing Register.\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmCpuFeaturesWriteSaveStateRegister (\r
  IN UINTN                        CpuIndex,\r
  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN UINTN                        Width,\r
  IN CONST VOID                   *Buffer\r
  )\r
{\r
  return EFI_UNSUPPORTED;\r
}\r
\r
/**\r
  This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
  notification is completely processed.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesCompleteSmmReadyToLock (\r
  VOID\r
  )\r
{\r
}\r
\r
/**\r
  This API provides a method for a CPU to allocate a specific region for storing page tables.\r
\r
  This API can be called more once to allocate memory for page tables.\r
\r
  Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL\r
  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is\r
  returned.\r
\r
  This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
\r
  @param  Pages                 The number of 4 KB pages to allocate.\r
\r
  @return A pointer to the allocated buffer for page tables.\r
  @retval NULL      Fail to allocate a specific region for storing page tables,\r
                    Or there is no preference on where the page tables are allocated in SMRAM.\r
\r
**/\r
VOID *\r
EFIAPI\r
SmmCpuFeaturesAllocatePageTableMemory (\r
  IN UINTN           Pages\r
  )\r
{\r
  return NULL;\r
}\r
Commit	Line	Data
9b6bbcdb MK	1	/** @file\r
	2	The Quark CPU specific programming for PiSmmCpuDxeSmm module.\r
	3	\r
	4	Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#include <PiSmm.h>\r
	16	#include <Library/SmmCpuFeaturesLib.h>\r
	17	#include <Register/SmramSaveStateMap.h>\r
	18	#include <Library/QNCAccessLib.h>\r
	19	\r
	20	#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11\r
	21	#define EFI_MSR_SMRR_MASK 0xFFFFF000\r
	22	\r
	23	/**\r
	24	Called during the very first SMI into System Management Mode to initialize\r
	25	CPU features, including SMBASE, for the currently executing CPU. Since this\r
	26	is the first SMI, the SMRAM Save State Map is at the default address of\r
	27	SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r
	28	CPU is specified by CpuIndex and CpuIndex can be used to access information\r
	29	about the currently executing CPU in the ProcessorInfo array and the\r
	30	HotPlugCpuData data structure.\r
	31	\r
	32	@param[in] CpuIndex The index of the CPU to initialize. The value\r
	33	must be between 0 and the NumberOfCpus field in\r
	34	the System Management System Table (SMST).\r
	35	@param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r
	36	was elected as monarch during System Management\r
	37	Mode initialization.\r
	38	FALSE if the CpuIndex is not the index of the CPU\r
	39	that was elected as monarch during System\r
	40	Management Mode initialization.\r
	41	@param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r
	42	structures. ProcessorInfo[CpuIndex] contains the\r
	43	information for the currently executing CPU.\r
	44	@param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r
	45	contains the ApidId and SmBase arrays.\r
	46	**/\r
	47	VOID\r
	48	EFIAPI\r
	49	SmmCpuFeaturesInitializeProcessor (\r
	50	IN UINTN CpuIndex,\r
	51	IN BOOLEAN IsMonarch,\r
	52	IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r
	53	IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r
	54	)\r
	55	{\r
	56	SMRAM_SAVE_STATE_MAP *CpuState;\r
	57	\r
	58	//\r
	59	// Configure SMBASE.\r
	60	//\r
	61	CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
	62	CpuState->x86.SMBASE = CpuHotPlugData->SmBase[CpuIndex];\r
	63	\r
	64	//\r
65	// Use QNC to initialize SMRR on Quark\r
66	//\r
67	QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE, CpuHotPlugData->SmrrBase);\r
68	QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK) \| EFI_MSR_SMRR_PHYS_MASK_VALID);\r
69	}\r
70	\r
71	/**\r
72	This function updates the SMRAM save state on the currently executing CPU\r
73	to resume execution at a specific address after an RSM instruction. This\r
74	function must evaluate the SMRAM save state to determine the execution mode\r
75	the RSM instruction resumes and update the resume execution address with\r
76	either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r
77	flag in the SMRAM save state must always be cleared. This function returns\r
78	the value of the instruction pointer from the SMRAM save state that was\r
79	replaced. If this function returns 0, then the SMRAM save state was not\r
80	modified.\r
81	\r
82	This function is called during the very first SMI on each CPU after\r
83	SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
84	to signal that the SMBASE of each CPU has been updated before the default\r
85	SMBASE address is used for the first SMI to the next CPU.\r
86	\r
87	@param[in] CpuIndex The index of the CPU to hook. The value\r
88	must be between 0 and the NumberOfCpus\r
89	field in the System Management System Table\r
90	(SMST).\r
91	@param[in] CpuState Pointer to SMRAM Save State Map for the\r
92	currently executing CPU.\r
93	@param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
94	32-bit execution mode from 64-bit SMM.\r
95	@param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
96	same execution mode as SMM.\r
97	\r
98	@retval 0 This function did modify the SMRAM save state.\r
99	@retval > 0 The original instruction pointer value from the SMRAM save state\r
100	before it was replaced.\r
101	**/\r
102	UINT64\r
103	EFIAPI\r
104	SmmCpuFeaturesHookReturnFromSmm (\r
105	IN UINTN CpuIndex,\r
106	IN SMRAM_SAVE_STATE_MAP *CpuState,\r
107	IN UINT64 NewInstructionPointer32,\r
108	IN UINT64 NewInstructionPointer\r
109	)\r
110	{\r
111	return 0;\r
112	}\r
113	\r
114	/**\r
115	Hook point in normal execution mode that allows the one CPU that was elected\r
116	as monarch during System Management Mode initialization to perform additional\r
117	initialization actions immediately after all of the CPUs have processed their\r
118	first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
119	into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
120	**/\r
121	VOID\r
122	EFIAPI\r
123	SmmCpuFeaturesSmmRelocationComplete (\r
124	VOID\r
125	)\r
126	{\r
127	}\r
128	\r
129	/**\r
130	Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is\r
131	returned, then a custom SMI handler is not provided by this library,\r
132	and the default SMI handler must be used.\r
133	\r
134	@retval 0 Use the default SMI handler.\r
135	@retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
136	The caller is required to allocate enough SMRAM for each CPU to\r
137	support the size of the custom SMI handler.\r
138	**/\r
139	UINTN\r
140	EFIAPI\r
141	SmmCpuFeaturesGetSmiHandlerSize (\r
142	VOID\r
143	)\r
144	{\r
145	return 0;\r
146	}\r
147	\r
148	/**\r
149	Install a custom SMI handler for the CPU specified by CpuIndex. This function\r
150	is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
151	than zero and is called by the CPU that was elected as monarch during System\r
152	Management Mode initialization.\r
153	\r
154	@param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
155	The value must be between 0 and the NumberOfCpus field\r
156	in the System Management System Table (SMST).\r
157	@param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
158	@param[in] SmiStack The stack to use when an SMI is processed by the\r
159	the CPU specified by CpuIndex.\r
160	@param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
161	processed by the CPU specified by CpuIndex.\r
162	@param[in] GdtBase The base address of the GDT to use when an SMI is\r
163	processed by the CPU specified by CpuIndex.\r
164	@param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
165	processed by the CPU specified by CpuIndex.\r
166	@param[in] IdtBase The base address of the IDT to use when an SMI is\r
167	processed by the CPU specified by CpuIndex.\r
168	@param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
169	processed by the CPU specified by CpuIndex.\r
170	@param[in] Cr3 The base address of the page tables to use when an SMI\r
171	is processed by the CPU specified by CpuIndex.\r
172	**/\r
173	VOID\r
174	EFIAPI\r
175	SmmCpuFeaturesInstallSmiHandler (\r
176	IN UINTN CpuIndex,\r
177	IN UINT32 SmBase,\r
178	IN VOID *SmiStack,\r
179	IN UINTN StackSize,\r
180	IN UINTN GdtBase,\r
181	IN UINTN GdtSize,\r
182	IN UINTN IdtBase,\r
183	IN UINTN IdtSize,\r
184	IN UINT32 Cr3\r
185	)\r
186	{\r
187	}\r
188	\r
189	/**\r
190	Determines if MTRR registers must be configured to set SMRAM cache-ability\r
191	when executing in System Management Mode.\r
192	\r
193	@retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r
194	@retval FALSE MTRR registers do not need to be configured to set SMRAM\r
195	cache-ability.\r
196	**/\r
197	BOOLEAN\r
198	EFIAPI\r
199	SmmCpuFeaturesNeedConfigureMtrrs (\r
200	VOID\r
201	)\r
202	{\r
203	return TRUE;\r
204	}\r
205	\r
206	/**\r
207	Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
208	returns TRUE.\r
209	**/\r
210	VOID\r
211	EFIAPI\r
212	SmmCpuFeaturesDisableSmrr (\r
213	VOID\r
214	)\r
215	{\r
216	//\r
217	// Use QNC to disable SMRR on Quark\r
218	//\r
219	QNCPortWrite(\r
220	QUARK_NC_HOST_BRIDGE_SB_PORT_ID,\r
221	QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,\r
222	QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) & ~EFI_MSR_SMRR_PHYS_MASK_VALID\r
223	);\r
224	}\r
225	\r
226	/**\r
227	Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
228	returns TRUE.\r
229	**/\r
230	VOID\r
231	EFIAPI\r
232	SmmCpuFeaturesReenableSmrr (\r
233	VOID\r
234	)\r
235	{\r
236	//\r
237	// Use QNC to enable SMRR on Quark\r
238	//\r
239	QNCPortWrite(\r
240	QUARK_NC_HOST_BRIDGE_SB_PORT_ID,\r
241	QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,\r
242	QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) \| EFI_MSR_SMRR_PHYS_MASK_VALID\r
243	);\r
244	}\r
245	\r
246	/**\r
247	Processor specific hook point each time a CPU enters System Management Mode.\r
248	\r
249	@param[in] CpuIndex The index of the CPU that has entered SMM. The value\r
250	must be between 0 and the NumberOfCpus field in the\r
251	System Management System Table (SMST).\r
252	**/\r
253	VOID\r
254	EFIAPI\r
255	SmmCpuFeaturesRendezvousEntry (\r
256	IN UINTN CpuIndex\r
257	)\r
258	{\r
259	}\r
260	\r
261	/**\r
262	Processor specific hook point each time a CPU exits System Management Mode.\r
263	\r
264	@param[in] CpuIndex The index of the CPU that is exiting SMM. The value must\r
265	be between 0 and the NumberOfCpus field in the System\r
266	Management System Table (SMST).\r
267	**/\r
268	VOID\r
269	EFIAPI\r
270	SmmCpuFeaturesRendezvousExit (\r
271	IN UINTN CpuIndex\r
272	)\r
273	{\r
274	}\r
275	\r
276	/**\r
277	Check to see if an SMM register is supported by a specified CPU.\r
278	\r
279	@param[in] CpuIndex The index of the CPU to check for SMM register support.\r
280	The value must be between 0 and the NumberOfCpus field\r
281	in the System Management System Table (SMST).\r
282	@param[in] RegName Identifies the SMM register to check for support.\r
283	\r
284	@retval TRUE The SMM register specified by RegName is supported by the CPU\r
285	specified by CpuIndex.\r
286	@retval FALSE The SMM register specified by RegName is not supported by the\r
287	CPU specified by CpuIndex.\r
288	**/\r
289	BOOLEAN\r
290	EFIAPI\r
291	SmmCpuFeaturesIsSmmRegisterSupported (\r
292	IN UINTN CpuIndex,\r
293	IN SMM_REG_NAME RegName\r
294	)\r
295	{\r
296	return FALSE;\r
297	}\r
298	\r
299	/**\r
300	Returns the current value of the SMM register for the specified CPU.\r
301	If the SMM register is not supported, then 0 is returned.\r
302	\r
303	@param[in] CpuIndex The index of the CPU to read the SMM register. The\r
304	value must be between 0 and the NumberOfCpus field in\r
305	the System Management System Table (SMST).\r
306	@param[in] RegName Identifies the SMM register to read.\r
307	\r
308	@return The value of the SMM register specified by RegName from the CPU\r
309	specified by CpuIndex.\r
310	**/\r
311	UINT64\r
312	EFIAPI\r
313	SmmCpuFeaturesGetSmmRegister (\r
314	IN UINTN CpuIndex,\r
315	IN SMM_REG_NAME RegName\r
316	)\r
317	{\r
318	return 0;\r
319	}\r
320	\r
321	/**\r
322	Sets the value of an SMM register on a specified CPU.\r
323	If the SMM register is not supported, then no action is performed.\r
324	\r
325	@param[in] CpuIndex The index of the CPU to write the SMM register. The\r
326	value must be between 0 and the NumberOfCpus field in\r
327	the System Management System Table (SMST).\r
328	@param[in] RegName Identifies the SMM register to write.\r
329	registers are read-only.\r
330	@param[in] Value The value to write to the SMM register.\r
331	**/\r
332	VOID\r
333	EFIAPI\r
334	SmmCpuFeaturesSetSmmRegister (\r
335	IN UINTN CpuIndex,\r
336	IN SMM_REG_NAME RegName,\r
337	IN UINT64 Value\r
338	)\r
339	{\r
340	}\r
341	\r
342	/**\r
343	Read an SMM Save State register on the target processor. If this function\r
344	returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
345	SMM Save Sate register.\r
346	\r
347	@param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r
348	value must be between 0 and the NumberOfCpus field in\r
349	the System Management System Table (SMST).\r
350	@param[in] Register The SMM Save State register to read.\r
351	@param[in] Width The number of bytes to read from the CPU save state.\r
352	@param[out] Buffer Upon return, this holds the CPU register value read\r
353	from the save state.\r
354	\r
355	@retval EFI_SUCCESS The register was read from Save State.\r
356	@retval EFI_INVALID_PARAMTER Buffer is NULL.\r
357	@retval EFI_UNSUPPORTED This function does not support reading Register.\r
358	\r
359	**/\r
360	EFI_STATUS\r
361	EFIAPI\r
362	SmmCpuFeaturesReadSaveStateRegister (\r
363	IN UINTN CpuIndex,\r
364	IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
365	IN UINTN Width,\r
366	OUT VOID *Buffer\r
367	)\r
368	{\r
369	return EFI_UNSUPPORTED;\r
370	}\r
371	\r
372	/**\r
373	Writes an SMM Save State register on the target processor. If this function\r
374	returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
375	SMM Save Sate register.\r
376	\r
377	@param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r
378	value must be between 0 and the NumberOfCpus field in\r
379	the System Management System Table (SMST).\r
380	@param[in] Register The SMM Save State register to write.\r
381	@param[in] Width The number of bytes to write to the CPU save state.\r
382	@param[in] Buffer Upon entry, this holds the new CPU register value.\r
383	\r
384	@retval EFI_SUCCESS The register was written to Save State.\r
385	@retval EFI_INVALID_PARAMTER Buffer is NULL.\r
386	@retval EFI_UNSUPPORTED This function does not support writing Register.\r
387	**/\r
388	EFI_STATUS\r
389	EFIAPI\r
390	SmmCpuFeaturesWriteSaveStateRegister (\r
391	IN UINTN CpuIndex,\r
392	IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
393	IN UINTN Width,\r
394	IN CONST VOID *Buffer\r
395	)\r
396	{\r
397	return EFI_UNSUPPORTED;\r
398	}\r
399	\r
400	/**\r
401	This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
402	notification is completely processed.\r
403	**/\r
404	VOID\r
405	EFIAPI\r
406	SmmCpuFeaturesCompleteSmmReadyToLock (\r
407	VOID\r
408	)\r
409	{\r
410	}\r
411	\r
412	/**\r
413	This API provides a method for a CPU to allocate a specific region for storing page tables.\r
414	\r
415	This API can be called more once to allocate memory for page tables.\r
416	\r
417	Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
418	allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
419	is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
420	returned.\r
421	\r
422	This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
423	\r
424	@param Pages The number of 4 KB pages to allocate.\r
425	\r
426	@return A pointer to the allocated buffer for page tables.\r
427	@retval NULL Fail to allocate a specific region for storing page tables,\r
428	Or there is no preference on where the page tables are allocated in SMRAM.\r
429	\r
430	**/\r
431	VOID *\r
432	EFIAPI\r
433	SmmCpuFeaturesAllocatePageTableMemory (\r
434	IN UINTN Pages\r
435	)\r
436	{\r
437	return NULL;\r
438	}\r