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QuarkSocPkg/QncSmmDispatcher: Fix context passed to SMI handlers
[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / MemoryInit / Pei / gen5_iosf_sb_definitions.h
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MK		 1/************************************************************************\r
2 *\r
3 * Copyright (c) 2013-2015 Intel Corporation.\r
4 *\r
5* This program and the accompanying materials\r
6* are licensed and made available under the terms and conditions of the BSD License\r
7* which accompanies this distribution. The full text of the license may be found at\r
8* http://opensource.org/licenses/bsd-license.php\r
9*\r
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12 *\r
13 * MCU register definition\r
14 *\r
15 ************************************************************************/\r
16#ifndef __IOSF_DEFINITIONS_H\r
17#define __IOSF_DEFINITIONS_H\r
18\r
19// Define each of the IOSF-SB register offsets used by MRC.\r
20\r
21\r
22// MCU registers (DUNIT):\r
23// ====\r
24#define DRP 0x0000\r
25#define DTR0 0x0001\r
26#define DTR1 0x0002\r
27#define DTR2 0x0003\r
28#define DTR3 0x0004\r
29#define DTR4 0x0005\r
30#define DPMC0 0x0006\r
31#define DPMC1 0x0007\r
32#define DRFC 0x0008\r
33#define DSCH 0x0009\r
34#define DCAL 0x000A\r
35#define DRMC 0x000B\r
36#define PMSTS 0x000C\r
37#define DCO 0x000F\r
38#define DSTAT 0x0020\r
39#define DECCCTRL 0x0060\r
40#define DFUSESTAT 0x0070\r
41#define SCRMSEED 0x0080\r
42#define SCRMLO 0x0081\r
43#define SCRMHI 0x0082\r
44\r
45#define MCU_CH_OFFSET 0x0040\r
46#define MCU_RK_OFFSET 0x0020\r
47\r
48////\r
49//\r
50// BEGIN DUnit register definition\r
51//\r
52#pragma pack(1)\r
53typedef union {\r
54 uint32_t raw;\r
55 struct {\r
56 uint32_t rank0Enabled :1; /**< BIT [0] Rank 0 Enable */\r
57 uint32_t rank1Enabled :1; /**< BIT [1] Rank 1 Enable */\r
58 uint32_t reserved0 :2;\r
59 uint32_t dimm0DevWidth :2; /**< BIT [5:4] DIMM 0 Device Width (Rank0&1) */\r
60 uint32_t dimm0DevDensity :2; /**< BIT [7:6] DIMM 0 Device Density */\r
61 uint32_t reserved1 :1;\r
62 uint32_t dimm1DevWidth :2; /**< BIT [10:9] DIMM 1 Device Width (Rank2&3) */\r
63 uint32_t dimm1DevDensity :2; /**< BIT [12:11] DIMM 1 Device Density */\r
64 uint32_t split64 :1; /**< BIT [13] split 64B transactions */\r
65 uint32_t addressMap :2; /**< BIT [15:14] Address Map select */\r
66 uint32_t reserved3 :14;\r
67 uint32_t mode32 :1; /**< BIT [30] Select 32bit data interface*/\r
68 uint32_t reserved4 :1;\r
69 } field;\r
70} RegDRP; /**< DRAM Rank Population and Interface Register */\r
71#pragma pack()\r
72\r
73\r
74#pragma pack(1)\r
75typedef union {\r
76 uint32_t raw;\r
77 struct {\r
78 uint32_t dramFrequency :2; /**< DRAM Frequency (000=800,001=1033,010=1333) */\r
79 uint32_t reserved1 :2;\r
80 uint32_t tRP :4; /**< bit [7:4] Precharge to Activate Delay */\r
81 uint32_t tRCD :4; /**< bit [11:8] Activate to CAS Delay */\r
82 uint32_t tCL :3; /**< bit [14:12] CAS Latency */\r
83 uint32_t reserved4 :1;\r
84 uint32_t tXS :1; /**< SRX Delay */\r
85 uint32_t reserved5 :1;\r
86 uint32_t tXSDLL :1; /**< SRX To DLL Delay */\r
87 uint32_t reserved6 :1;\r
88 uint32_t tZQCS :1; /**< bit [20] ZQTS recovery Latncy */\r
89 uint32_t reserved7 :1;\r
90 uint32_t tZQCL :1; /**< bit [22] ZQCL recovery Latncy */\r
91 uint32_t reserved8 :1;\r
92 uint32_t pmeDelay :2; /**< bit [25:24] Power mode entry delay */\r
93 uint32_t reserved9 :2;\r
94 uint32_t CKEDLY :4; /**< bit [31:28] */\r
95 } field;\r
96} RegDTR0; /**< DRAM Timing Register 0 */\r
97#pragma pack()\r
98\r
99#pragma pack(1)\r
100typedef union {\r
101 uint32_t raw;\r
102 struct {\r
103 uint32_t tWCL :3; /**< bit [2:0] CAS Write Latency */\r
104 uint32_t reserved1 :1;\r
105 uint32_t tCMD :2; /**< bit [5:4] Command transport duration */\r
106 uint32_t reserved2 :2;\r
107 uint32_t tWTP :4; /**< Write to Precharge */\r
108 uint32_t tCCD :2; /**< CAS to CAS delay */\r
109 uint32_t reserved4 :2;\r
110 uint32_t tFAW :4; /**< Four bank Activation Window*/\r
111 uint32_t tRAS :4; /**< Row Activation Period: */\r
112 uint32_t tRRD :2; /**<Row activation to Row activation Delay */\r
113 uint32_t reserved5 :2;\r
114 uint32_t tRTP :3; /**<Read to Precharge Delay */\r
115 uint32_t reserved6 :1;\r
116 } field;\r
117} RegDTR1; /**< DRAM Timing Register 1 */\r
118#pragma pack()\r
119\r
120#pragma pack(1)\r
121typedef union {\r
122 uint32_t raw;\r
123 struct {\r
124 uint32_t tRRDR :3; /**< RD to RD from different ranks, same DIMM */\r
125 uint32_t reserved1 :5;\r
126 uint32_t tWWDR :3; /**< WR to WR from different ranks, same DIMM. */\r
127 uint32_t reserved3 :5;\r
128 uint32_t tRWDR :4; /**< bit [19:16] RD to WR from different ranks, same DIMM. */\r
129 uint32_t reserved5 :12;\r
130 } field;\r
131} RegDTR2; /**< DRAM Timing Register 2 */\r
132#pragma pack()\r
133\r
134#pragma pack(1)\r
135typedef union {\r
136 uint32_t raw;\r
137 struct {\r
138 uint32_t tWRDR :3; /**< WR to RD from different ranks, same DIMM. */\r
139 uint32_t reserved1 :1;\r
140 uint32_t tWRDD :3; /**< WR to RD from different DIMM. */\r
141 uint32_t reserved2 :1;\r
142 uint32_t tRWSR :4; /**< RD to WR Same Rank. */\r
143 uint32_t reserved3 :1;\r
144 uint32_t tWRSR :4; /**< WR to RD Same Rank. */\r
145 uint32_t reserved4 :5;\r
146 uint32_t tXP :2; /**< Time from CKE set on to any command. */\r
147 uint32_t PWD_DLY :4; /**< Extended Power-Down Delay. */\r
148 uint32_t EnDeRate :1;\r
149 uint32_t DeRateOvr :1;\r
150 uint32_t DeRateStat :1;\r
151 uint32_t reserved5 :1;\r
152 } field;\r
153} RegDTR3; /**< DRAM Timing Register 3 */\r
154#pragma pack()\r
155\r
156\r
157#pragma pack(1)\r
158typedef union {\r
159 uint32_t raw;\r
160 struct {\r
161 uint32_t WRODTSTRT :2; /**< WR command to ODT assert delay */\r
162 uint32_t reserved1 :2;\r
163 uint32_t WRODTSTOP :3; /**< Write command to ODT de-assert delay. */\r
164 uint32_t reserved2 :1;\r
165 uint32_t RDODTSTRT :3; /**< Read command to ODT assert delay */\r
166 uint32_t reserved3 :1;\r
167 uint32_t RDODTSTOP :3; /**< Read command to ODT de-assert delay */\r
168 uint32_t ODTDIS :1; /**< ODT disable */\r
169 uint32_t TRGSTRDIS :1; /**< Write target rank is not stretched */\r
170 uint32_t RDODTDIS :1; /**< Disable Read ODT */\r
171 uint32_t WRBODTDIS :1; /**< Disable Write ODT */\r
172 uint32_t reserved5 :13;\r
173 } field;\r
174} RegDTR4; /**< DRAM Timing Register 3 */\r
175#pragma pack()\r
176\r
177#pragma pack(1)\r
178typedef union {\r
179 uint32_t raw;\r
180 struct {\r
181 uint32_t SREntryDelay :8; /**< Self-Refresh Entry Delay: */\r
182 uint32_t powerModeOpCode :5; /**< SPID Power Mode Opcode */\r
183 uint32_t reserved1 :3;\r
184 uint32_t PCLSTO :3; /**< Page Close Timeout Period */\r
185 uint32_t reserved2 :1;\r
186 uint32_t PCLSWKOK :1; /**< Wake Allowed For Page Close Timeout */\r
187 uint32_t PREAPWDEN :1; /**< Send Precharge All to rank before entering Power-Down mode. */\r
188 uint32_t reserved3 :1;\r
189 uint32_t DYNSREN :1; /**< Dynamic Self-Refresh */\r
190 uint32_t CLKGTDIS :1; /**< Clock Gating Disabled*/\r
191 uint32_t DISPWRDN :1; /**< Disable Power Down*/\r
192 uint32_t reserved4 :2;\r
193 uint32_t REUTCLKGTDIS :1;\r
194 uint32_t ENPHYCLKGATE :1;\r
195 uint32_t reserved5 :2;\r
196 } field;\r
197} RegDPMC0; /**< DRAM Power Management Control Register 0 */\r
198#pragma pack()\r
199\r
200#pragma pack(1)\r
201typedef union {\r
202 uint32_t raw;\r
203 struct {\r
204 uint32_t REFWMLO :4; /**< Refresh Opportunistic Watermark */\r
205 uint32_t REFWMHI :4; /**< Refresh High Watermark*/\r
206 uint32_t REFWMPNC :4; /**< Refresh Panic Watermark */\r
207 uint32_t tREFI :3; /**< bit [14:12] Refresh Period */\r
208 uint32_t reserved1 :1;\r
209 uint32_t REFCNTMAX :2; /**< Refresh Max tREFI Interval */\r
210 uint32_t reserved2 :2;\r
211 uint32_t REFSKEWDIS :1; /**< tREFI counters */\r
212 uint32_t REFDBTCLR :1;\r
213 uint32_t reserved3 :2;\r
214 uint32_t CuRefRate :3;\r
215 uint32_t DisRefBW :1;\r
216 uint32_t reserved4 :4;\r
217 } field;\r
218} RegDRCF; /**< DRAM Refresh Control Register*/\r
219#pragma pack()\r
220\r
221#pragma pack(1)\r
222typedef union {\r
223 uint32_t raw;\r
224 struct {\r
225 uint32_t reserved1 :8;\r
226 uint32_t ZQCINT :3; /**< ZQ Calibration Short Interval: */\r
227 uint32_t reserved2 :1;\r
228 uint32_t SRXZQCL :2; /** < ZQ Calibration Length */\r
229 uint32_t ZQCalType :1;\r
230 uint32_t ZQCalStart :1;\r
231 uint32_t TQPollStart :1;\r
232 uint32_t TQPollRS :2;\r
233 uint32_t reserved3 :5;\r
234 uint32_t MRRData :8; /**< bit[31:24] */\r
235 } field;\r
236} RegDCAL; /**< DRAM Calibration Control*/\r
237#pragma pack()\r
238\r
239#pragma pack(1)\r
240typedef union {\r
241 uint32_t raw;\r
242 struct {\r
243 uint32_t OOOAGETRH :5; /**< Out-of-Order Aging Threshold */\r
244 uint32_t reserved1 :3;\r
245 uint32_t OOODIS :1; /**< Out-of-Order Disable */\r
246 uint32_t OOOST3DIS :1; /**< Out-of-Order Disabled when RequestBD_Status is 3. */\r
247 uint32_t reserved2 :2;\r
248 uint32_t NEWBYPDIS :1;\r
249 uint32_t reserved3 :3;\r
250 uint32_t IPREQMAX :3; /** < Max In-Progress Requests stored in MC */\r
251 uint32_t reserved4 :13;\r
252 } field;\r
253} RegDSCH; /**< DRAM Scheduler Control Register */\r
254#pragma pack()\r
255\r
256#pragma pack(1)\r
257typedef union {\r
258 uint32_t raw;\r
259 struct {\r
260 uint32_t DRPLOCK :1; /**< DRP lock bit */\r
261 uint32_t reserved1 :7;\r
262 uint32_t REUTLOCK :1; /**< REUT lock bit */\r
263 uint32_t reserved2 :19;\r
264 uint32_t PMICTL :1; /**< PRI Control Select: 0-memory_manager, 1-hte */\r
265 uint32_t PMIDIS :1; /**< PMIDIS Should be set is using IOSF-SB RW */\r
266 uint32_t DIOIC :1; /**< DDRIO initialization is complete */\r
267 uint32_t IC :1; /**< D-unit Initialization Complete */\r
268 } field;\r
269} RegDCO; /**< DRAM Controller Operation Register*/\r
270#pragma pack()\r
271\r
272#pragma pack(1)\r
273typedef union {\r
274 uint32_t raw;\r
275 struct {\r
276 uint32_t SBEEN :1; /**< Enable Single Bit Error Detection and Correction */\r
277 uint32_t DBEEN :1; /**< Enable Double Bit Error Detection */\r
278 uint32_t CBOEN :3; /**< Enable ECC Check Bits Override */\r
279 uint32_t SYNSEL :2; /**< ECC Syndrome Bits Select for Observation */\r
280 uint32_t CLRSBECNT :1; /**< Clear ECC Single Bit Error Count */\r
281 uint32_t CBOV :8; /**< ECC Check Bits Override Value */\r
282 uint32_t reserved1 :1; /**< */\r
283 uint32_t ENCBGEN :1; /**< Enable Generation of ECC Check Bits */\r
284 uint32_t ENCBGESWIZ :1; /**< Enable Same Chip ECC Byte Lane Swizzle */\r
285\r
286 } field;\r
287} RegDECCCTRL; /**< DRAM ECC Control Register */\r
288#pragma pack()\r
289\r
290\r
291#pragma pack(1)\r
292typedef union {\r
293 uint32_t raw;\r
294 struct {\r
295 uint32_t FUS_DUN_ECC_DIS :1;\r
296 uint32_t FUS_DUN_MAX_SUPPORTED_MEMORY :3;\r
297 uint32_t FUS_DUN_MAX_DEVDEN :2;\r
298 uint32_t RESERVED1 :1;\r
299 uint32_t FUS_DUN_RANK2_DIS :1;\r
300 uint32_t FUS_DUN_OOO_DIS :1;\r
301 uint32_t FUS_DUN_MEMX8_DIS :1;\r
302 uint32_t FUS_DUN_MEMX16_DIS :1;\r
303 uint32_t RESERVED2 :1;\r
304 uint32_t FUS_DUN_1N_DIS :1;\r
305 uint32_t FUS_DUN_DQ_SCRAMBLER_DIS :1;\r
306 uint32_t RESERVED3 :1;\r
307 uint32_t FUS_DUN_32BIT_DRAM_IFC :1;\r
308 } field;\r
309} RegDFUSESTAT;\r
310#pragma pack()\r
311\r
312//\r
313// END DUnit register definition\r
314//\r
315////\r
316\r
317\r
318\r
319////\r
320//\r
321// DRAM Initialization Structures used in JEDEC Message Bus Commands\r
322//\r
323\r
324#pragma pack(1)\r
325typedef union {\r
326 uint32_t raw;\r
327 struct {\r
328 unsigned command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */\r
329 unsigned bankAddress :3; /**< Bank Address (BA[2:0]) */\r
330 unsigned BL :2; /**< Burst Length, CDV:1*/\r
331 unsigned CL :1; /**< CL Reserved CDV:0 */\r
332 unsigned RBT :1; /**< Read Burst Type */\r
333 unsigned casLatency :3; /**< cas Latency */\r
334 unsigned TM :1; /**< Test mode */\r
335 unsigned dllReset :1; /**< DLL Reset */\r
336 unsigned writeRecovery :3; /**< Write Recovery for Auto Pre-Charge: 001=2,010=3,011=4,100=5,101=6 */\r
337 unsigned PPD :1; /**< DLL Control for Precharge Power-Down CDV:1 */\r
338 unsigned reserved1 :3;\r
339 unsigned rankSelect :4; /**< Rank Select */\r
340 unsigned reserved2 :6;\r
341 } field;\r
342} DramInitDDR3MRS0; /**< DDR3 Mode Register Set (MRS) Command */\r
343#pragma pack()\r
344\r
345#pragma pack(1)\r
346typedef union {\r
347 uint32_t raw;\r
348 struct {\r
349 unsigned command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */\r
350 unsigned bankAddress :3; /**< Bank Address (BA[2:0]) */\r
351 unsigned dllEnabled :1; /**< CDV=0 */\r
352 unsigned DIC0 :1; /**< Output Driver Impedance Control */\r
353 unsigned rttNom0 :1; /**< RTT_nom[0] */\r
354 unsigned MRC_AL :2; /**< Additive Latency = 0 */\r
355 unsigned DIC1 :1; /**< Reserved */\r
356 unsigned rttNom1 :1; /**< RTT_nom[1] */\r
357 unsigned wlEnabled :1; /**< Write Leveling Enable */\r
358 unsigned reserved1 :1;\r
359 unsigned rttNom2 :1; /** < RTT_nom[2] */\r
360 unsigned reserved2 :1;\r
361 unsigned TDQS :1; /**< TDQS Enable */\r
362 unsigned Qoff :1; /**< Output Buffers Disabled */\r
363 unsigned reserved3 :3;\r
364 unsigned rankSelect :4; /**< Rank Select */\r
365 unsigned reserved4 :6;\r
366 } field;\r
367} DramInitDDR3EMR1; /**< DDR3 Extended Mode Register 1 Set (EMRS1) Command */\r
368#pragma pack()\r
369\r
370#pragma pack(1)\r
371typedef union {\r
372 uint32_t raw;\r
373 struct {\r
374 uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */\r
375 uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */\r
376 uint32_t PASR :3; /**< Partial Array Self-Refresh */\r
377 uint32_t CWL :3; /**< CAS Write Latency */\r
378 uint32_t ASR :1; /**< Auto Self-Refresh */\r
379 uint32_t SRT :1; /**< SR Temperature Range = 0*/\r
380 uint32_t reserved1 :1;\r
381 uint32_t rtt_WR :2; /**< Rtt_WR */\r
382 uint32_t reserved2 :5;\r
383 uint32_t rankSelect :4; /**< Rank Select */\r
384 uint32_t reserved3 :6;\r
385 } field;\r
386} DramInitDDR3EMR2; /**< DDR3 Extended Mode Register 2 Set (EMRS2) Command */\r
387#pragma pack()\r
388\r
389#pragma pack(1)\r
390typedef union {\r
391 uint32_t raw;\r
392 struct {\r
393 uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */\r
394 uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */\r
395 uint32_t MPR_Location :2; /**< MPR Location */\r
396 uint32_t MPR :1; /**< MPR: Multi Purpose Register */\r
397 uint32_t reserved1 :13;\r
398 uint32_t rankSelect :4; /**< Rank Select */\r
399 uint32_t reserved2 :6;\r
400 } field;\r
401} DramInitDDR3EMR3; /**< DDR3 Extended Mode Register 2 Set (EMRS2) Command */\r
402#pragma pack()\r
403\r
404#pragma pack(1)\r
405typedef union {\r
406 uint32_t raw;\r
407 struct {\r
408 uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110 - ZQ Calibration,111-NOP */\r
409 uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */\r
410 uint32_t multAddress :16; /**< Multiplexed Address (MA[14:0]) */\r
411 uint32_t rankSelect :2; /**< Rank Select */\r
412 uint32_t reserved3 :8;\r
413 } field;\r
414} DramInitMisc; /**< Miscellaneous DDRx Initialization Command */\r
415#pragma pack()\r
416\r
417//\r
418// Construct DRAM init command using DramInitXxxx pattern\r
419//\r
420#define DCMD_MRS1(rnk,dat) (0 | ((rnk)<<22) | (1<<3) | ((dat)<<6))\r
421#define DCMD_REF(rnk) (1 | ((rnk)<<22))\r
422#define DCMD_PRE(rnk) (2 | ((rnk)<<22))\r
423#define DCMD_PREA(rnk) (2 | ((rnk)<<22) | (BIT10<<6))\r
424#define DCMD_ACT(rnk,row) (3 | ((rnk)<<22) | ((row)<<6))\r
425#define DCMD_WR(rnk,col) (4 | ((rnk)<<22) | ((col)<<6))\r
426#define DCMD_RD(rnk,col) (5 | ((rnk)<<22) | ((col)<<6))\r
427#define DCMD_ZQCS(rnk) (6 | ((rnk)<<22))\r
428#define DCMD_ZQCL(rnk) (6 | ((rnk)<<22) | (BIT10<<6))\r
429#define DCMD_NOP(rnk) (7 | ((rnk)<<22))\r
430\r
431\r
432\r
433\r
434#define DDR3_EMRS1_DIC_40 (0)\r
435#define DDR3_EMRS1_DIC_34 (1)\r
436\r
437#define DDR3_EMRS2_RTTWR_60 (BIT9)\r
438#define DDR3_EMRS2_RTTWR_120 (BIT10)\r
439\r
440#define DDR3_EMRS1_RTTNOM_0 (0)\r
441#define DDR3_EMRS1_RTTNOM_60 (BIT2)\r
442#define DDR3_EMRS1_RTTNOM_120 (BIT6)\r
443#define DDR3_EMRS1_RTTNOM_40 (BIT6|BIT2)\r
444#define DDR3_EMRS1_RTTNOM_20 (BIT9)\r
445#define DDR3_EMRS1_RTTNOM_30 (BIT9|BIT2)\r
446\r
447\r
448//\r
449// END DRAM Init...\r
450//\r
451////\r
452\r
453\r
454// HOST_BRIDGE registers:\r
455#define HMBOUND 0x0020 //ok\r
456\r
457// MEMORY_MANAGER registers:\r
458#define BCTRL 0x0004\r
459#define BWFLUSH 0x0008\r
460#define BDEBUG1 0x00C4\r
461\r
462////\r
463//\r
464// BEGIN DDRIO registers\r
465//\r
466\r
467// DDR IOs & COMPs:\r
468#define DDRIODQ_BL_OFFSET 0x0800\r
469#define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES/2) * DDRIODQ_BL_OFFSET)\r
470#define DDRIOCCC_CH_OFFSET 0x0800\r
471#define DDRCOMP_CH_OFFSET 0x0100\r
472\r
473// CH0-BL01-DQ\r
474#define DQOBSCKEBBCTL 0x0000\r
475#define DQDLLTXCTL 0x0004\r
476#define DQDLLRXCTL 0x0008\r
477#define DQMDLLCTL 0x000C\r
478#define B0RXIOBUFCTL 0x0010\r
479#define B0VREFCTL 0x0014\r
480#define B0RXOFFSET1 0x0018\r
481#define B0RXOFFSET0 0x001C\r
482#define B1RXIOBUFCTL 0x0020\r
483#define B1VREFCTL 0x0024\r
484#define B1RXOFFSET1 0x0028\r
485#define B1RXOFFSET0 0x002C\r
486#define DQDFTCTL 0x0030\r
487#define DQTRAINSTS 0x0034\r
488#define B1DLLPICODER0 0x0038\r
489#define B0DLLPICODER0 0x003C\r
490#define B1DLLPICODER1 0x0040\r
491#define B0DLLPICODER1 0x0044\r
492#define B1DLLPICODER2 0x0048\r
493#define B0DLLPICODER2 0x004C\r
494#define B1DLLPICODER3 0x0050\r
495#define B0DLLPICODER3 0x0054\r
496#define B1RXDQSPICODE 0x0058\r
497#define B0RXDQSPICODE 0x005C\r
498#define B1RXDQPICODER32 0x0060\r
499#define B1RXDQPICODER10 0x0064\r
500#define B0RXDQPICODER32 0x0068\r
501#define B0RXDQPICODER10 0x006C\r
502#define B01PTRCTL0 0x0070\r
503#define B01PTRCTL1 0x0074\r
504#define B01DBCTL0 0x0078\r
505#define B01DBCTL1 0x007C\r
506#define B0LATCTL0 0x0080\r
507#define B1LATCTL0 0x0084\r
508#define B01LATCTL1 0x0088\r
509#define B0ONDURCTL 0x008C\r
510#define B1ONDURCTL 0x0090\r
511#define B0OVRCTL 0x0094\r
512#define B1OVRCTL 0x0098\r
513#define DQCTL 0x009C\r
514#define B0RK2RKCHGPTRCTRL 0x00A0\r
515#define B1RK2RKCHGPTRCTRL 0x00A4\r
516#define DQRK2RKCTL 0x00A8\r
517#define DQRK2RKPTRCTL 0x00AC\r
518#define B0RK2RKLAT 0x00B0\r
519#define B1RK2RKLAT 0x00B4\r
520#define DQCLKALIGNREG0 0x00B8\r
521#define DQCLKALIGNREG1 0x00BC\r
522#define DQCLKALIGNREG2 0x00C0\r
523#define DQCLKALIGNSTS0 0x00C4\r
524#define DQCLKALIGNSTS1 0x00C8\r
525#define DQCLKGATE 0x00CC\r
526#define B0COMPSLV1 0x00D0\r
527#define B1COMPSLV1 0x00D4\r
528#define B0COMPSLV2 0x00D8\r
529#define B1COMPSLV2 0x00DC\r
530#define B0COMPSLV3 0x00E0\r
531#define B1COMPSLV3 0x00E4\r
532#define DQVISALANECR0TOP 0x00E8\r
533#define DQVISALANECR1TOP 0x00EC\r
534#define DQVISACONTROLCRTOP 0x00F0\r
535#define DQVISALANECR0BL 0x00F4\r
536#define DQVISALANECR1BL 0x00F8\r
537#define DQVISACONTROLCRBL 0x00FC\r
538#define DQTIMINGCTRL 0x010C\r
539// CH0-ECC\r
540#define ECCDLLTXCTL 0x2004\r
541#define ECCDLLRXCTL 0x2008\r
542#define ECCMDLLCTL 0x200C\r
543#define ECCB1DLLPICODER0 0x2038\r
544#define ECCB1DLLPICODER1 0x2040\r
545#define ECCB1DLLPICODER2 0x2048\r
546#define ECCB1DLLPICODER3 0x2050\r
547#define ECCB01DBCTL0 0x2078\r
548#define ECCB01DBCTL1 0x207C\r
549#define ECCCLKALIGNREG0 0x20B8\r
550#define ECCCLKALIGNREG1 0x20BC\r
551#define ECCCLKALIGNREG2 0x20C0\r
552// CH0-CMD\r
553#define CMDOBSCKEBBCTL 0x4800\r
554#define CMDDLLTXCTL 0x4808\r
555#define CMDDLLRXCTL 0x480C\r
556#define CMDMDLLCTL 0x4810\r
557#define CMDRCOMPODT 0x4814\r
558#define CMDDLLPICODER0 0x4820\r
559#define CMDDLLPICODER1 0x4824\r
560#define CMDCFGREG0 0x4840\r
561#define CMDPTRREG 0x4844\r
562#define CMDCLKALIGNREG0 0x4850\r
563#define CMDCLKALIGNREG1 0x4854\r
564#define CMDCLKALIGNREG2 0x4858\r
565#define CMDPMCONFIG0 0x485C\r
566#define CMDPMDLYREG0 0x4860\r
567#define CMDPMDLYREG1 0x4864\r
568#define CMDPMDLYREG2 0x4868\r
569#define CMDPMDLYREG3 0x486C\r
570#define CMDPMDLYREG4 0x4870\r
571#define CMDCLKALIGNSTS0 0x4874\r
572#define CMDCLKALIGNSTS1 0x4878\r
573#define CMDPMSTS0 0x487C\r
574#define CMDPMSTS1 0x4880\r
575#define CMDCOMPSLV 0x4884\r
576#define CMDBONUS0 0x488C\r
577#define CMDBONUS1 0x4890\r
578#define CMDVISALANECR0 0x4894\r
579#define CMDVISALANECR1 0x4898\r
580#define CMDVISACONTROLCR 0x489C\r
581#define CMDCLKGATE 0x48A0\r
582#define CMDTIMINGCTRL 0x48A4\r
583// CH0-CLK-CTL\r
584#define CCOBSCKEBBCTL 0x5800\r
585#define CCRCOMPIO 0x5804\r
586#define CCDLLTXCTL 0x5808\r
587#define CCDLLRXCTL 0x580C\r
588#define CCMDLLCTL 0x5810\r
589#define CCRCOMPODT 0x5814\r
590#define CCDLLPICODER0 0x5820\r
591#define CCDLLPICODER1 0x5824\r
592#define CCDDR3RESETCTL 0x5830\r
593#define CCCFGREG0 0x5838\r
594#define CCCFGREG1 0x5840\r
595#define CCPTRREG 0x5844\r
596#define CCCLKALIGNREG0 0x5850\r
597#define CCCLKALIGNREG1 0x5854\r
598#define CCCLKALIGNREG2 0x5858\r
599#define CCPMCONFIG0 0x585C\r
600#define CCPMDLYREG0 0x5860\r
601#define CCPMDLYREG1 0x5864\r
602#define CCPMDLYREG2 0x5868\r
603#define CCPMDLYREG3 0x586C\r
604#define CCPMDLYREG4 0x5870\r
605#define CCCLKALIGNSTS0 0x5874\r
606#define CCCLKALIGNSTS1 0x5878\r
607#define CCPMSTS0 0x587C\r
608#define CCPMSTS1 0x5880\r
609#define CCCOMPSLV1 0x5884\r
610#define CCCOMPSLV2 0x5888\r
611#define CCCOMPSLV3 0x588C\r
612#define CCBONUS0 0x5894\r
613#define CCBONUS1 0x5898\r
614#define CCVISALANECR0 0x589C\r
615#define CCVISALANECR1 0x58A0\r
616#define CCVISACONTROLCR 0x58A4\r
617#define CCCLKGATE 0x58A8\r
618#define CCTIMINGCTL 0x58AC\r
619// COMP\r
620#define CMPCTRL 0x6800\r
621#define SOFTRSTCNTL 0x6804\r
622#define MSCNTR 0x6808\r
623#define NMSCNTRL 0x680C\r
624#define LATCH1CTL 0x6814\r
625#define COMPVISALANECR0 0x681C\r
626#define COMPVISALANECR1 0x6820\r
627#define COMPVISACONTROLCR 0x6824\r
628#define COMPBONUS0 0x6830\r
629#define TCOCNTCTRL 0x683C\r
630#define DQANAODTPUCTL 0x6840\r
631#define DQANAODTPDCTL 0x6844\r
632#define DQANADRVPUCTL 0x6848\r
633#define DQANADRVPDCTL 0x684C\r
634#define DQANADLYPUCTL 0x6850\r
635#define DQANADLYPDCTL 0x6854\r
636#define DQANATCOPUCTL 0x6858\r
637#define DQANATCOPDCTL 0x685C\r
638#define CMDANADRVPUCTL 0x6868\r
639#define CMDANADRVPDCTL 0x686C\r
640#define CMDANADLYPUCTL 0x6870\r
641#define CMDANADLYPDCTL 0x6874\r
642#define CLKANAODTPUCTL 0x6880\r
643#define CLKANAODTPDCTL 0x6884\r
644#define CLKANADRVPUCTL 0x6888\r
645#define CLKANADRVPDCTL 0x688C\r
646#define CLKANADLYPUCTL 0x6890\r
647#define CLKANADLYPDCTL 0x6894\r
648#define CLKANATCOPUCTL 0x6898\r
649#define CLKANATCOPDCTL 0x689C\r
650#define DQSANAODTPUCTL 0x68A0\r
651#define DQSANAODTPDCTL 0x68A4\r
652#define DQSANADRVPUCTL 0x68A8\r
653#define DQSANADRVPDCTL 0x68AC\r
654#define DQSANADLYPUCTL 0x68B0\r
655#define DQSANADLYPDCTL 0x68B4\r
656#define DQSANATCOPUCTL 0x68B8\r
657#define DQSANATCOPDCTL 0x68BC\r
658#define CTLANADRVPUCTL 0x68C8\r
659#define CTLANADRVPDCTL 0x68CC\r
660#define CTLANADLYPUCTL 0x68D0\r
661#define CTLANADLYPDCTL 0x68D4\r
662#define CHNLBUFSTATIC 0x68F0\r
663#define COMPOBSCNTRL 0x68F4\r
664#define COMPBUFFDBG0 0x68F8\r
665#define COMPBUFFDBG1 0x68FC\r
666#define CFGMISCCH0 0x6900\r
667#define COMPEN0CH0 0x6904\r
668#define COMPEN1CH0 0x6908\r
669#define COMPEN2CH0 0x690C\r
670#define STATLEGEN0CH0 0x6910\r
671#define STATLEGEN1CH0 0x6914\r
672#define DQVREFCH0 0x6918\r
673#define CMDVREFCH0 0x691C\r
674#define CLKVREFCH0 0x6920\r
675#define DQSVREFCH0 0x6924\r
676#define CTLVREFCH0 0x6928\r
677#define TCOVREFCH0 0x692C\r
678#define DLYSELCH0 0x6930\r
679#define TCODRAMBUFODTCH0 0x6934\r
680#define CCBUFODTCH0 0x6938\r
681#define RXOFFSETCH0 0x693C\r
682#define DQODTPUCTLCH0 0x6940\r
683#define DQODTPDCTLCH0 0x6944\r
684#define DQDRVPUCTLCH0 0x6948\r
685#define DQDRVPDCTLCH0 0x694C\r
686#define DQDLYPUCTLCH0 0x6950\r
687#define DQDLYPDCTLCH0 0x6954\r
688#define DQTCOPUCTLCH0 0x6958\r
689#define DQTCOPDCTLCH0 0x695C\r
690#define CMDDRVPUCTLCH0 0x6968\r
691#define CMDDRVPDCTLCH0 0x696C\r
692#define CMDDLYPUCTLCH0 0x6970\r
693#define CMDDLYPDCTLCH0 0x6974\r
694#define CLKODTPUCTLCH0 0x6980\r
695#define CLKODTPDCTLCH0 0x6984\r
696#define CLKDRVPUCTLCH0 0x6988\r
697#define CLKDRVPDCTLCH0 0x698C\r
698#define CLKDLYPUCTLCH0 0x6990\r
699#define CLKDLYPDCTLCH0 0x6994\r
700#define CLKTCOPUCTLCH0 0x6998\r
701#define CLKTCOPDCTLCH0 0x699C\r
702#define DQSODTPUCTLCH0 0x69A0\r
703#define DQSODTPDCTLCH0 0x69A4\r
704#define DQSDRVPUCTLCH0 0x69A8\r
705#define DQSDRVPDCTLCH0 0x69AC\r
706#define DQSDLYPUCTLCH0 0x69B0\r
707#define DQSDLYPDCTLCH0 0x69B4\r
708#define DQSTCOPUCTLCH0 0x69B8\r
709#define DQSTCOPDCTLCH0 0x69BC\r
710#define CTLDRVPUCTLCH0 0x69C8\r
711#define CTLDRVPDCTLCH0 0x69CC\r
712#define CTLDLYPUCTLCH0 0x69D0\r
713#define CTLDLYPDCTLCH0 0x69D4\r
714#define FNLUPDTCTLCH0 0x69F0\r
715// PLL\r
716#define MPLLCTRL0 0x7800\r
717#define MPLLCTRL1 0x7808\r
718#define MPLLCSR0 0x7810\r
719#define MPLLCSR1 0x7814\r
720#define MPLLCSR2 0x7820\r
721#define MPLLDFT 0x7828\r
722#define MPLLMON0CTL 0x7830\r
723#define MPLLMON1CTL 0x7838\r
724#define MPLLMON2CTL 0x783C\r
725#define SFRTRIM 0x7850\r
726#define MPLLDFTOUT0 0x7858\r
727#define MPLLDFTOUT1 0x785C\r
728#define MASTERRSTN 0x7880\r
729#define PLLLOCKDEL 0x7884\r
730#define SFRDEL 0x7888\r
731#define CRUVISALANECR0 0x78F0\r
732#define CRUVISALANECR1 0x78F4\r
733#define CRUVISACONTROLCR 0x78F8\r
734#define IOSFVISALANECR0 0x78FC\r
735#define IOSFVISALANECR1 0x7900\r
736#define IOSFVISACONTROLCR 0x7904\r
737\r
738//\r
739// END DDRIO registers\r
740//\r
741////\r
742\r
743\r
744#endif\r
EFI Development Kit II mirror for PVE