]>
Commit | Line | Data |
---|---|---|
9b6bbcdb MK |
1 | /** @file\r |
2 | The interface layer for memory controller access.\r | |
3 | It is supporting both real hardware platform and simulation environment.\r | |
4 | \r | |
5 | Copyright (c) 2013-2015 Intel Corporation.\r | |
6 | \r | |
c9f231d0 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
9b6bbcdb MK |
8 | \r |
9 | **/\r | |
10 | #include "mrc.h"\r | |
11 | #include "memory_options.h"\r | |
12 | #include "meminit_utils.h"\r | |
13 | #include "io.h"\r | |
14 | \r | |
15 | #ifdef SIM\r | |
16 | \r | |
17 | void SimMmio32Write (\r | |
18 | uint32_t be,\r | |
19 | uint32_t address,\r | |
20 | uint32_t data );\r | |
21 | \r | |
22 | void SimMmio32Read (\r | |
23 | uint32_t be,\r | |
24 | uint32_t address,\r | |
25 | uint32_t *data );\r | |
26 | \r | |
27 | void SimDelayClk (\r | |
28 | uint32_t x2clk );\r | |
29 | \r | |
30 | // This is a simple delay function.\r | |
31 | // It takes "nanoseconds" as a parameter.\r | |
32 | void delay_n(uint32_t nanoseconds)\r | |
33 | {\r | |
34 | SimDelayClk( 800*nanoseconds/1000);\r | |
35 | }\r | |
36 | #endif\r | |
37 | \r | |
38 | /****\r | |
39 | *\r | |
40 | ***/\r | |
41 | uint32_t Rd32(\r | |
42 | uint32_t unit,\r | |
43 | uint32_t addr)\r | |
44 | {\r | |
45 | uint32_t data;\r | |
46 | \r | |
47 | switch (unit)\r | |
48 | {\r | |
49 | case MEM:\r | |
50 | case MMIO:\r | |
51 | #ifdef SIM\r | |
52 | SimMmio32Read( 1, addr, &data);\r | |
53 | #else\r | |
54 | data = *PTR32(addr);\r | |
55 | #endif\r | |
56 | break;\r | |
57 | \r | |
58 | case MCU:\r | |
59 | case HOST_BRIDGE:\r | |
60 | case MEMORY_MANAGER:\r | |
61 | case HTE:\r | |
62 | // Handle case addr bigger than 8bit\r | |
63 | pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);\r | |
64 | addr &= 0x00FF;\r | |
65 | \r | |
66 | pciwrite32(0, 0, 0, SB_PACKET_REG,\r | |
67 | SB_COMMAND(SB_REG_READ_OPCODE, unit, addr));\r | |
68 | data = pciread32(0, 0, 0, SB_DATA_REG);\r | |
69 | break;\r | |
70 | \r | |
71 | case DDRPHY:\r | |
72 | // Handle case addr bigger than 8bit\r | |
73 | pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);\r | |
74 | addr &= 0x00FF;\r | |
75 | \r | |
76 | pciwrite32(0, 0, 0, SB_PACKET_REG,\r | |
77 | SB_COMMAND(SB_DDRIO_REG_READ_OPCODE, unit, addr));\r | |
78 | data = pciread32(0, 0, 0, SB_DATA_REG);\r | |
79 | break;\r | |
80 | \r | |
81 | default:\r | |
82 | DEAD_LOOP()\r | |
83 | ;\r | |
84 | }\r | |
85 | \r | |
86 | if (unit < MEM)\r | |
87 | DPF(D_REGRD, "RD32 %03X %08X %08X\n", unit, addr, data);\r | |
88 | \r | |
89 | return data;\r | |
90 | }\r | |
91 | \r | |
92 | /****\r | |
93 | *\r | |
94 | ***/\r | |
95 | void Wr32(\r | |
96 | uint32_t unit,\r | |
97 | uint32_t addr,\r | |
98 | uint32_t data)\r | |
99 | {\r | |
100 | if (unit < MEM)\r | |
101 | DPF(D_REGWR, "WR32 %03X %08X %08X\n", unit, addr, data);\r | |
102 | \r | |
103 | switch (unit)\r | |
104 | {\r | |
105 | case MEM:\r | |
106 | case MMIO:\r | |
107 | #ifdef SIM\r | |
108 | SimMmio32Write( 1, addr, data);\r | |
109 | #else\r | |
110 | *PTR32(addr) = data;\r | |
111 | #endif\r | |
112 | break;\r | |
113 | \r | |
114 | case MCU:\r | |
115 | case HOST_BRIDGE:\r | |
116 | case MEMORY_MANAGER:\r | |
117 | case HTE:\r | |
118 | // Handle case addr bigger than 8bit\r | |
119 | pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);\r | |
120 | addr &= 0x00FF;\r | |
121 | \r | |
122 | pciwrite32(0, 0, 0, SB_DATA_REG, data);\r | |
123 | pciwrite32(0, 0, 0, SB_PACKET_REG,\r | |
124 | SB_COMMAND(SB_REG_WRITE_OPCODE, unit, addr));\r | |
125 | break;\r | |
126 | \r | |
127 | case DDRPHY:\r | |
128 | // Handle case addr bigger than 8bit\r | |
129 | pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);\r | |
130 | addr &= 0x00FF;\r | |
131 | \r | |
132 | pciwrite32(0, 0, 0, SB_DATA_REG, data);\r | |
133 | pciwrite32(0, 0, 0, SB_PACKET_REG,\r | |
134 | SB_COMMAND(SB_DDRIO_REG_WRITE_OPCODE, unit, addr));\r | |
135 | break;\r | |
136 | \r | |
137 | case DCMD:\r | |
138 | pciwrite32(0, 0, 0, SB_HADR_REG, 0);\r | |
139 | pciwrite32(0, 0, 0, SB_DATA_REG, data);\r | |
140 | pciwrite32(0, 0, 0, SB_PACKET_REG,\r | |
141 | SB_COMMAND(SB_DRAM_CMND_OPCODE, MCU, 0));\r | |
142 | break;\r | |
143 | \r | |
144 | default:\r | |
145 | DEAD_LOOP()\r | |
146 | ;\r | |
147 | }\r | |
148 | }\r | |
149 | \r | |
150 | /****\r | |
151 | *\r | |
152 | ***/\r | |
153 | void WrMask32(\r | |
154 | uint32_t unit,\r | |
155 | uint32_t addr,\r | |
156 | uint32_t data,\r | |
157 | uint32_t mask)\r | |
158 | {\r | |
159 | Wr32(unit, addr, ((Rd32(unit, addr) & ~mask) | (data & mask)));\r | |
160 | }\r | |
161 | \r | |
162 | /****\r | |
163 | *\r | |
164 | ***/\r | |
165 | void pciwrite32(\r | |
166 | uint32_t bus,\r | |
167 | uint32_t dev,\r | |
168 | uint32_t fn,\r | |
169 | uint32_t reg,\r | |
170 | uint32_t data)\r | |
171 | {\r | |
172 | Wr32(MMIO, PCIADDR(bus,dev,fn,reg), data);\r | |
173 | }\r | |
174 | \r | |
175 | /****\r | |
176 | *\r | |
177 | ***/\r | |
178 | uint32_t pciread32(\r | |
179 | uint32_t bus,\r | |
180 | uint32_t dev,\r | |
181 | uint32_t fn,\r | |
182 | uint32_t reg)\r | |
183 | {\r | |
184 | return Rd32(MMIO, PCIADDR(bus,dev,fn,reg));\r | |
185 | }\r | |
186 | \r |