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1 | /** @file\r |
2 | File to contain all the hardware specific stuff for the Smm Sx dispatch protocol.\r | |
3 | \r | |
4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
5 | \r | |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | //\r | |
18 | // Include common header file for this module.\r | |
19 | //\r | |
20 | #include "CommonHeader.h"\r | |
21 | \r | |
22 | #include "QNCSmmHelpers.h"\r | |
23 | \r | |
24 | CONST QNC_SMM_SOURCE_DESC SX_SOURCE_DESC = {\r | |
25 | QNC_SMM_NO_FLAGS,\r | |
26 | {\r | |
27 | {\r | |
28 | {GPE_ADDR_TYPE, {R_QNC_GPE0BLK_SMIE}}, S_QNC_GPE0BLK_SMIE, N_QNC_GPE0BLK_SMIE_SLP\r | |
29 | },\r | |
30 | NULL_BIT_DESC_INITIALIZER\r | |
31 | },\r | |
32 | {\r | |
33 | {\r | |
34 | {GPE_ADDR_TYPE, {R_QNC_GPE0BLK_SMIS}}, S_QNC_GPE0BLK_SMIS, N_QNC_GPE0BLK_SMIS_SLP\r | |
35 | }\r | |
36 | }\r | |
37 | };\r | |
38 | \r | |
39 | VOID\r | |
40 | SxGetContext(\r | |
41 | IN DATABASE_RECORD *Record,\r | |
42 | OUT QNC_SMM_CONTEXT *Context\r | |
43 | )\r | |
44 | {\r | |
45 | UINT32 Pm1Cnt;\r | |
46 | \r | |
47 | Pm1Cnt = IoRead32 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C);\r | |
48 | \r | |
49 | //\r | |
50 | // By design, the context phase will always be ENTRY\r | |
51 | //\r | |
52 | Context->Sx.Phase = SxEntry;\r | |
53 | \r | |
54 | //\r | |
55 | // Map the PM1_CNT register's SLP_TYP bits to the context type\r | |
56 | //\r | |
57 | switch (Pm1Cnt & B_QNC_PM1BLK_PM1C_SLPTP) {\r | |
58 | \r | |
59 | case V_S0:\r | |
60 | Context->Sx.Type = SxS0;\r | |
61 | break;\r | |
62 | \r | |
63 | case V_S3:\r | |
64 | Context->Sx.Type = SxS3;\r | |
65 | break;\r | |
66 | \r | |
67 | case V_S4:\r | |
68 | Context->Sx.Type = SxS4;\r | |
69 | break;\r | |
70 | \r | |
71 | case V_S5:\r | |
72 | Context->Sx.Type = SxS5;\r | |
73 | break;\r | |
74 | \r | |
75 | default:\r | |
76 | ASSERT (FALSE);\r | |
77 | break;\r | |
78 | };\r | |
79 | }\r | |
80 | \r | |
81 | BOOLEAN\r | |
82 | SxCmpContext (\r | |
83 | IN QNC_SMM_CONTEXT *Context1,\r | |
84 | IN QNC_SMM_CONTEXT *Context2\r | |
85 | )\r | |
86 | {\r | |
87 | return (BOOLEAN)(Context1->Sx.Type == Context2->Sx.Type);\r | |
88 | }\r | |
89 | \r | |
90 | VOID\r | |
91 | QNCSmmSxGoToSleep(\r | |
92 | VOID\r | |
93 | )\r | |
94 | /*++\r | |
95 | \r | |
96 | Routine Description:\r | |
97 | \r | |
98 | When we get an SMI that indicates that we are transitioning to a sleep state,\r | |
99 | we need to actually transition to that state. We do this by disabling the\r | |
100 | "SMI on sleep enable" feature, which generates an SMI when the operating system\r | |
101 | tries to put the system to sleep, and then physically putting the system to sleep.\r | |
102 | \r | |
103 | Returns:\r | |
104 | \r | |
105 | None.\r | |
106 | \r | |
107 | --*/\r | |
108 | {\r | |
109 | UINT32 Pm1Cnt;\r | |
110 | \r | |
111 | //\r | |
112 | // Flush cache into memory before we go to sleep. It is necessary for S3 sleep\r | |
113 | // because we may update memory in SMM Sx sleep handlers -- the updates are in cache now\r | |
114 | //\r | |
115 | AsmWbinvd();\r | |
116 | \r | |
117 | //\r | |
118 | // Disable SMIs\r | |
119 | //\r | |
120 | QNCSmmClearSource (&SX_SOURCE_DESC );\r | |
121 | QNCSmmDisableSource (&SX_SOURCE_DESC);\r | |
122 | \r | |
123 | //\r | |
124 | // Clear Sleep Type Enable\r | |
125 | //\r | |
126 | IoAnd16 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIE, (UINT16)(~B_QNC_GPE0BLK_SMIE_SLP));\r | |
127 | \r | |
128 | // clear sleep SMI status\r | |
129 | IoAnd16 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIS, (UINT16)(S_QNC_GPE0BLK_SMIS));\r | |
130 | \r | |
131 | //\r | |
132 | // Now that SMIs are disabled, write to the SLP_EN bit again to trigger the sleep\r | |
133 | //\r | |
134 | Pm1Cnt = IoOr32 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C, B_QNC_PM1BLK_PM1C_SLPEN);\r | |
135 | \r | |
136 | //\r | |
137 | // The system just went to sleep. If the sleep state was S1, then code execution will resume\r | |
138 | // here when the system wakes up.\r | |
139 | //\r | |
140 | Pm1Cnt = IoRead32 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C);\r | |
141 | if ((Pm1Cnt & B_QNC_PM1BLK_PM1C_SCIEN) == 0) {\r | |
142 | //\r | |
143 | // An ACPI OS isn't present, clear the sleep information\r | |
144 | //\r | |
145 | Pm1Cnt &= ~B_QNC_PM1BLK_PM1C_SLPTP;\r | |
146 | Pm1Cnt |= V_S0;\r | |
147 | \r | |
148 | IoWrite32 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C, Pm1Cnt);\r | |
149 | }\r | |
150 | \r | |
151 | QNCSmmClearSource (&SX_SOURCE_DESC);\r | |
152 | QNCSmmEnableSource (&SX_SOURCE_DESC);\r | |
153 | }\r |