[mirror_edk2.git] / QuarkSocPkg / QuarkSouthCluster / Include / MMC.h

/** @file\r
\r
Header file for Industry MMC 4.2 spec.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _MMC_H\r
#define _MMC_H\r
\r
#pragma pack(1)\r
//\r
//Command definition\r
//\r
\r
#define  CMD0              0\r
#define  CMD1              1\r
#define  CMD2              2\r
#define  CMD3              3\r
#define  CMD4              4\r
#define  CMD6              6\r
#define  CMD7              7\r
#define  CMD8              8\r
#define  CMD9              9\r
#define  CMD10             10\r
#define  CMD11             11\r
#define  CMD12             12\r
#define  CMD13             13\r
#define  CMD14             14\r
#define  CMD15             15\r
#define  CMD16             16\r
#define  CMD17             17\r
#define  CMD18             18\r
#define  CMD19             19\r
#define  CMD20             20\r
#define  CMD23             23\r
#define  CMD24             24\r
#define  CMD25             25\r
#define  CMD26             26\r
#define  CMD27             27\r
#define  CMD28             28\r
#define  CMD29             29\r
#define  CMD30             30\r
#define  CMD35             35\r
#define  CMD36             36\r
#define  CMD38             38\r
#define  CMD39             39\r
#define  CMD40             40\r
#define  CMD42             42\r
#define  CMD55             55\r
#define  CMD56             56\r
\r
\r
\r
#define  GO_IDLE_STATE           CMD0\r
#define  SEND_OP_COND            CMD1\r
#define  ALL_SEND_CID            CMD2\r
#define  SET_RELATIVE_ADDR       CMD3\r
#define  SET_DSR                 CMD4\r
#define  SWITCH                  CMD6\r
#define  SELECT_DESELECT_CARD    CMD7\r
#define  SEND_EXT_CSD            CMD8\r
#define  SEND_CSD                CMD9\r
#define  SEND_CID                CMD10\r
#define  READ_DAT_UNTIL_STOP     CMD11\r
#define  STOP_TRANSMISSION       CMD12\r
#define  SEND_STATUS             CMD13\r
#define  BUSTEST_R               CMD14\r
#define  GO_INACTIVE_STATE       CMD15\r
#define  SET_BLOCKLEN            CMD16\r
#define  READ_SINGLE_BLOCK       CMD17\r
#define  READ_MULTIPLE_BLOCK     CMD18\r
#define  BUSTEST_W               CMD19\r
#define  WRITE_DAT_UNTIL_STOP    CMD20\r
#define  SET_BLOCK_COUNT         CMD23\r
#define  WRITE_BLOCK             CMD24\r
#define  WRITE_MULTIPLE_BLOCK    CMD25\r
#define  PROGRAM_CID             CMD26\r
#define  PROGRAM_CSD             CMD27\r
#define  SET_WRITE_PROT          CMD28\r
#define  CLR_WRITE_PROT          CMD29\r
#define  SEND_WRITE_PROT         CMD30\r
#define  ERASE_GROUP_START       CMD35\r
#define  ERASE_GROUP_END         CMD36\r
#define  ERASE                   CMD38\r
#define  FAST_IO                 CMD39\r
#define  GO_IRQ_STATE            CMD40\r
#define  LOCK_UNLOCK             CMD42\r
#define  APP_CMD                 CMD55\r
#define  GEN_CMD                 CMD56\r
\r
\r
#define CMD_INDEX_MASK           0x3F\r
#define AUTO_CMD12_ENABLE        BIT6\r
#define AUTO_CMD23_ENABLE        BIT7\r
\r
#define FREQUENCY_OD            (400 * 1000)\r
#define FREQUENCY_MMC_PP        (26 * 1000 * 1000)\r
#define FREQUENCY_MMC_PP_HIGH   (52 * 1000 * 1000)\r
\r
#define DEFAULT_DSR_VALUE        0x404\r
\r
//\r
//Registers definition\r
//\r
\r
typedef struct {\r
  UINT32  Reserved0:   7;  // 0\r
  UINT32  V170_V195:   1;  // 1.70V - 1.95V\r
  UINT32  V200_V260:   7;  // 2.00V - 2.60V\r
  UINT32  V270_V360:   9;  // 2.70V - 3.60V\r
  UINT32  Reserved1:   5;  // 0\r
  UINT32  AccessMode:  2;  // 00b (byte mode), 10b (sector mode)\r
  UINT32  Busy:        1;  // This bit is set to LOW if the card has not finished the power up routine\r
}OCR;\r
\r
\r
typedef struct {\r
  UINT8   NotUsed:     1; //  1\r
  UINT8   CRC:         7; //  CRC7 checksum\r
  UINT8   MDT;            //  Manufacturing date\r
  UINT32  PSN;            //  Product serial number\r
  UINT8   PRV;            //  Product revision\r
  UINT8   PNM[6];         //  Product name\r
  UINT16  OID;            //  OEM/Application ID\r
  UINT8   MID;            //  Manufacturer ID\r
}CID;\r
\r
\r
typedef struct {\r
  UINT8   NotUsed:            1; //  1 [0:0]\r
  UINT8   CRC:                7; //  CRC [7:1]\r
  UINT8   ECC:                2; //  ECC code [9:8]\r
  UINT8   FILE_FORMAT:        2; //  File format [11:10]\r
  UINT8   TMP_WRITE_PROTECT:  1; //  Temporary write protection [12:12]\r
  UINT8   PERM_WRITE_PROTECT: 1; //  Permanent write protection [13:13]\r
  UINT8   COPY:               1; //  Copy flag (OTP) [14:14]\r
  UINT8   FILE_FORMAT_GRP:    1; //  File format group [15:15]\r
  UINT16  CONTENT_PROT_APP:   1; //  Content protection application [16:16]\r
  UINT16  Reserved0:          4; //  0 [20:17]\r
  UINT16  WRITE_BL_PARTIAL:   1; //  Partial blocks for write allowed [21:21]\r
  UINT16  WRITE_BL_LEN:       4; //  Max. write data block length [25:22]\r
  UINT16  R2W_FACTOR:         3; //  Write speed factor [28:26]\r
  UINT16  DEFAULT_ECC:        2; //  Manufacturer default ECC [30:29]\r
  UINT16  WP_GRP_ENABLE:      1; //  Write protect group enable [31:31]\r
  UINT32  WP_GRP_SIZE:        5; //  Write protect group size [36:32]\r
  UINT32  ERASE_GRP_MULT:     5; //  Erase group size multiplier [41:37]\r
  UINT32  ERASE_GRP_SIZE:     5; //  Erase group size [46:42]\r
  UINT32  C_SIZE_MULT:        3; //  Device size multiplier [49:47]\r
  UINT32  VDD_W_CURR_MAX:     3; //  Max. write current @ VDD max [52:50]\r
  UINT32  VDD_W_CURR_MIN:     3; //  Max. write current @ VDD min [55:53]\r
  UINT32  VDD_R_CURR_MAX:     3; //  Max. read current @ VDD max [58:56]\r
  UINT32  VDD_R_CURR_MIN:     3; //  Max. read current @ VDD min [61:59]\r
  UINT32  C_SIZELow2:         2;//  Device size [73:62]\r
  UINT32  C_SIZEHigh10:       10;//  Device size [73:62]\r
  UINT32  Reserved1:          2; //  0 [75:74]\r
  UINT32  DSR_IMP:            1; //  DSR implemented [76:76]\r
  UINT32  READ_BLK_MISALIGN:  1; //  Read block misalignment [77:77]\r
  UINT32  WRITE_BLK_MISALIGN: 1; //  Write block misalignment [78:78]\r
  UINT32  READ_BL_PARTIAL:    1; //  Partial blocks for read allowed [79:79]\r
  UINT32  READ_BL_LEN:        4; //  Max. read data block length [83:80]\r
  UINT32  CCC:                12;//  Card command classes [95:84]\r
  UINT8   TRAN_SPEED          ; //  Max. bus clock frequency [103:96]\r
  UINT8   NSAC                ; //  Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
  UINT8   TAAC                ; //  Data read access-time 1 [119:112]\r
  UINT8   Reserved2:          2; //  0 [121:120]\r
  UINT8   SPEC_VERS:          4; //  System specification version [125:122]\r
  UINT8   CSD_STRUCTURE:      2; //  CSD structure [127:126]\r
}CSD;\r
\r
typedef struct {\r
  UINT8  Reserved0[181];         //  0 [0:180]\r
  UINT8  ERASED_MEM_CONT;        //  Erased Memory Content [181]\r
  UINT8  Reserved2;              //  Erased Memory Content [182]\r
  UINT8  BUS_WIDTH;              //  Bus Width Mode [183]\r
  UINT8  Reserved3;              //  0 [184]\r
  UINT8  HS_TIMING;              //  High Speed Interface Timing [185]\r
  UINT8  Reserved4;              //  0 [186]\r
  UINT8  POWER_CLASS;            //  Power Class [187]\r
  UINT8  Reserved5;              //  0 [188]\r
  UINT8  CMD_SET_REV;            //  Command Set Revision [189]\r
  UINT8  Reserved6;              //  0 [190]\r
  UINT8  CMD_SET;                //  Command Set [191]\r
  UINT8  EXT_CSD_REV;            //  Extended CSD Revision [192]\r
  UINT8  Reserved7;              //  0 [193]\r
  UINT8  CSD_STRUCTURE;          //  CSD Structure Version [194]\r
  UINT8  Reserved8;              //  0 [195]\r
  UINT8  CARD_TYPE;              //  Card Type [196]\r
  UINT8  Reserved9[3];           //  0 [199:197]\r
  UINT8  PWR_CL_52_195;          //  Power Class for 52MHz @ 1.95V [200]\r
  UINT8  PWR_CL_26_195;          //  Power Class for 26MHz @ 1.95V [201]\r
  UINT8  PWR_CL_52_360;          //  Power Class for 52MHz @ 3.6V [202]\r
  UINT8  PWR_CL_26_360;          //  Power Class for 26MHz @ 3.6V [203]\r
  UINT8  Reserved10;             //  0 [204]\r
  UINT8  MIN_PERF_R_4_26;        //  Minimum Read Performance for 4bit @26MHz [205]\r
  UINT8  MIN_PERF_W_4_26;        //  Minimum Write Performance for 4bit @26MHz [206]\r
  UINT8  MIN_PERF_R_8_26_4_52;   //  Minimum Read Performance for 8bit @26MHz/4bit @52MHz [207]\r
  UINT8  MIN_PERF_W_8_26_4_52;   //  Minimum Write Performance for 8bit @26MHz/4bit @52MHz [208]\r
  UINT8  MIN_PERF_R_8_52;        //  Minimum Read Performance for 8bit @52MHz [209]\r
  UINT8  MIN_PERF_W_8_52;        //  Minimum Write Performance for 8bit @52MHz [210]\r
  UINT8  Reserved11;             //  0 [211]\r
  UINT8  SEC_COUNT[4];           //  Sector Count [215:212]\r
  UINT8  Reserved12[288];        //  0 [503:216]\r
  UINT8  S_CMD_SET;              //  Sector Count [504]\r
  UINT8  Reserved13[7];          //  Sector Count [511:505]\r
}EXT_CSD;\r
\r
\r
//\r
//Card Status definition\r
//\r
typedef struct {\r
  UINT32  Reserved0:           2; //Reserved for Manufacturer Test Mode\r
  UINT32  Reserved1:           2; //Reserved for Application Specific commands\r
  UINT32  Reserved2:           1; //\r
  UINT32  SAPP_CMD:            1; //\r
  UINT32  Reserved3:           1; //Reserved\r
  UINT32  SWITCH_ERROR:        1; //\r
  UINT32  READY_FOR_DATA:      1; //\r
  UINT32  CURRENT_STATE:       4; //\r
  UINT32  ERASE_RESET:         1; //\r
  UINT32  Reserved4:           1; //Reserved\r
  UINT32  WP_ERASE_SKIP:       1; //\r
  UINT32  CID_CSD_OVERWRITE:   1; //\r
  UINT32  OVERRUN:             1; //\r
  UINT32  UNDERRUN:            1; //\r
  UINT32  ERROR:               1; //\r
  UINT32  CC_ERROR:            1; //\r
  UINT32  CARD_ECC_FAILED:     1; //\r
  UINT32  ILLEGAL_COMMAND:     1; //\r
  UINT32  COM_CRC_ERROR:       1; //\r
  UINT32  LOCK_UNLOCK_FAILED:  1; //\r
  UINT32  CARD_IS_LOCKED:      1; //\r
  UINT32  WP_VIOLATION:        1; //\r
  UINT32  ERASE_PARAM:         1; //\r
  UINT32  ERASE_SEQ_ERROR:     1; //\r
  UINT32  BLOCK_LEN_ERROR:     1; //\r
  UINT32  ADDRESS_MISALIGN:    1; //\r
  UINT32  ADDRESS_OUT_OF_RANGE:1; //\r
}CARD_STATUS;\r
\r
typedef struct {\r
  UINT32  CmdSet:              3;\r
  UINT32  Reserved0:           5;\r
  UINT32  Value:               8;\r
  UINT32  Index:               8;\r
  UINT32  Access:              2;\r
  UINT32  Reserved1:           6;\r
}SWITCH_ARGUMENT;\r
\r
#define CommandSet_Mode          0\r
#define SetBits_Mode             1\r
#define ClearBits_Mode           2\r
#define WriteByte_Mode           3\r
\r
\r
#define  Idle_STATE              0\r
#define  Ready_STATE             1\r
#define  Ident_STATE             2\r
#define  Stby_STATE              3\r
#define  Tran_STATE              4\r
#define  Data_STATE              5\r
#define  Rcv_STATE               6\r
#define  Prg_STATE               7\r
#define  Dis_STATE               8\r
#define  Btst_STATE              9\r
\r
\r
\r
#pragma pack()\r
#endif\r
Commit	Line	Data
9b6bbcdb MK	1	/** @file\r
	2	\r
	3	Header file for Industry MMC 4.2 spec.\r
	4	\r
	5	Copyright (c) 2013-2015 Intel Corporation.\r
	6	\r
c9f231d0	7	SPDX-License-Identifier: BSD-2-Clause-Patent\r
9b6bbcdb MK	8	\r
	9	**/\r
	10	\r
	11	#ifndef _MMC_H\r
	12	#define _MMC_H\r
	13	\r
	14	#pragma pack(1)\r
	15	//\r
	16	//Command definition\r
	17	//\r
	18	\r
	19	#define CMD0 0\r
	20	#define CMD1 1\r
	21	#define CMD2 2\r
	22	#define CMD3 3\r
	23	#define CMD4 4\r
	24	#define CMD6 6\r
	25	#define CMD7 7\r
	26	#define CMD8 8\r
	27	#define CMD9 9\r
	28	#define CMD10 10\r
	29	#define CMD11 11\r
	30	#define CMD12 12\r
	31	#define CMD13 13\r
	32	#define CMD14 14\r
	33	#define CMD15 15\r
	34	#define CMD16 16\r
	35	#define CMD17 17\r
	36	#define CMD18 18\r
	37	#define CMD19 19\r
	38	#define CMD20 20\r
	39	#define CMD23 23\r
	40	#define CMD24 24\r
	41	#define CMD25 25\r
	42	#define CMD26 26\r
	43	#define CMD27 27\r
	44	#define CMD28 28\r
	45	#define CMD29 29\r
	46	#define CMD30 30\r
	47	#define CMD35 35\r
	48	#define CMD36 36\r
	49	#define CMD38 38\r
	50	#define CMD39 39\r
	51	#define CMD40 40\r
	52	#define CMD42 42\r
	53	#define CMD55 55\r
	54	#define CMD56 56\r
	55	\r
	56	\r
	57	\r
	58	#define GO_IDLE_STATE CMD0\r
	59	#define SEND_OP_COND CMD1\r
	60	#define ALL_SEND_CID CMD2\r
	61	#define SET_RELATIVE_ADDR CMD3\r
	62	#define SET_DSR CMD4\r
	63	#define SWITCH CMD6\r
	64	#define SELECT_DESELECT_CARD CMD7\r
	65	#define SEND_EXT_CSD CMD8\r
	66	#define SEND_CSD CMD9\r
	67	#define SEND_CID CMD10\r
	68	#define READ_DAT_UNTIL_STOP CMD11\r
	69	#define STOP_TRANSMISSION CMD12\r
	70	#define SEND_STATUS CMD13\r
	71	#define BUSTEST_R CMD14\r
72	#define GO_INACTIVE_STATE CMD15\r
73	#define SET_BLOCKLEN CMD16\r
74	#define READ_SINGLE_BLOCK CMD17\r
75	#define READ_MULTIPLE_BLOCK CMD18\r
76	#define BUSTEST_W CMD19\r
77	#define WRITE_DAT_UNTIL_STOP CMD20\r
78	#define SET_BLOCK_COUNT CMD23\r
79	#define WRITE_BLOCK CMD24\r
80	#define WRITE_MULTIPLE_BLOCK CMD25\r
81	#define PROGRAM_CID CMD26\r
82	#define PROGRAM_CSD CMD27\r
83	#define SET_WRITE_PROT CMD28\r
84	#define CLR_WRITE_PROT CMD29\r
85	#define SEND_WRITE_PROT CMD30\r
86	#define ERASE_GROUP_START CMD35\r
87	#define ERASE_GROUP_END CMD36\r
88	#define ERASE CMD38\r
89	#define FAST_IO CMD39\r
90	#define GO_IRQ_STATE CMD40\r
91	#define LOCK_UNLOCK CMD42\r
92	#define APP_CMD CMD55\r
93	#define GEN_CMD CMD56\r
94	\r
95	\r
96	#define CMD_INDEX_MASK 0x3F\r
97	#define AUTO_CMD12_ENABLE BIT6\r
98	#define AUTO_CMD23_ENABLE BIT7\r
99	\r
100	#define FREQUENCY_OD (400 * 1000)\r
101	#define FREQUENCY_MMC_PP (26 * 1000 * 1000)\r
102	#define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000)\r
103	\r
104	#define DEFAULT_DSR_VALUE 0x404\r
105	\r
106	//\r
107	//Registers definition\r
108	//\r
109	\r
110	typedef struct {\r
111	UINT32 Reserved0: 7; // 0\r
112	UINT32 V170_V195: 1; // 1.70V - 1.95V\r
113	UINT32 V200_V260: 7; // 2.00V - 2.60V\r
114	UINT32 V270_V360: 9; // 2.70V - 3.60V\r
115	UINT32 Reserved1: 5; // 0\r
116	UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)\r
117	UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine\r
118	}OCR;\r
119	\r
120	\r
121	typedef struct {\r
122	UINT8 NotUsed: 1; // 1\r
123	UINT8 CRC: 7; // CRC7 checksum\r
124	UINT8 MDT; // Manufacturing date\r
125	UINT32 PSN; // Product serial number\r
126	UINT8 PRV; // Product revision\r
127	UINT8 PNM[6]; // Product name\r
128	UINT16 OID; // OEM/Application ID\r
129	UINT8 MID; // Manufacturer ID\r
130	}CID;\r
131	\r
132	\r
133	typedef struct {\r
134	UINT8 NotUsed: 1; // 1 [0:0]\r
135	UINT8 CRC: 7; // CRC [7:1]\r
136	UINT8 ECC: 2; // ECC code [9:8]\r
137	UINT8 FILE_FORMAT: 2; // File format [11:10]\r
138	UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]\r
139	UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]\r
140	UINT8 COPY: 1; // Copy flag (OTP) [14:14]\r
141	UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]\r
142	UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16]\r
143	UINT16 Reserved0: 4; // 0 [20:17]\r
144	UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]\r
145	UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]\r
146	UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]\r
147	UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]\r
148	UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]\r
149	UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32]\r
150	UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37]\r
151	UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42]\r
152	UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]\r
153	UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]\r
154	UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]\r
155	UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]\r
156	UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]\r
157	UINT32 C_SIZELow2: 2;// Device size [73:62]\r
158	UINT32 C_SIZEHigh10: 10;// Device size [73:62]\r
159	UINT32 Reserved1: 2; // 0 [75:74]\r
160	UINT32 DSR_IMP: 1; // DSR implemented [76:76]\r
161	UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]\r
162	UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]\r
163	UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]\r
164	UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]\r
165	UINT32 CCC: 12;// Card command classes [95:84]\r
166	UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]\r
167	UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
168	UINT8 TAAC ; // Data read access-time 1 [119:112]\r
169	UINT8 Reserved2: 2; // 0 [121:120]\r
170	UINT8 SPEC_VERS: 4; // System specification version [125:122]\r
171	UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]\r
172	}CSD;\r
173	\r
174	typedef struct {\r
175	UINT8 Reserved0[181]; // 0 [0:180]\r
176	UINT8 ERASED_MEM_CONT; // Erased Memory Content [181]\r
177	UINT8 Reserved2; // Erased Memory Content [182]\r
178	UINT8 BUS_WIDTH; // Bus Width Mode [183]\r
179	UINT8 Reserved3; // 0 [184]\r
180	UINT8 HS_TIMING; // High Speed Interface Timing [185]\r
181	UINT8 Reserved4; // 0 [186]\r
182	UINT8 POWER_CLASS; // Power Class [187]\r
183	UINT8 Reserved5; // 0 [188]\r
184	UINT8 CMD_SET_REV; // Command Set Revision [189]\r
185	UINT8 Reserved6; // 0 [190]\r
186	UINT8 CMD_SET; // Command Set [191]\r
187	UINT8 EXT_CSD_REV; // Extended CSD Revision [192]\r
188	UINT8 Reserved7; // 0 [193]\r
189	UINT8 CSD_STRUCTURE; // CSD Structure Version [194]\r
190	UINT8 Reserved8; // 0 [195]\r
191	UINT8 CARD_TYPE; // Card Type [196]\r
192	UINT8 Reserved9[3]; // 0 [199:197]\r
193	UINT8 PWR_CL_52_195; // Power Class for 52MHz @ 1.95V [200]\r
194	UINT8 PWR_CL_26_195; // Power Class for 26MHz @ 1.95V [201]\r
195	UINT8 PWR_CL_52_360; // Power Class for 52MHz @ 3.6V [202]\r
196	UINT8 PWR_CL_26_360; // Power Class for 26MHz @ 3.6V [203]\r
197	UINT8 Reserved10; // 0 [204]\r
198	UINT8 MIN_PERF_R_4_26; // Minimum Read Performance for 4bit @26MHz [205]\r
199	UINT8 MIN_PERF_W_4_26; // Minimum Write Performance for 4bit @26MHz [206]\r
200	UINT8 MIN_PERF_R_8_26_4_52; // Minimum Read Performance for 8bit @26MHz/4bit @52MHz [207]\r
201	UINT8 MIN_PERF_W_8_26_4_52; // Minimum Write Performance for 8bit @26MHz/4bit @52MHz [208]\r
202	UINT8 MIN_PERF_R_8_52; // Minimum Read Performance for 8bit @52MHz [209]\r
203	UINT8 MIN_PERF_W_8_52; // Minimum Write Performance for 8bit @52MHz [210]\r
204	UINT8 Reserved11; // 0 [211]\r
205	UINT8 SEC_COUNT[4]; // Sector Count [215:212]\r
206	UINT8 Reserved12[288]; // 0 [503:216]\r
207	UINT8 S_CMD_SET; // Sector Count [504]\r
208	UINT8 Reserved13[7]; // Sector Count [511:505]\r
209	}EXT_CSD;\r
210	\r
211	\r
212	//\r
213	//Card Status definition\r
214	//\r
215	typedef struct {\r
216	UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode\r
217	UINT32 Reserved1: 2; //Reserved for Application Specific commands\r
218	UINT32 Reserved2: 1; //\r
219	UINT32 SAPP_CMD: 1; //\r
220	UINT32 Reserved3: 1; //Reserved\r
221	UINT32 SWITCH_ERROR: 1; //\r
222	UINT32 READY_FOR_DATA: 1; //\r
223	UINT32 CURRENT_STATE: 4; //\r
224	UINT32 ERASE_RESET: 1; //\r
225	UINT32 Reserved4: 1; //Reserved\r
226	UINT32 WP_ERASE_SKIP: 1; //\r
227	UINT32 CID_CSD_OVERWRITE: 1; //\r
228	UINT32 OVERRUN: 1; //\r
229	UINT32 UNDERRUN: 1; //\r
230	UINT32 ERROR: 1; //\r
231	UINT32 CC_ERROR: 1; //\r
232	UINT32 CARD_ECC_FAILED: 1; //\r
233	UINT32 ILLEGAL_COMMAND: 1; //\r
234	UINT32 COM_CRC_ERROR: 1; //\r
235	UINT32 LOCK_UNLOCK_FAILED: 1; //\r
236	UINT32 CARD_IS_LOCKED: 1; //\r
237	UINT32 WP_VIOLATION: 1; //\r
238	UINT32 ERASE_PARAM: 1; //\r
239	UINT32 ERASE_SEQ_ERROR: 1; //\r
240	UINT32 BLOCK_LEN_ERROR: 1; //\r
241	UINT32 ADDRESS_MISALIGN: 1; //\r
242	UINT32 ADDRESS_OUT_OF_RANGE:1; //\r
243	}CARD_STATUS;\r
244	\r
245	typedef struct {\r
246	UINT32 CmdSet: 3;\r
247	UINT32 Reserved0: 5;\r
248	UINT32 Value: 8;\r
249	UINT32 Index: 8;\r
250	UINT32 Access: 2;\r
251	UINT32 Reserved1: 6;\r
252	}SWITCH_ARGUMENT;\r
253	\r
254	#define CommandSet_Mode 0\r
255	#define SetBits_Mode 1\r
256	#define ClearBits_Mode 2\r
257	#define WriteByte_Mode 3\r
258	\r
259	\r
260	#define Idle_STATE 0\r
261	#define Ready_STATE 1\r
262	#define Ident_STATE 2\r
263	#define Stby_STATE 3\r
264	#define Tran_STATE 4\r
265	#define Data_STATE 5\r
266	#define Rcv_STATE 6\r
267	#define Prg_STATE 7\r
268	#define Dis_STATE 8\r
269	#define Btst_STATE 9\r
270	\r
271	\r
272	\r
273	#pragma pack()\r
274	#endif\r