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9b6bbcdb MK |
1 | /** @file\r |
2 | This file contains the definination for host controller\r | |
3 | register operation routines.\r | |
4 | \r | |
5 | Copyright (c) 2013-2015 Intel Corporation.\r | |
6 | \r | |
c9f231d0 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
9b6bbcdb MK |
8 | \r |
9 | **/\r | |
10 | \r | |
11 | \r | |
12 | \r | |
13 | #ifndef _OHCI_REGS_H\r | |
14 | #define _OHCI_REGS_H\r | |
15 | \r | |
16 | #define HC_STATE_RESET 0x0\r | |
17 | #define HC_STATE_RESUME 0x1\r | |
18 | #define HC_STATE_OPERATIONAL 0x2\r | |
19 | #define HC_STATE_SUSPEND 0x3\r | |
20 | \r | |
21 | #define PERIODIC_ENABLE 0x01\r | |
22 | #define ISOCHRONOUS_ENABLE 0x02\r | |
23 | #define CONTROL_ENABLE 0x04\r | |
24 | #define BULK_ENABLE 0x08\r | |
25 | #define CONTROL_BULK_RATIO 0x10\r | |
26 | \r | |
27 | #define HC_FUNCTIONAL_STATE 0x20\r | |
28 | #define INTERRUPT_ROUTING 0x40\r | |
29 | \r | |
30 | #define HC_RESET 0x01\r | |
31 | #define CONTROL_LIST_FILLED 0x02\r | |
32 | #define BULK_LIST_FILLED 0x04\r | |
33 | #define CHANGE_OWNER_REQUEST 0x08\r | |
34 | \r | |
35 | #define SCHEDULE_OVERRUN_COUNT 0x10\r | |
36 | \r | |
37 | #define SCHEDULE_OVERRUN 0x00001\r | |
38 | #define WRITEBACK_DONE_HEAD 0x00002\r | |
39 | #define START_OF_FRAME 0x00004\r | |
40 | #define RESUME_DETECT 0x00008\r | |
41 | #define UNRECOVERABLE_ERROR 0x00010\r | |
42 | #define FRAME_NUMBER_OVERFLOW 0x00020\r | |
43 | #define ROOTHUB_STATUS_CHANGE 0x00040\r | |
44 | #define OWNERSHIP_CHANGE 0x00080\r | |
45 | \r | |
46 | #define MASTER_INTERRUPT 0x00400\r | |
47 | \r | |
48 | #define CONTROL_HEAD 0x001\r | |
49 | #define BULK_HEAD 0x002\r | |
50 | #define DONE_HEAD 0x004\r | |
51 | \r | |
52 | #define Hc_HCCA 0x001\r | |
53 | #define Hc_PERIODIC_CURRENT 0x002\r | |
54 | #define Hc_CONTOL_HEAD 0x004\r | |
55 | #define Hc_CONTROL_CURRENT_PTR 0x008\r | |
56 | #define Hc_BULK_HEAD 0x010\r | |
57 | #define Hc_BULK_CURRENT_PTR 0x020\r | |
58 | #define Hc_DONE_HEAD 0x040\r | |
59 | \r | |
60 | #define FRAME_INTERVAL 0x008\r | |
61 | #define FS_LARGEST_DATA_PACKET 0x010\r | |
62 | #define FRMINT_TOGGLE 0x020\r | |
63 | #define FRAME_REMAINING 0x040\r | |
64 | #define FRAME_REMAIN_TOGGLE 0x080\r | |
65 | \r | |
66 | #define RH_DESC_A 0x00001\r | |
67 | #define RH_DESC_B 0x00002\r | |
68 | #define RH_NUM_DS_PORTS 0x00004\r | |
69 | #define RH_NO_PSWITCH 0x00008\r | |
70 | #define RH_PSWITCH_MODE 0x00010\r | |
71 | #define RH_DEVICE_TYPE 0x00020\r | |
72 | #define RH_OC_PROT_MODE 0x00040\r | |
73 | #define RH_NOC_PROT 0x00080\r | |
74 | #define RH_POTPGT 0x00100\r | |
75 | #define RH_NO_POTPGT 0x00200\r | |
76 | #define RH_DEV_REMOVABLE 0x00400\r | |
77 | #define RH_PORT_PWR_CTRL_MASK 0x00800\r | |
78 | \r | |
79 | #define RH_LOCAL_PSTAT 0x00001\r | |
80 | #define RH_OC_ID 0x00002\r | |
81 | #define RH_REMOTE_WK_ENABLE 0x00004\r | |
82 | #define RH_LOCAL_PSTAT_CHANGE 0x00008\r | |
83 | #define RH_OC_ID_CHANGE 0x00010\r | |
84 | #define RH_CLR_RMT_WK_ENABLE 0x00020\r | |
85 | \r | |
86 | #define RH_CLEAR_PORT_ENABLE 0x0001\r | |
87 | #define RH_SET_PORT_ENABLE 0x0002\r | |
88 | #define RH_SET_PORT_SUSPEND 0x0004\r | |
89 | #define RH_CLEAR_SUSPEND_STATUS 0x0008\r | |
90 | #define RH_SET_PORT_RESET 0x0010\r | |
91 | #define RH_SET_PORT_POWER 0x0020\r | |
92 | #define RH_CLEAR_PORT_POWER 0x0040\r | |
93 | #define RH_CONNECT_STATUS_CHANGE 0x10000\r | |
94 | #define RH_PORT_ENABLE_STAT_CHANGE 0x20000\r | |
95 | #define RH_PORT_SUSPEND_STAT_CHANGE 0x40000\r | |
96 | #define RH_OC_INDICATOR_CHANGE 0x80000\r | |
97 | #define RH_PORT_RESET_STAT_CHANGE 0x100000\r | |
98 | \r | |
99 | #define RH_CURR_CONNECT_STAT 0x0001\r | |
100 | #define RH_PORT_ENABLE_STAT 0x0002\r | |
101 | #define RH_PORT_SUSPEND_STAT 0x0004\r | |
102 | #define RH_PORT_OC_INDICATOR 0x0008\r | |
103 | #define RH_PORT_RESET_STAT 0x0010\r | |
104 | #define RH_PORT_POWER_STAT 0x0020\r | |
105 | #define RH_LSDEVICE_ATTACHED 0x0040\r | |
106 | \r | |
107 | #define RESET_SYSTEM_BUS (1 << 0)\r | |
108 | #define RESET_HOST_CONTROLLER (1 << 1)\r | |
109 | #define RESET_CLOCK_GENERATION (1 << 2)\r | |
110 | #define RESET_SSE_GLOBAL (1 << 5)\r | |
111 | #define RESET_PSPL (1 << 6)\r | |
112 | #define RESET_PCPL (1 << 7)\r | |
113 | #define RESET_SSEP1 (1 << 9)\r | |
114 | #define RESET_SSEP2 (1 << 10)\r | |
115 | #define RESET_SSEP3 (1 << 11)\r | |
116 | \r | |
117 | #define ONE_SECOND 1000000\r | |
118 | #define ONE_MILLI_SEC 1000\r | |
119 | #define MAX_BYTES_PER_TD 0x1000\r | |
120 | #define MAX_RETRY_TIMES 100\r | |
121 | #define PORT_NUMBER_ON_MAINSTONE2 1\r | |
122 | \r | |
123 | \r | |
124 | //\r | |
125 | // Operational Register Offsets\r | |
126 | //\r | |
127 | \r | |
128 | //\r | |
129 | // Command & Status Registers Offsets\r | |
130 | //\r | |
131 | #define HC_REVISION 0x00\r | |
132 | #define HC_CONTROL 0x04\r | |
133 | #define HC_COMMAND_STATUS 0x08\r | |
134 | #define HC_INTERRUPT_STATUS 0x0C\r | |
135 | #define HC_INTERRUPT_ENABLE 0x10\r | |
136 | #define HC_INTERRUPT_DISABLE 0x14\r | |
137 | \r | |
138 | //\r | |
139 | // Memory Pointer Offsets\r | |
140 | //\r | |
141 | #define HC_HCCA 0x18\r | |
142 | #define HC_PERIODIC_CURRENT 0x1C\r | |
143 | #define HC_CONTROL_HEAD 0x20\r | |
144 | #define HC_CONTROL_CURRENT_PTR 0x24\r | |
145 | #define HC_BULK_HEAD 0x28\r | |
146 | #define HC_BULK_CURRENT_PTR 0x2C\r | |
147 | #define HC_DONE_HEAD 0x30\r | |
148 | \r | |
149 | //\r | |
150 | // Frame Register Offsets\r | |
151 | //\r | |
152 | #define HC_FRM_INTERVAL 0x34\r | |
153 | #define HC_FRM_REMAINING 0x38\r | |
154 | #define HC_FRM_NUMBER 0x3C\r | |
155 | #define HC_PERIODIC_START 0x40\r | |
156 | #define HC_LS_THREASHOLD 0x44\r | |
157 | \r | |
158 | //\r | |
159 | // Root Hub Register Offsets\r | |
160 | //\r | |
161 | #define HC_RH_DESC_A 0x48\r | |
162 | #define HC_RH_DESC_B 0x4C\r | |
163 | #define HC_RH_STATUS 0x50\r | |
164 | #define HC_RH_PORT_STATUS 0x54\r | |
165 | \r | |
166 | #define USBHOST_OFFSET_UHCHR 0x64 // Usb Host reset register\r | |
167 | \r | |
168 | #define OHC_BAR_INDEX 0\r | |
169 | \r | |
170 | //\r | |
171 | // Usb Host controller register offset\r | |
172 | //\r | |
173 | #define USBHOST_OFFSET_UHCREV 0x0 // Usb Host revision register\r | |
174 | #define USBHOST_OFFSET_UHCHCON 0x4 // Usb Host control register\r | |
175 | #define USBHOST_OFFSET_UHCCOMS 0x8 // Usb Host Command Status register\r | |
176 | #define USBHOST_OFFSET_UHCINTS 0xC // Usb Host Interrupt Status register\r | |
177 | #define USBHOST_OFFSET_UHCINTE 0x10 // Usb Host Interrupt Enable register\r | |
178 | #define USBHOST_OFFSET_UHCINTD 0x14 // Usb Host Interrupt Disable register\r | |
179 | #define USBHOST_OFFSET_UHCHCCA 0x18 // Usb Host Controller Communication Area\r | |
180 | #define USBHOST_OFFSET_UHCPCED 0x1C // Usb Host Period Current Endpoint Descriptor\r | |
181 | #define USBHOST_OFFSET_UHCCHED 0x20 // Usb Host Control Head Endpoint Descriptor\r | |
182 | #define USBHOST_OFFSET_UHCCCED 0x24 // Usb Host Control Current Endpoint Descriptor\r | |
183 | #define USBHOST_OFFSET_UHCBHED 0x28 // Usb Host Bulk Head Endpoint Descriptor\r | |
184 | #define USBHOST_OFFSET_UHCBCED 0x2C // Usb Host Bulk Current Endpoint Descriptor\r | |
185 | #define USBHOST_OFFSET_UHCDHEAD 0x30 // Usb Host Done Head register\r | |
186 | #define USBHOST_OFFSET_UHCFMI 0x34 // Usb Host Frame Interval register\r | |
187 | #define USBHOST_OFFSET_UHCFMR 0x38 // Usb Host Frame Remaining register\r | |
188 | #define USBHOST_OFFSET_UHCFMN 0x3C // Usb Host Frame Number register\r | |
189 | #define USBHOST_OFFSET_UHCPERS 0x40 // Usb Host Periodic Start register\r | |
190 | #define USBHOST_OFFSET_UHCLST 0x44 // Usb Host Low-Speed Threshold register\r | |
191 | #define USBHOST_OFFSET_UHCRHDA 0x48 // Usb Host Root Hub Descriptor A register\r | |
192 | #define USBHOST_OFFSET_UHCRHDB 0x4C // Usb Host Root Hub Descriptor B register\r | |
193 | #define USBHOST_OFFSET_UHCRHS 0x50 // Usb Host Root Hub Status register\r | |
194 | #define USBHOST_OFFSET_UHCRHPS1 0x54 // Usb Host Root Hub Port Status 1 register\r | |
195 | \r | |
196 | //\r | |
197 | // Usb Host controller register bit fields\r | |
198 | //\r | |
199 | #pragma pack(1)\r | |
200 | \r | |
201 | typedef struct {\r | |
202 | UINT8 ProgInterface;\r | |
203 | UINT8 SubClassCode;\r | |
204 | UINT8 BaseCode;\r | |
205 | } USB_CLASSC;\r | |
206 | \r | |
207 | typedef struct {\r | |
208 | UINT32 Revision:8;\r | |
209 | UINT32 Rsvd:24;\r | |
210 | } HcREVISION;\r | |
211 | \r | |
212 | typedef struct {\r | |
213 | UINT32 ControlBulkRatio:2;\r | |
214 | UINT32 PeriodicEnable:1;\r | |
215 | UINT32 IsochronousEnable:1;\r | |
216 | UINT32 ControlEnable:1;\r | |
217 | UINT32 BulkEnable:1;\r | |
218 | UINT32 FunctionalState:2;\r | |
219 | UINT32 InterruptRouting:1;\r | |
220 | UINT32 RemoteWakeup:1;\r | |
221 | UINT32 RemoteWakeupEnable:1;\r | |
222 | UINT32 Reserved:21;\r | |
223 | } HcCONTROL;\r | |
224 | \r | |
225 | typedef struct {\r | |
226 | UINT32 HcReset:1;\r | |
227 | UINT32 ControlListFilled:1;\r | |
228 | UINT32 BulkListFilled:1;\r | |
229 | UINT32 ChangeOwnerRequest:1;\r | |
230 | UINT32 Reserved1:12;\r | |
231 | UINT32 ScheduleOverrunCount:2;\r | |
232 | UINT32 Reserved:14;\r | |
233 | } HcCOMMAND_STATUS;\r | |
234 | \r | |
235 | typedef struct {\r | |
236 | UINT32 SchedulingOverrun:1;\r | |
237 | UINT32 WriteBackDone:1;\r | |
238 | UINT32 Sof:1;\r | |
239 | UINT32 ResumeDetected:1;\r | |
240 | UINT32 UnrecoverableError:1;\r | |
241 | UINT32 FrameNumOverflow:1;\r | |
242 | UINT32 RHStatusChange:1;\r | |
243 | UINT32 Reserved1:23;\r | |
244 | UINT32 OwnerChange:1;\r | |
245 | UINT32 Reserved2:1;\r | |
246 | } HcINTERRUPT_STATUS;\r | |
247 | \r | |
248 | typedef struct {\r | |
249 | UINT32 SchedulingOverrunInt:1;\r | |
250 | UINT32 WriteBackDoneInt:1;\r | |
251 | UINT32 SofInt:1;\r | |
252 | UINT32 ResumeDetectedInt:1;\r | |
253 | UINT32 UnrecoverableErrorInt:1;\r | |
254 | UINT32 FrameNumOverflowInt:1;\r | |
255 | UINT32 RHStatusChangeInt:1;\r | |
256 | UINT32 Reserved:23;\r | |
257 | UINT32 OwnerChangedInt:1;\r | |
258 | UINT32 MasterInterruptEnable:1;\r | |
259 | } HcINTERRUPT_CONTROL;\r | |
260 | \r | |
261 | typedef struct {\r | |
262 | UINT32 Rerserved:8;\r | |
263 | UINT32 Hcca:24;\r | |
264 | } HcHCCA;\r | |
265 | \r | |
266 | typedef struct {\r | |
267 | UINT32 Reserved:4;\r | |
268 | UINT32 MemoryPtr:28;\r | |
269 | } HcMEMORY_PTR;\r | |
270 | \r | |
271 | typedef struct {\r | |
272 | UINT32 FrameInterval:14;\r | |
273 | UINT32 Reserved:2;\r | |
274 | UINT32 FSMaxDataPacket:15;\r | |
275 | UINT32 FrmIntervalToggle:1;\r | |
276 | } HcFRM_INTERVAL;\r | |
277 | \r | |
278 | typedef struct {\r | |
279 | UINT32 FrameRemaining:14;\r | |
280 | UINT32 Reserved:17;\r | |
281 | UINT32 FrameRemainingToggle:1;\r | |
282 | } HcFRAME_REMAINING;\r | |
283 | \r | |
284 | typedef struct {\r | |
285 | UINT32 FrameNumber:16;\r | |
286 | UINT32 Reserved:16;\r | |
287 | } HcFRAME_NUMBER;\r | |
288 | \r | |
289 | typedef struct {\r | |
290 | UINT32 PeriodicStart:14;\r | |
291 | UINT32 Reserved:18;\r | |
292 | } HcPERIODIC_START;\r | |
293 | \r | |
294 | typedef struct {\r | |
295 | UINT32 LsThreshold:12;\r | |
296 | UINT32 Reserved:20;\r | |
297 | } HcLS_THRESHOLD;\r | |
298 | \r | |
299 | typedef struct {\r | |
300 | UINT32 NumDownStrmPorts:8;\r | |
301 | UINT32 PowerSwitchMode:1;\r | |
302 | UINT32 NoPowerSwitch:1;\r | |
303 | UINT32 DeviceType:1;\r | |
304 | UINT32 OverCurrentProtMode:1;\r | |
305 | UINT32 NoOverCurrentProtMode:1;\r | |
306 | UINT32 Reserved:11;\r | |
307 | UINT32 PowerOnToPowerGoodTime:8;\r | |
308 | } HcRH_DESC_A;\r | |
309 | \r | |
310 | typedef struct {\r | |
311 | UINT32 DeviceRemovable:16;\r | |
312 | UINT32 PortPowerControlMask:16;\r | |
313 | } HcRH_DESC_B;\r | |
314 | \r | |
315 | typedef struct {\r | |
316 | UINT32 LocalPowerStat:1;\r | |
317 | UINT32 OverCurrentIndicator:1;\r | |
318 | UINT32 Reserved1:13;\r | |
319 | UINT32 DevRemoteWakeupEnable:1;\r | |
320 | UINT32 LocalPowerStatChange:1;\r | |
321 | UINT32 OverCurrentIndicatorChange:1;\r | |
322 | UINT32 Reserved2:13;\r | |
323 | UINT32 ClearRemoteWakeupEnable:1;\r | |
324 | } HcRH_STATUS;\r | |
325 | \r | |
326 | typedef struct {\r | |
327 | UINT32 CurrentConnectStat:1;\r | |
328 | UINT32 EnableStat:1;\r | |
329 | UINT32 SuspendStat:1;\r | |
330 | UINT32 OCIndicator:1;\r | |
331 | UINT32 ResetStat:1;\r | |
332 | UINT32 Reserved1:3;\r | |
333 | UINT32 PowerStat:1;\r | |
334 | UINT32 LsDeviceAttached:1;\r | |
335 | UINT32 Reserved2:6;\r | |
336 | UINT32 ConnectStatChange:1;\r | |
337 | UINT32 EnableStatChange:1;\r | |
338 | UINT32 SuspendStatChange:1;\r | |
339 | UINT32 OCIndicatorChange:1;\r | |
340 | UINT32 ResetStatChange:1;\r | |
341 | UINT32 Reserved3:11;\r | |
342 | } HcRHPORT_STATUS;\r | |
343 | \r | |
344 | typedef struct {\r | |
345 | UINT32 FSBIR:1;\r | |
346 | UINT32 FHR:1;\r | |
347 | UINT32 CGR:1;\r | |
348 | UINT32 SSDC:1;\r | |
349 | UINT32 UIT:1;\r | |
350 | UINT32 SSE:1;\r | |
351 | UINT32 PSPL:1;\r | |
352 | UINT32 PCPL:1;\r | |
353 | UINT32 Reserved0:1;\r | |
354 | UINT32 SSEP1:1;\r | |
355 | UINT32 SSEP2:1;\r | |
356 | UINT32 SSEP3:1;\r | |
357 | UINT32 Reserved1:20;\r | |
358 | } HcRESET;\r | |
359 | \r | |
360 | #pragma pack()\r | |
361 | \r | |
362 | //\r | |
363 | // Func List\r | |
364 | //\r | |
365 | /**\r | |
366 | \r | |
367 | Get OHCI operational reg value\r | |
368 | \r | |
369 | @param Ohc UHC private data\r | |
370 | @param Offset Offset of the operational reg\r | |
371 | \r | |
372 | @retval Value of the register\r | |
373 | \r | |
374 | **/\r | |
375 | UINT32\r | |
376 | OhciGetOperationalReg (\r | |
377 | IN USB_OHCI_HC_DEV *Ohc,\r | |
378 | IN UINT32 Offset\r | |
379 | );\r | |
380 | /**\r | |
381 | \r | |
382 | Set OHCI operational reg value\r | |
383 | \r | |
384 | @param Ohc UHC private data\r | |
385 | @param Offset Offset of the operational reg\r | |
386 | @param Value Value to set\r | |
387 | \r | |
388 | @retval EFI_SUCCESS Value set to the reg\r | |
389 | \r | |
390 | **/\r | |
391 | EFI_STATUS\r | |
392 | OhciSetOperationalReg (\r | |
393 | USB_OHCI_HC_DEV *Ohc,\r | |
394 | IN UINT32 Offset,\r | |
395 | IN UINT32 *Value\r | |
396 | );\r | |
397 | /**\r | |
398 | \r | |
399 | Get HcRevision reg value\r | |
400 | \r | |
401 | @param Ohc UHC private data\r | |
402 | \r | |
403 | @retval Value of the register\r | |
404 | \r | |
405 | **/\r | |
406 | \r | |
407 | \r | |
408 | UINT32\r | |
409 | OhciGetHcRevision (\r | |
410 | USB_OHCI_HC_DEV *Ohc\r | |
411 | );\r | |
412 | \r | |
413 | /**\r | |
414 | \r | |
415 | Set HcReset reg value\r | |
416 | \r | |
417 | @param Ohc UHC private data\r | |
418 | @param Field Field to set\r | |
419 | @param Value Value to set\r | |
420 | \r | |
421 | @retval EFI_SUCCESS Value set\r | |
422 | \r | |
423 | **/\r | |
424 | \r | |
425 | EFI_STATUS\r | |
426 | OhciSetHcReset (\r | |
427 | IN USB_OHCI_HC_DEV *Ohc,\r | |
428 | IN UINT32 Field,\r | |
429 | IN UINT32 Value\r | |
430 | );\r | |
431 | /**\r | |
432 | \r | |
433 | Get specific field of HcReset reg value\r | |
434 | \r | |
435 | @param Ohc UHC private data\r | |
436 | @param Field Field to get\r | |
437 | \r | |
438 | @retval Value of the field\r | |
439 | \r | |
440 | **/\r | |
441 | \r | |
442 | UINT32\r | |
443 | OhciGetHcReset (\r | |
444 | IN USB_OHCI_HC_DEV *Ohc,\r | |
445 | IN UINT32 Field\r | |
446 | );\r | |
447 | /**\r | |
448 | \r | |
449 | Set HcControl reg value\r | |
450 | \r | |
451 | @param Ohc UHC private data\r | |
452 | @param Field Field to set\r | |
453 | @param Value Value to set\r | |
454 | \r | |
455 | @retval EFI_SUCCESS Value set\r | |
456 | \r | |
457 | **/\r | |
458 | \r | |
459 | EFI_STATUS\r | |
460 | OhciSetHcControl (\r | |
461 | IN USB_OHCI_HC_DEV *Ohc,\r | |
462 | IN UINTN Field,\r | |
463 | IN UINT32 Value\r | |
464 | );\r | |
465 | /**\r | |
466 | \r | |
467 | Get specific field of HcControl reg value\r | |
468 | \r | |
469 | @param Ohc UHC private data\r | |
470 | @param Field Field to get\r | |
471 | \r | |
472 | @retval Value of the field\r | |
473 | \r | |
474 | **/\r | |
475 | \r | |
476 | \r | |
477 | UINT32\r | |
478 | OhciGetHcControl (\r | |
479 | IN USB_OHCI_HC_DEV *Ohc,\r | |
480 | IN UINTN Field\r | |
481 | );\r | |
482 | /**\r | |
483 | \r | |
484 | Set HcCommand reg value\r | |
485 | \r | |
486 | @param Ohc UHC private data\r | |
487 | @param Field Field to set\r | |
488 | @param Value Value to set\r | |
489 | \r | |
490 | @retval EFI_SUCCESS Value set\r | |
491 | \r | |
492 | **/\r | |
493 | \r | |
494 | EFI_STATUS\r | |
495 | OhciSetHcCommandStatus (\r | |
496 | IN USB_OHCI_HC_DEV *Ohc,\r | |
497 | IN UINTN Field,\r | |
498 | IN UINT32 Value\r | |
499 | );\r | |
500 | /**\r | |
501 | \r | |
502 | Get specific field of HcCommand reg value\r | |
503 | \r | |
504 | @param Ohc UHC private data\r | |
505 | @param Field Field to get\r | |
506 | \r | |
507 | @retval Value of the field\r | |
508 | \r | |
509 | **/\r | |
510 | \r | |
511 | UINT32\r | |
512 | OhciGetHcCommandStatus (\r | |
513 | IN USB_OHCI_HC_DEV *Ohc,\r | |
514 | IN UINTN Field\r | |
515 | );\r | |
516 | /**\r | |
517 | \r | |
518 | Clear specific fields of Interrupt Status\r | |
519 | \r | |
520 | @param Ohc UHC private data\r | |
521 | @param Field Field to clear\r | |
522 | \r | |
523 | @retval EFI_SUCCESS Fields cleared\r | |
524 | \r | |
525 | **/\r | |
526 | \r | |
527 | EFI_STATUS\r | |
528 | OhciClearInterruptStatus (\r | |
529 | IN USB_OHCI_HC_DEV *Ohc,\r | |
530 | IN UINTN Field\r | |
531 | );\r | |
532 | /**\r | |
533 | \r | |
534 | Get fields of HcInterrupt reg value\r | |
535 | \r | |
536 | @param Ohc UHC private data\r | |
537 | @param Field Field to get\r | |
538 | \r | |
539 | @retval Value of the field\r | |
540 | \r | |
541 | **/\r | |
542 | \r | |
543 | UINT32\r | |
544 | OhciGetHcInterruptStatus (\r | |
545 | IN USB_OHCI_HC_DEV *Ohc,\r | |
546 | IN UINTN Field\r | |
547 | );\r | |
548 | /**\r | |
549 | \r | |
550 | Set Interrupt Control reg value\r | |
551 | \r | |
552 | @param Ohc UHC private data\r | |
553 | @param StatEnable Enable or Disable\r | |
554 | @param Field Field to set\r | |
555 | @param Value Value to set\r | |
556 | \r | |
557 | @retval EFI_SUCCESS Value set\r | |
558 | \r | |
559 | **/\r | |
560 | \r | |
561 | EFI_STATUS\r | |
562 | OhciSetInterruptControl (\r | |
563 | IN USB_OHCI_HC_DEV *Ohc,\r | |
564 | IN BOOLEAN StatEnable,\r | |
565 | IN UINTN Field,\r | |
566 | IN UINT32 Value\r | |
567 | );\r | |
568 | /**\r | |
569 | \r | |
570 | Get field of HcInterruptControl reg value\r | |
571 | \r | |
572 | @param Ohc UHC private data\r | |
573 | @param Field Field to get\r | |
574 | \r | |
575 | @retval Value of the field\r | |
576 | \r | |
577 | **/\r | |
578 | \r | |
579 | UINT32\r | |
580 | OhciGetHcInterruptControl (\r | |
581 | IN USB_OHCI_HC_DEV *Ohc,\r | |
582 | IN UINTN Field\r | |
583 | );\r | |
584 | /**\r | |
585 | \r | |
586 | Set memory pointer of specific type\r | |
587 | \r | |
588 | @param Ohc UHC private data\r | |
589 | @param PointerType Type of the pointer to set\r | |
590 | @param Value Value to set\r | |
591 | \r | |
592 | @retval EFI_SUCCESS Memory pointer set\r | |
593 | \r | |
594 | **/\r | |
595 | \r | |
596 | EFI_STATUS\r | |
597 | OhciSetMemoryPointer(\r | |
598 | IN USB_OHCI_HC_DEV *Ohc,\r | |
599 | IN UINTN PointerType,\r | |
600 | IN VOID *Value\r | |
601 | );\r | |
602 | /**\r | |
603 | \r | |
604 | Get memory pointer of specific type\r | |
605 | \r | |
606 | @param Ohc UHC private data\r | |
607 | @param PointerType Type of pointer\r | |
608 | \r | |
609 | @retval Memory pointer of the specific type\r | |
610 | \r | |
611 | **/\r | |
612 | \r | |
613 | VOID *\r | |
614 | OhciGetMemoryPointer (\r | |
615 | IN USB_OHCI_HC_DEV *Ohc,\r | |
616 | IN UINTN PointerType\r | |
617 | );\r | |
618 | /**\r | |
619 | \r | |
620 | Set Frame Interval value\r | |
621 | \r | |
622 | @param Ohc UHC private data\r | |
623 | @param Field Field to set\r | |
624 | @param Value Value to set\r | |
625 | \r | |
626 | @retval EFI_SUCCESS Value set\r | |
627 | \r | |
628 | **/\r | |
629 | \r | |
630 | EFI_STATUS\r | |
631 | OhciSetFrameInterval (\r | |
632 | IN USB_OHCI_HC_DEV *Ohc,\r | |
633 | IN UINTN Field,\r | |
634 | IN UINT32 Value\r | |
635 | );\r | |
636 | /**\r | |
637 | \r | |
638 | Get field of frame interval reg value\r | |
639 | \r | |
640 | @param Ohc UHC private data\r | |
641 | @param Field Field to get\r | |
642 | \r | |
643 | @retval Value of the field\r | |
644 | \r | |
645 | **/\r | |
646 | \r | |
647 | UINT32\r | |
648 | OhciGetFrameInterval (\r | |
649 | IN USB_OHCI_HC_DEV *Ohc,\r | |
650 | IN UINTN Field\r | |
651 | );\r | |
652 | /**\r | |
653 | \r | |
654 | Set Frame Remaining reg value\r | |
655 | \r | |
656 | @param Ohc UHC private data\r | |
657 | @param Value Value to set\r | |
658 | \r | |
659 | @retval EFI_SUCCESS Value set\r | |
660 | \r | |
661 | **/\r | |
662 | \r | |
663 | EFI_STATUS\r | |
664 | OhciSetFrameRemaining (\r | |
665 | IN USB_OHCI_HC_DEV *Ohc,\r | |
666 | IN UINT32 Value\r | |
667 | );\r | |
668 | /**\r | |
669 | \r | |
670 | Get value of frame remaining reg\r | |
671 | \r | |
672 | @param Ohc UHC private data\r | |
673 | @param Field Field to get\r | |
674 | \r | |
675 | @retval Value of frame remaining reg\r | |
676 | \r | |
677 | **/\r | |
678 | UINT32\r | |
679 | OhciGetFrameRemaining (\r | |
680 | IN USB_OHCI_HC_DEV *Ohc,\r | |
681 | IN UINTN Field\r | |
682 | );\r | |
683 | /**\r | |
684 | \r | |
685 | Set frame number reg value\r | |
686 | \r | |
687 | @param Ohc UHC private data\r | |
688 | @param Value Value to set\r | |
689 | \r | |
690 | @retval EFI_SUCCESS Value set\r | |
691 | \r | |
692 | **/\r | |
693 | \r | |
694 | EFI_STATUS\r | |
695 | OhciSetFrameNumber(\r | |
696 | IN USB_OHCI_HC_DEV *Ohc,\r | |
697 | IN UINT32 Value\r | |
698 | );\r | |
699 | /**\r | |
700 | \r | |
701 | Get frame number reg value\r | |
702 | \r | |
703 | @param Ohc UHC private data\r | |
704 | \r | |
705 | @retval Value of frame number reg\r | |
706 | \r | |
707 | **/\r | |
708 | \r | |
709 | UINT32\r | |
710 | OhciGetFrameNumber (\r | |
711 | IN USB_OHCI_HC_DEV *Ohc\r | |
712 | );\r | |
713 | /**\r | |
714 | \r | |
715 | Set period start reg value\r | |
716 | \r | |
717 | @param Ohc UHC private data\r | |
718 | @param Value Value to set\r | |
719 | \r | |
720 | @retval EFI_SUCCESS Value set\r | |
721 | \r | |
722 | **/\r | |
723 | \r | |
724 | EFI_STATUS\r | |
725 | OhciSetPeriodicStart (\r | |
726 | IN USB_OHCI_HC_DEV *Ohc,\r | |
727 | IN UINT32 Value\r | |
728 | );\r | |
729 | /**\r | |
730 | \r | |
731 | Get periodic start reg value\r | |
732 | \r | |
733 | @param Ohc UHC private data\r | |
734 | \r | |
735 | @param Value of periodic start reg\r | |
736 | \r | |
737 | **/\r | |
738 | \r | |
739 | UINT32\r | |
740 | OhciGetPeriodicStart (\r | |
741 | IN USB_OHCI_HC_DEV *Ohc\r | |
742 | );\r | |
743 | /**\r | |
744 | \r | |
745 | Set Ls Threshold reg value\r | |
746 | \r | |
747 | @param Ohc UHC private data\r | |
748 | @param Value Value to set\r | |
749 | \r | |
750 | @retval EFI_SUCCESS Value set\r | |
751 | \r | |
752 | **/\r | |
753 | \r | |
754 | EFI_STATUS\r | |
755 | OhciSetLsThreshold (\r | |
756 | IN USB_OHCI_HC_DEV *Ohc,\r | |
757 | IN UINT32 Value\r | |
758 | );\r | |
759 | /**\r | |
760 | \r | |
761 | Get Ls Threshold reg value\r | |
762 | \r | |
763 | @param Ohc UHC private data\r | |
764 | \r | |
765 | @retval Value of Ls Threshold reg\r | |
766 | \r | |
767 | **/\r | |
768 | \r | |
769 | UINT32\r | |
770 | OhciGetLsThreshold (\r | |
771 | IN USB_OHCI_HC_DEV *Ohc\r | |
772 | );\r | |
773 | /**\r | |
774 | \r | |
775 | Set Root Hub Descriptor reg value\r | |
776 | \r | |
777 | @param Ohc UHC private data\r | |
778 | @param Field Field to set\r | |
779 | @param Value Value to set\r | |
780 | \r | |
781 | @retval EFI_SUCCESS Value set\r | |
782 | \r | |
783 | **/\r | |
784 | EFI_STATUS\r | |
785 | OhciSetRootHubDescriptor (\r | |
786 | IN USB_OHCI_HC_DEV *Ohc,\r | |
787 | IN UINTN Field,\r | |
788 | IN UINT32 Value\r | |
789 | );\r | |
790 | /**\r | |
791 | \r | |
792 | Get Root Hub Descriptor reg value\r | |
793 | \r | |
794 | @param Ohc UHC private data\r | |
795 | @param Field Field to get\r | |
796 | \r | |
797 | @retval Value of the field\r | |
798 | \r | |
799 | **/\r | |
800 | \r | |
801 | UINT32\r | |
802 | OhciGetRootHubDescriptor (\r | |
803 | IN USB_OHCI_HC_DEV *Ohc,\r | |
804 | IN UINTN Field\r | |
805 | );\r | |
806 | /**\r | |
807 | \r | |
808 | Set Root Hub Status reg value\r | |
809 | \r | |
810 | @param Ohc UHC private data\r | |
811 | @param Field Field to set\r | |
812 | \r | |
813 | @retval EFI_SUCCESS Value set\r | |
814 | \r | |
815 | **/\r | |
816 | \r | |
817 | EFI_STATUS\r | |
818 | OhciSetRootHubStatus (\r | |
819 | IN USB_OHCI_HC_DEV *Ohc,\r | |
820 | IN UINTN Field\r | |
821 | );\r | |
822 | /**\r | |
823 | \r | |
824 | Get Root Hub Status reg value\r | |
825 | \r | |
826 | @param Ohc UHC private data\r | |
827 | @param Field Field to get\r | |
828 | \r | |
829 | @retval Value of the field\r | |
830 | \r | |
831 | **/\r | |
832 | \r | |
833 | UINT32\r | |
834 | OhciGetRootHubStatus (\r | |
835 | IN USB_OHCI_HC_DEV *Ohc,\r | |
836 | IN UINTN Field\r | |
837 | );\r | |
838 | /**\r | |
839 | \r | |
840 | Set Root Hub Port Status reg value\r | |
841 | \r | |
842 | @param Ohc UHC private data\r | |
843 | @param Index Index of the port\r | |
844 | @param Field Field to set\r | |
845 | \r | |
846 | @retval EFI_SUCCESS Value set\r | |
847 | \r | |
848 | **/\r | |
849 | \r | |
850 | EFI_STATUS\r | |
851 | OhciSetRootHubPortStatus (\r | |
852 | IN USB_OHCI_HC_DEV *Ohc,\r | |
853 | IN UINT32 Index,\r | |
854 | IN UINTN Field\r | |
855 | );\r | |
856 | /**\r | |
857 | \r | |
858 | Get Root Hub Port Status reg value\r | |
859 | \r | |
860 | @param Ohc UHC private data\r | |
861 | @param Index Index of the port\r | |
862 | @param Field Field to get\r | |
863 | \r | |
864 | @retval Value of the field and index\r | |
865 | \r | |
866 | **/\r | |
867 | \r | |
868 | UINT32\r | |
869 | OhciReadRootHubPortStatus (\r | |
870 | IN USB_OHCI_HC_DEV *Ohc,\r | |
871 | IN UINT32 Index,\r | |
872 | IN UINTN Field\r | |
873 | );\r | |
874 | \r | |
875 | #endif\r |