[mirror_edk2.git] / SecurityPkg / Library / Tpm12DeviceLibDTpm / Tpm12Tis.c

/** @file\r
  TIS (TPM Interface Specification) functions used by TPM1.2.\r
  \r
Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution.  The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <Uefi.h>\r
#include <IndustryStandard/Tpm12.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/TimerLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/Tpm12CommandLib.h>\r
#include <Library/PcdLib.h>\r
\r
//\r
// Set structure alignment to 1-byte\r
//\r
#pragma pack (1)\r
\r
//\r
// Register set map as specified in TIS specification Chapter 10\r
//\r
typedef struct {\r
  ///\r
  /// Used to gain ownership for this particular port.\r
  ///\r
  UINT8                             Access;             // 0\r
  UINT8                             Reserved1[7];       // 1\r
  ///\r
  /// Controls interrupts.\r
  ///\r
  UINT32                            IntEnable;          // 8\r
  ///\r
  /// SIRQ vector to be used by the TPM.\r
  ///\r
  UINT8                             IntVector;          // 0ch\r
  UINT8                             Reserved2[3];       // 0dh\r
  ///\r
  /// What caused interrupt.\r
  ///\r
  UINT32                            IntSts;             // 10h\r
  ///\r
  /// Shows which interrupts are supported by that particular TPM.\r
  ///\r
  UINT32                            IntfCapability;     // 14h\r
  ///\r
  /// Status Register. Provides status of the TPM.\r
  ///\r
  UINT8                             Status;             // 18h\r
  ///\r
  /// Number of consecutive writes that can be done to the TPM.\r
  ///\r
  UINT16                            BurstCount;         // 19h\r
  UINT8                             Reserved3[9];\r
  ///\r
  /// Read or write FIFO, depending on transaction.\r
  ///\r
  UINT32                            DataFifo;           // 24h\r
  UINT8                             Reserved4[0xed8];   // 28h\r
  ///\r
  /// Vendor ID\r
  ///\r
  UINT16                            Vid;                // 0f00h\r
  ///\r
  /// Device ID\r
  ///\r
  UINT16                            Did;                // 0f02h\r
  ///\r
  /// Revision ID\r
  ///\r
  UINT8                             Rid;                // 0f04h\r
  ///\r
  /// TCG defined configuration registers.\r
  ///\r
  UINT8                             TcgDefined[0x7b];   // 0f05h\r
  ///\r
  /// Alias to I/O legacy space.\r
  ///\r
  UINT32                            LegacyAddress1;     // 0f80h\r
  ///\r
  /// Additional 8 bits for I/O legacy space extension.\r
  ///\r
  UINT32                            LegacyAddress1Ex;   // 0f84h\r
  ///\r
  /// Alias to second I/O legacy space.\r
  ///\r
  UINT32                            LegacyAddress2;     // 0f88h\r
  ///\r
  /// Additional 8 bits for second I/O legacy space extension.\r
  ///\r
  UINT32                            LegacyAddress2Ex;   // 0f8ch\r
  ///\r
  /// Vendor-defined configuration registers.\r
  ///\r
  UINT8                             VendorDefined[0x70];// 0f90h\r
} TIS_PC_REGISTERS;\r
\r
//\r
// Restore original structure alignment\r
//\r
#pragma pack ()\r
\r
//\r
// Define pointer types used to access TIS registers on PC\r
//\r
typedef TIS_PC_REGISTERS  *TIS_PC_REGISTERS_PTR;\r
\r
//\r
// Define bits of ACCESS and STATUS registers\r
//\r
\r
///\r
/// This bit is a 1 to indicate that the other bits in this register are valid.\r
///\r
#define TIS_PC_VALID                BIT7\r
///\r
/// Indicate that this locality is active.\r
///\r
#define TIS_PC_ACC_ACTIVE           BIT5\r
///\r
/// Set to 1 to indicate that this locality had the TPM taken away while\r
/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
///\r
#define TIS_PC_ACC_SEIZED           BIT4\r
///\r
/// Set to 1 to indicate that TPM MUST reset the\r
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
/// locality that is writing this bit.\r
///\r
#define TIS_PC_ACC_SEIZE            BIT3\r
///\r
/// When this bit is 1, another locality is requesting usage of the TPM.\r
///\r
#define TIS_PC_ACC_PENDIND          BIT2\r
///\r
/// Set to 1 to indicate that this locality is requesting to use TPM.\r
///\r
#define TIS_PC_ACC_RQUUSE           BIT1\r
///\r
/// A value of 1 indicates that a T/OS has not been established on the platform\r
///\r
#define TIS_PC_ACC_ESTABLISH        BIT0\r
\r
///\r
/// When this bit is 1, TPM is in the Ready state, \r
/// indicating it is ready to receive a new command.\r
///\r
#define TIS_PC_STS_READY            BIT6\r
///\r
/// Write a 1 to this bit to cause the TPM to execute that command.\r
///\r
#define TIS_PC_STS_GO               BIT5\r
///\r
/// This bit indicates that the TPM has data available as a response.\r
///\r
#define TIS_PC_STS_DATA             BIT4\r
///\r
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
///\r
#define TIS_PC_STS_EXPECT           BIT3\r
///\r
/// Writes a 1 to this bit to force the TPM to re-send the response.\r
///\r
#define TIS_PC_STS_RETRY            BIT1\r
\r
//\r
// Default TimeOut value\r
//\r
#define TIS_TIMEOUT_A               (750  * 1000)  // 750ms\r
#define TIS_TIMEOUT_B               (2000 * 1000)  // 2s\r
#define TIS_TIMEOUT_C               (750  * 1000)  // 750ms\r
#define TIS_TIMEOUT_D               (750  * 1000)  // 750ms\r
\r
//\r
// Max TPM command/reponse length\r
//\r
#define TPMCMDBUFLENGTH             1024\r
\r
/**\r
  Check whether TPM chip exist.\r
\r
  @param[in] TisReg  Pointer to TIS register.\r
\r
  @retval    TRUE    TPM chip exists.\r
  @retval    FALSE   TPM chip is not found.\r
**/\r
BOOLEAN\r
Tpm12TisPcPresenceCheck (\r
  IN      TIS_PC_REGISTERS_PTR      TisReg\r
  )\r
{\r
  UINT8                             RegRead;\r
  \r
  RegRead = MmioRead8 ((UINTN)&TisReg->Access);\r
  return (BOOLEAN)(RegRead != (UINT8)-1);\r
}\r
\r
/**\r
  Check whether the value of a TPM chip register satisfies the input BIT setting.\r
\r
  @param[in]  Register     Address port of register to be checked.\r
  @param[in]  BitSet       Check these data bits are set.\r
  @param[in]  BitClear     Check these data bits are clear.\r
  @param[in]  TimeOut      The max wait time (unit MicroSecond) when checking register.\r
\r
  @retval     EFI_SUCCESS  The register satisfies the check bit.\r
  @retval     EFI_TIMEOUT  The register can't run into the expected status in time.\r
**/\r
EFI_STATUS\r
EFIAPI\r
Tpm12TisPcWaitRegisterBits (\r
  IN      UINT8                     *Register,\r
  IN      UINT8                     BitSet,\r
  IN      UINT8                     BitClear,\r
  IN      UINT32                    TimeOut\r
  )\r
{\r
  UINT8                             RegRead;\r
  UINT32                            WaitTime;\r
\r
  for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r
    RegRead = MmioRead8 ((UINTN)Register);\r
    if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)\r
      return EFI_SUCCESS;\r
    MicroSecondDelay (30);\r
  }\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Get BurstCount by reading the burstCount field of a TIS regiger \r
  in the time of default TIS_TIMEOUT_D.\r
\r
  @param[in]  TisReg                Pointer to TIS register.\r
  @param[out] BurstCount            Pointer to a buffer to store the got BurstConut.\r
\r
  @retval     EFI_SUCCESS           Get BurstCount.\r
  @retval     EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.\r
  @retval     EFI_TIMEOUT           BurstCount can't be got in time.\r
**/\r
EFI_STATUS\r
EFIAPI\r
Tpm12TisPcReadBurstCount (\r
  IN      TIS_PC_REGISTERS_PTR      TisReg,\r
     OUT  UINT16                    *BurstCount\r
  )\r
{\r
  UINT32                            WaitTime;\r
  UINT8                             DataByte0;\r
  UINT8                             DataByte1;\r
\r
  if (BurstCount == NULL || TisReg == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  WaitTime = 0;\r
  do {\r
    //\r
    // TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,\r
    // so it needs to use MmioRead8 to read two times\r
    //\r
    DataByte0   = MmioRead8 ((UINTN)&TisReg->BurstCount);\r
    DataByte1   = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);\r
    *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);\r
    if (*BurstCount != 0) {\r
      return EFI_SUCCESS;\r
    }\r
    MicroSecondDelay (30);\r
    WaitTime += 30;\r
  } while (WaitTime < TIS_TIMEOUT_D);\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Set TPM chip to ready state by sending ready command TIS_PC_STS_READY \r
  to Status Register in time.\r
\r
  @param[in] TisReg                Pointer to TIS register.\r
\r
  @retval    EFI_SUCCESS           TPM chip enters into ready state.\r
  @retval    EFI_INVALID_PARAMETER TisReg is NULL.\r
  @retval    EFI_TIMEOUT           TPM chip can't be set to ready state in time.\r
**/\r
EFI_STATUS\r
EFIAPI\r
Tpm12TisPcPrepareCommand (\r
  IN      TIS_PC_REGISTERS_PTR      TisReg\r
  )\r
{\r
  EFI_STATUS                        Status;\r
\r
  if (TisReg == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
  Status = Tpm12TisPcWaitRegisterBits (\r
             &TisReg->Status,\r
             TIS_PC_STS_READY,\r
             0,\r
             TIS_TIMEOUT_B\r
             );\r
  return Status;\r
}\r
\r
/**\r
  Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE \r
  to ACCESS Register in the time of default TIS_TIMEOUT_A.\r
\r
  @param[in] TisReg                Pointer to TIS register.\r
\r
  @retval    EFI_SUCCESS           Get the control of TPM chip.\r
  @retval    EFI_INVALID_PARAMETER TisReg is NULL.\r
  @retval    EFI_NOT_FOUND         TPM chip doesn't exit.\r
  @retval    EFI_TIMEOUT           Can't get the TPM control in time.\r
**/\r
EFI_STATUS\r
EFIAPI\r
Tpm12TisPcRequestUseTpm (\r
  IN      TIS_PC_REGISTERS_PTR      TisReg\r
  )\r
{\r
  EFI_STATUS                        Status;\r
  \r
  if (TisReg == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  \r
  if (!Tpm12TisPcPresenceCheck (TisReg)) {\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);\r
  Status = Tpm12TisPcWaitRegisterBits (\r
             &TisReg->Access,\r
             (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),\r
             0,\r
             TIS_TIMEOUT_A\r
             );\r
  return Status;\r
}\r
\r
/**\r
  Send a command to TPM for execution and return response data.\r
\r
  @param[in]      TisReg        TPM register space base address.  \r
  @param[in]      BufferIn      Buffer for command data.  \r
  @param[in]      SizeIn        Size of command data.  \r
  @param[in, out] BufferOut     Buffer for response data.  \r
  @param[in, out] SizeOut       Size of response data.  \r
 \r
  @retval EFI_SUCCESS           Operation completed successfully.\r
  @retval EFI_TIMEOUT           The register can't run into the expected status in time.\r
  @retval EFI_BUFFER_TOO_SMALL  Response data buffer is too small.\r
  @retval EFI_DEVICE_ERROR      Unexpected device behavior.\r
  @retval EFI_UNSUPPORTED       Unsupported TPM version\r
\r
**/\r
EFI_STATUS\r
Tpm12TisTpmCommand (\r
  IN     TIS_PC_REGISTERS_PTR       TisReg,\r
  IN     UINT8                      *BufferIn,\r
  IN     UINT32                     SizeIn,\r
  IN OUT UINT8                      *BufferOut,\r
  IN OUT UINT32                     *SizeOut\r
  )\r
{\r
  EFI_STATUS                        Status;\r
  UINT16                            BurstCount;\r
  UINT32                            Index;\r
  UINT32                            TpmOutSize;\r
  UINT16                            Data16;\r
  UINT32                            Data32;\r
\r
  DEBUG_CODE (\r
    UINTN  DebugSize;\r
\r
    DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand Send - "));\r
    if (SizeIn > 0x100) {\r
      DebugSize = 0x40;\r
    } else {\r
      DebugSize = SizeIn;\r
    }\r
    for (Index = 0; Index < DebugSize; Index++) {\r
      DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));\r
    }\r
    if (DebugSize != SizeIn) {\r
      DEBUG ((EFI_D_INFO, "...... "));\r
      for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r
        DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));\r
      }\r
    }\r
    DEBUG ((EFI_D_INFO, "\n"));\r
  );\r
  TpmOutSize = 0;\r
\r
  Status = Tpm12TisPcPrepareCommand (TisReg);\r
  if (EFI_ERROR (Status)){\r
    DEBUG ((DEBUG_ERROR, "Tpm12 is not ready for command!\n"));\r
    return Status;\r
  }\r
  //\r
  // Send the command data to Tpm\r
  //\r
  Index = 0;\r
  while (Index < SizeIn) {\r
    Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r
    if (EFI_ERROR (Status)) {\r
      Status = EFI_TIMEOUT;\r
      goto Exit;\r
    }\r
    for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {\r
      MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));\r
      Index++;\r
    }\r
  }\r
  //\r
  // Check the Tpm status STS_EXPECT change from 1 to 0\r
  //\r
  Status = Tpm12TisPcWaitRegisterBits (\r
             &TisReg->Status,\r
             (UINT8) TIS_PC_VALID,\r
             TIS_PC_STS_EXPECT,\r
             TIS_TIMEOUT_C\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "Tpm12 The send buffer too small!\n"));\r
    Status = EFI_BUFFER_TOO_SMALL;\r
    goto Exit;\r
  }\r
  //\r
  // Executed the TPM command and waiting for the response data ready\r
  //\r
  MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);\r
  Status = Tpm12TisPcWaitRegisterBits (\r
             &TisReg->Status,\r
             (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),\r
             0,\r
             TIS_TIMEOUT_B\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "Wait for Tpm12 response data time out!!\n"));\r
    Status = EFI_TIMEOUT;\r
    goto Exit;\r
  }\r
  //\r
  // Get response data header\r
  //\r
  Index = 0;\r
  BurstCount = 0;\r
  while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {\r
    Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r
    if (EFI_ERROR (Status)) {\r
      Status = EFI_TIMEOUT;\r
      goto Exit;\r
    }\r
    for (; BurstCount > 0; BurstCount--) {\r
      *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
      Index++;\r
      if (Index == sizeof (TPM_RSP_COMMAND_HDR)) break;\r
    }\r
  }\r
  DEBUG_CODE (\r
    DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand ReceiveHeader - "));\r
    for (Index = 0; Index < sizeof (TPM_RSP_COMMAND_HDR); Index++) {\r
      DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));\r
    }\r
    DEBUG ((EFI_D_INFO, "\n"));\r
  );\r
  //\r
  // Check the reponse data header (tag,parasize and returncode )\r
  //\r
  CopyMem (&Data16, BufferOut, sizeof (UINT16));\r
  if (SwapBytes16 (Data16) != TPM_TAG_RSP_COMMAND) {\r
    DEBUG ((EFI_D_ERROR, "TPM12: TPM_ST_RSP error - %x\n", TPM_TAG_RSP_COMMAND));\r
    Status = EFI_UNSUPPORTED;\r
    goto Exit;\r
  }\r
\r
  CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r
  TpmOutSize  = SwapBytes32 (Data32);\r
  if (*SizeOut < TpmOutSize) {\r
    Status = EFI_BUFFER_TOO_SMALL;\r
    goto Exit;\r
  }\r
  *SizeOut = TpmOutSize;\r
  //\r
  // Continue reading the remaining data\r
  //\r
  while ( Index < TpmOutSize ) {\r
    for (; BurstCount > 0; BurstCount--) {\r
      *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
      Index++;\r
      if (Index == TpmOutSize) {\r
        Status = EFI_SUCCESS;\r
        goto Exit;\r
      }\r
    }\r
    Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r
    if (EFI_ERROR (Status)) {\r
      Status = EFI_TIMEOUT;\r
      goto Exit;\r
    }\r
  }\r
Exit:\r
  DEBUG_CODE (\r
    DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand Receive - "));\r
    for (Index = 0; Index < TpmOutSize; Index++) {\r
      DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));\r
    }\r
    DEBUG ((EFI_D_INFO, "\n"));\r
  );\r
  MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
  return Status;\r
}\r
\r
/**\r
  This service enables the sending of commands to the TPM12.\r
\r
  @param[in]      InputParameterBlockSize  Size of the TPM12 input parameter block.\r
  @param[in]      InputParameterBlock      Pointer to the TPM12 input parameter block.\r
  @param[in,out]  OutputParameterBlockSize Size of the TPM12 output parameter block.\r
  @param[in]      OutputParameterBlock     Pointer to the TPM12 output parameter block.\r
\r
  @retval EFI_SUCCESS            The command byte stream was successfully sent to the device and a response was successfully received.\r
  @retval EFI_DEVICE_ERROR       The command was not successfully sent to the device or a response was not successfully received from the device.\r
  @retval EFI_BUFFER_TOO_SMALL   The output parameter block is too small. \r
**/\r
EFI_STATUS\r
EFIAPI\r
Tpm12SubmitCommand (\r
  IN UINT32            InputParameterBlockSize,\r
  IN UINT8             *InputParameterBlock,\r
  IN OUT UINT32        *OutputParameterBlockSize,\r
  IN UINT8             *OutputParameterBlock\r
  )\r
{\r
  return Tpm12TisTpmCommand (\r
           (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r
           InputParameterBlock,\r
           InputParameterBlockSize,\r
           OutputParameterBlock,\r
           OutputParameterBlockSize\r
           );\r
}\r
\r
/**\r
  This service requests use TPM12.\r
\r
  @retval EFI_SUCCESS      Get the control of TPM12 chip.\r
  @retval EFI_NOT_FOUND    TPM12 not found.\r
  @retval EFI_DEVICE_ERROR Unexpected device behavior.\r
**/\r
EFI_STATUS\r
EFIAPI\r
Tpm12RequestUseTpm (\r
  VOID\r
  )\r
{\r
  return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
}\r
Commit	Line	Data
c1d93242 JY	1	/** @file\r
	2	TIS (TPM Interface Specification) functions used by TPM1.2.\r
	3	\r
	4	Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
	5	This program and the accompanying materials \r
	6	are licensed and made available under the terms and conditions of the BSD License \r
	7	which accompanies this distribution. The full text of the license may be found at \r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#include <Uefi.h>\r
	16	#include <IndustryStandard/Tpm12.h>\r
	17	#include <Library/BaseLib.h>\r
	18	#include <Library/BaseMemoryLib.h>\r
	19	#include <Library/IoLib.h>\r
	20	#include <Library/TimerLib.h>\r
	21	#include <Library/DebugLib.h>\r
	22	#include <Library/Tpm12CommandLib.h>\r
	23	#include <Library/PcdLib.h>\r
	24	\r
	25	//\r
	26	// Set structure alignment to 1-byte\r
	27	//\r
	28	#pragma pack (1)\r
	29	\r
	30	//\r
	31	// Register set map as specified in TIS specification Chapter 10\r
	32	//\r
	33	typedef struct {\r
	34	///\r
	35	/// Used to gain ownership for this particular port.\r
	36	///\r
	37	UINT8 Access; // 0\r
	38	UINT8 Reserved1[7]; // 1\r
	39	///\r
	40	/// Controls interrupts.\r
	41	///\r
	42	UINT32 IntEnable; // 8\r
	43	///\r
	44	/// SIRQ vector to be used by the TPM.\r
	45	///\r
	46	UINT8 IntVector; // 0ch\r
	47	UINT8 Reserved2[3]; // 0dh\r
	48	///\r
	49	/// What caused interrupt.\r
	50	///\r
	51	UINT32 IntSts; // 10h\r
	52	///\r
	53	/// Shows which interrupts are supported by that particular TPM.\r
	54	///\r
	55	UINT32 IntfCapability; // 14h\r
	56	///\r
	57	/// Status Register. Provides status of the TPM.\r
	58	///\r
	59	UINT8 Status; // 18h\r
	60	///\r
	61	/// Number of consecutive writes that can be done to the TPM.\r
	62	///\r
	63	UINT16 BurstCount; // 19h\r
	64	UINT8 Reserved3[9];\r
65	///\r
66	/// Read or write FIFO, depending on transaction.\r
67	///\r
68	UINT32 DataFifo; // 24h\r
69	UINT8 Reserved4[0xed8]; // 28h\r
70	///\r
71	/// Vendor ID\r
72	///\r
73	UINT16 Vid; // 0f00h\r
74	///\r
75	/// Device ID\r
76	///\r
77	UINT16 Did; // 0f02h\r
78	///\r
79	/// Revision ID\r
80	///\r
81	UINT8 Rid; // 0f04h\r
82	///\r
83	/// TCG defined configuration registers.\r
84	///\r
85	UINT8 TcgDefined[0x7b]; // 0f05h\r
86	///\r
87	/// Alias to I/O legacy space.\r
88	///\r
89	UINT32 LegacyAddress1; // 0f80h\r
90	///\r
91	/// Additional 8 bits for I/O legacy space extension.\r
92	///\r
93	UINT32 LegacyAddress1Ex; // 0f84h\r
94	///\r
95	/// Alias to second I/O legacy space.\r
96	///\r
97	UINT32 LegacyAddress2; // 0f88h\r
98	///\r
99	/// Additional 8 bits for second I/O legacy space extension.\r
100	///\r
101	UINT32 LegacyAddress2Ex; // 0f8ch\r
102	///\r
103	/// Vendor-defined configuration registers.\r
104	///\r
105	UINT8 VendorDefined[0x70];// 0f90h\r
106	} TIS_PC_REGISTERS;\r
107	\r
108	//\r
109	// Restore original structure alignment\r
110	//\r
111	#pragma pack ()\r
112	\r
113	//\r
114	// Define pointer types used to access TIS registers on PC\r
115	//\r
116	typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r
117	\r
118	//\r
119	// Define bits of ACCESS and STATUS registers\r
120	//\r
121	\r
122	///\r
123	/// This bit is a 1 to indicate that the other bits in this register are valid.\r
124	///\r
125	#define TIS_PC_VALID BIT7\r
126	///\r
127	/// Indicate that this locality is active.\r
128	///\r
129	#define TIS_PC_ACC_ACTIVE BIT5\r
130	///\r
131	/// Set to 1 to indicate that this locality had the TPM taken away while\r
132	/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
133	///\r
134	#define TIS_PC_ACC_SEIZED BIT4\r
135	///\r
136	/// Set to 1 to indicate that TPM MUST reset the\r
137	/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
138	/// locality that is writing this bit.\r
139	///\r
140	#define TIS_PC_ACC_SEIZE BIT3\r
141	///\r
142	/// When this bit is 1, another locality is requesting usage of the TPM.\r
143	///\r
144	#define TIS_PC_ACC_PENDIND BIT2\r
145	///\r
146	/// Set to 1 to indicate that this locality is requesting to use TPM.\r
147	///\r
148	#define TIS_PC_ACC_RQUUSE BIT1\r
149	///\r
150	/// A value of 1 indicates that a T/OS has not been established on the platform\r
151	///\r
152	#define TIS_PC_ACC_ESTABLISH BIT0\r
153	\r
154	///\r
155	/// When this bit is 1, TPM is in the Ready state, \r
156	/// indicating it is ready to receive a new command.\r
157	///\r
158	#define TIS_PC_STS_READY BIT6\r
159	///\r
160	/// Write a 1 to this bit to cause the TPM to execute that command.\r
161	///\r
162	#define TIS_PC_STS_GO BIT5\r
163	///\r
164	/// This bit indicates that the TPM has data available as a response.\r
165	///\r
166	#define TIS_PC_STS_DATA BIT4\r
167	///\r
168	/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
169	///\r
170	#define TIS_PC_STS_EXPECT BIT3\r
171	///\r
172	/// Writes a 1 to this bit to force the TPM to re-send the response.\r
173	///\r
174	#define TIS_PC_STS_RETRY BIT1\r
175	\r
176	//\r
177	// Default TimeOut value\r
178	//\r
179	#define TIS_TIMEOUT_A (750 * 1000) // 750ms\r
180	#define TIS_TIMEOUT_B (2000 * 1000) // 2s\r
181	#define TIS_TIMEOUT_C (750 * 1000) // 750ms\r
182	#define TIS_TIMEOUT_D (750 * 1000) // 750ms\r
183	\r
184	//\r
185	// Max TPM command/reponse length\r
186	//\r
187	#define TPMCMDBUFLENGTH 1024\r
188	\r
189	/**\r
190	Check whether TPM chip exist.\r
191	\r
192	@param[in] TisReg Pointer to TIS register.\r
193	\r
194	@retval TRUE TPM chip exists.\r
195	@retval FALSE TPM chip is not found.\r
196	**/\r
197	BOOLEAN\r
198	Tpm12TisPcPresenceCheck (\r
199	IN TIS_PC_REGISTERS_PTR TisReg\r
200	)\r
201	{\r
202	UINT8 RegRead;\r
203	\r
204	RegRead = MmioRead8 ((UINTN)&TisReg->Access);\r
205	return (BOOLEAN)(RegRead != (UINT8)-1);\r
206	}\r
207	\r
208	/**\r
209	Check whether the value of a TPM chip register satisfies the input BIT setting.\r
210	\r
211	@param[in] Register Address port of register to be checked.\r
212	@param[in] BitSet Check these data bits are set.\r
213	@param[in] BitClear Check these data bits are clear.\r
214	@param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r
215	\r
216	@retval EFI_SUCCESS The register satisfies the check bit.\r
217	@retval EFI_TIMEOUT The register can't run into the expected status in time.\r
218	**/\r
219	EFI_STATUS\r
220	EFIAPI\r
221	Tpm12TisPcWaitRegisterBits (\r
222	IN UINT8 *Register,\r
223	IN UINT8 BitSet,\r
224	IN UINT8 BitClear,\r
225	IN UINT32 TimeOut\r
226	)\r
227	{\r
228	UINT8 RegRead;\r
229	UINT32 WaitTime;\r
230	\r
231	for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r
232	RegRead = MmioRead8 ((UINTN)Register);\r
233	if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)\r
234	return EFI_SUCCESS;\r
235	MicroSecondDelay (30);\r
236	}\r
237	return EFI_TIMEOUT;\r
238	}\r
239	\r
240	/**\r
241	Get BurstCount by reading the burstCount field of a TIS regiger \r
242	in the time of default TIS_TIMEOUT_D.\r
243	\r
244	@param[in] TisReg Pointer to TIS register.\r
245	@param[out] BurstCount Pointer to a buffer to store the got BurstConut.\r
246	\r
247	@retval EFI_SUCCESS Get BurstCount.\r
248	@retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.\r
249	@retval EFI_TIMEOUT BurstCount can't be got in time.\r
250	**/\r
251	EFI_STATUS\r
252	EFIAPI\r
253	Tpm12TisPcReadBurstCount (\r
254	IN TIS_PC_REGISTERS_PTR TisReg,\r
255	OUT UINT16 *BurstCount\r
256	)\r
257	{\r
258	UINT32 WaitTime;\r
259	UINT8 DataByte0;\r
260	UINT8 DataByte1;\r
261	\r
262	if (BurstCount == NULL \|\| TisReg == NULL) {\r
263	return EFI_INVALID_PARAMETER;\r
264	}\r
265	\r
266	WaitTime = 0;\r
267	do {\r
268	//\r
269	// TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,\r
270	// so it needs to use MmioRead8 to read two times\r
271	//\r
272	DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);\r
273	DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);\r
274	*BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);\r
275	if (*BurstCount != 0) {\r
276	return EFI_SUCCESS;\r
277	}\r
278	MicroSecondDelay (30);\r
279	WaitTime += 30;\r
280	} while (WaitTime < TIS_TIMEOUT_D);\r
281	\r
282	return EFI_TIMEOUT;\r
283	}\r
284	\r
285	/**\r
286	Set TPM chip to ready state by sending ready command TIS_PC_STS_READY \r
287	to Status Register in time.\r
288	\r
289	@param[in] TisReg Pointer to TIS register.\r
290	\r
291	@retval EFI_SUCCESS TPM chip enters into ready state.\r
292	@retval EFI_INVALID_PARAMETER TisReg is NULL.\r
293	@retval EFI_TIMEOUT TPM chip can't be set to ready state in time.\r
294	**/\r
295	EFI_STATUS\r
296	EFIAPI\r
297	Tpm12TisPcPrepareCommand (\r
298	IN TIS_PC_REGISTERS_PTR TisReg\r
299	)\r
300	{\r
301	EFI_STATUS Status;\r
302	\r
303	if (TisReg == NULL) {\r
304	return EFI_INVALID_PARAMETER;\r
305	}\r
306	\r
307	MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
308	Status = Tpm12TisPcWaitRegisterBits (\r
309	&TisReg->Status,\r
310	TIS_PC_STS_READY,\r
311	0,\r
312	TIS_TIMEOUT_B\r
313	);\r
314	return Status;\r
315	}\r
316	\r
317	/**\r
318	Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE \r
319	to ACCESS Register in the time of default TIS_TIMEOUT_A.\r
320	\r
321	@param[in] TisReg Pointer to TIS register.\r
322	\r
323	@retval EFI_SUCCESS Get the control of TPM chip.\r
324	@retval EFI_INVALID_PARAMETER TisReg is NULL.\r
325	@retval EFI_NOT_FOUND TPM chip doesn't exit.\r
326	@retval EFI_TIMEOUT Can't get the TPM control in time.\r
327	**/\r
328	EFI_STATUS\r
329	EFIAPI\r
330	Tpm12TisPcRequestUseTpm (\r
331	IN TIS_PC_REGISTERS_PTR TisReg\r
332	)\r
333	{\r
334	EFI_STATUS Status;\r
335	\r
336	if (TisReg == NULL) {\r
337	return EFI_INVALID_PARAMETER;\r
338	}\r
339	\r
340	if (!Tpm12TisPcPresenceCheck (TisReg)) {\r
341	return EFI_NOT_FOUND;\r
342	}\r
343	\r
344	MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);\r
345	Status = Tpm12TisPcWaitRegisterBits (\r
346	&TisReg->Access,\r
347	(UINT8)(TIS_PC_ACC_ACTIVE \|TIS_PC_VALID),\r
348	0,\r
349	TIS_TIMEOUT_A\r
350	);\r
351	return Status;\r
352	}\r
353	\r
354	/**\r
355	Send a command to TPM for execution and return response data.\r
356	\r
357	@param[in] TisReg TPM register space base address. \r
358	@param[in] BufferIn Buffer for command data. \r
359	@param[in] SizeIn Size of command data. \r
360	@param[in, out] BufferOut Buffer for response data. \r
361	@param[in, out] SizeOut Size of response data. \r
362	\r
363	@retval EFI_SUCCESS Operation completed successfully.\r
364	@retval EFI_TIMEOUT The register can't run into the expected status in time.\r
365	@retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r
366	@retval EFI_DEVICE_ERROR Unexpected device behavior.\r
367	@retval EFI_UNSUPPORTED Unsupported TPM version\r
368	\r
369	**/\r
370	EFI_STATUS\r
371	Tpm12TisTpmCommand (\r
372	IN TIS_PC_REGISTERS_PTR TisReg,\r
373	IN UINT8 *BufferIn,\r
374	IN UINT32 SizeIn,\r
375	IN OUT UINT8 *BufferOut,\r
376	IN OUT UINT32 *SizeOut\r
377	)\r
378	{\r
379	EFI_STATUS Status;\r
380	UINT16 BurstCount;\r
381	UINT32 Index;\r
382	UINT32 TpmOutSize;\r
383	UINT16 Data16;\r
384	UINT32 Data32;\r
385	\r
386	DEBUG_CODE (\r
387	UINTN DebugSize;\r
388	\r
389	DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand Send - "));\r
390	if (SizeIn > 0x100) {\r
391	DebugSize = 0x40;\r
392	} else {\r
393	DebugSize = SizeIn;\r
394	}\r
395	for (Index = 0; Index < DebugSize; Index++) {\r
396	DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));\r
397	}\r
398	if (DebugSize != SizeIn) {\r
399	DEBUG ((EFI_D_INFO, "...... "));\r
400	for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r
401	DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));\r
402	}\r
403	}\r
404	DEBUG ((EFI_D_INFO, "\n"));\r
405	);\r
406	TpmOutSize = 0;\r
407	\r
408	Status = Tpm12TisPcPrepareCommand (TisReg);\r
409	if (EFI_ERROR (Status)){\r
410	DEBUG ((DEBUG_ERROR, "Tpm12 is not ready for command!\n"));\r
411	return Status;\r
412	}\r
413	//\r
414	// Send the command data to Tpm\r
415	//\r
416	Index = 0;\r
417	while (Index < SizeIn) {\r
418	Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r
419	if (EFI_ERROR (Status)) {\r
420	Status = EFI_TIMEOUT;\r
421	goto Exit;\r
422	}\r
423	for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {\r
424	MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));\r
425	Index++;\r
426	}\r
427	}\r
428	//\r
429	// Check the Tpm status STS_EXPECT change from 1 to 0\r
430	//\r
431	Status = Tpm12TisPcWaitRegisterBits (\r
432	&TisReg->Status,\r
433	(UINT8) TIS_PC_VALID,\r
434	TIS_PC_STS_EXPECT,\r
435	TIS_TIMEOUT_C\r
436	);\r
437	if (EFI_ERROR (Status)) {\r
438	DEBUG ((DEBUG_ERROR, "Tpm12 The send buffer too small!\n"));\r
439	Status = EFI_BUFFER_TOO_SMALL;\r
440	goto Exit;\r
441	}\r
442	//\r
443	// Executed the TPM command and waiting for the response data ready\r
444	//\r
445	MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);\r
446	Status = Tpm12TisPcWaitRegisterBits (\r
447	&TisReg->Status,\r
448	(UINT8) (TIS_PC_VALID \| TIS_PC_STS_DATA),\r
449	0,\r
450	TIS_TIMEOUT_B\r
451	);\r
452	if (EFI_ERROR (Status)) {\r
453	DEBUG ((DEBUG_ERROR, "Wait for Tpm12 response data time out!!\n"));\r
454	Status = EFI_TIMEOUT;\r
455	goto Exit;\r
456	}\r
457	//\r
458	// Get response data header\r
459	//\r
460	Index = 0;\r
461	BurstCount = 0;\r
462	while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {\r
463	Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r
464	if (EFI_ERROR (Status)) {\r
465	Status = EFI_TIMEOUT;\r
466	goto Exit;\r
467	}\r
468	for (; BurstCount > 0; BurstCount--) {\r
469	*(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
470	Index++;\r
471	if (Index == sizeof (TPM_RSP_COMMAND_HDR)) break;\r
472	}\r
473	}\r
474	DEBUG_CODE (\r
475	DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand ReceiveHeader - "));\r
476	for (Index = 0; Index < sizeof (TPM_RSP_COMMAND_HDR); Index++) {\r
477	DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));\r
478	}\r
479	DEBUG ((EFI_D_INFO, "\n"));\r
480	);\r
481	//\r
482	// Check the reponse data header (tag,parasize and returncode )\r
483	//\r
484	CopyMem (&Data16, BufferOut, sizeof (UINT16));\r
485	if (SwapBytes16 (Data16) != TPM_TAG_RSP_COMMAND) {\r
486	DEBUG ((EFI_D_ERROR, "TPM12: TPM_ST_RSP error - %x\n", TPM_TAG_RSP_COMMAND));\r
487	Status = EFI_UNSUPPORTED;\r
488	goto Exit;\r
489	}\r
490	\r
491	CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r
492	TpmOutSize = SwapBytes32 (Data32);\r
493	if (*SizeOut < TpmOutSize) {\r
494	Status = EFI_BUFFER_TOO_SMALL;\r
495	goto Exit;\r
496	}\r
497	*SizeOut = TpmOutSize;\r
498	//\r
499	// Continue reading the remaining data\r
500	//\r
501	while ( Index < TpmOutSize ) {\r
502	for (; BurstCount > 0; BurstCount--) {\r
503	*(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
504	Index++;\r
505	if (Index == TpmOutSize) {\r
506	Status = EFI_SUCCESS;\r
507	goto Exit;\r
508	}\r
509	}\r
510	Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r
511	if (EFI_ERROR (Status)) {\r
512	Status = EFI_TIMEOUT;\r
513	goto Exit;\r
514	}\r
515	}\r
516	Exit:\r
517	DEBUG_CODE (\r
518	DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand Receive - "));\r
519	for (Index = 0; Index < TpmOutSize; Index++) {\r
520	DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));\r
521	}\r
522	DEBUG ((EFI_D_INFO, "\n"));\r
523	);\r
524	MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
525	return Status;\r
526	}\r
527	\r
528	/**\r
529	This service enables the sending of commands to the TPM12.\r
530	\r
531	@param[in] InputParameterBlockSize Size of the TPM12 input parameter block.\r
532	@param[in] InputParameterBlock Pointer to the TPM12 input parameter block.\r
533	@param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block.\r
534	@param[in] OutputParameterBlock Pointer to the TPM12 output parameter block.\r
535	\r
536	@retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.\r
537	@retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.\r
538	@retval EFI_BUFFER_TOO_SMALL The output parameter block is too small. \r
539	**/\r
540	EFI_STATUS\r
541	EFIAPI\r
542	Tpm12SubmitCommand (\r
543	IN UINT32 InputParameterBlockSize,\r
544	IN UINT8 *InputParameterBlock,\r
545	IN OUT UINT32 *OutputParameterBlockSize,\r
546	IN UINT8 *OutputParameterBlock\r
547	)\r
548	{\r
549	return Tpm12TisTpmCommand (\r
550	(TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r
551	InputParameterBlock,\r
552	InputParameterBlockSize,\r
553	OutputParameterBlock,\r
554	OutputParameterBlockSize\r
555	);\r
556	}\r
557	\r
558	/**\r
559	This service requests use TPM12.\r
560	\r
561	@retval EFI_SUCCESS Get the control of TPM12 chip.\r
562	@retval EFI_NOT_FOUND TPM12 not found.\r
563	@retval EFI_DEVICE_ERROR Unexpected device behavior.\r
564	**/\r
565	EFI_STATUS\r
566	EFIAPI\r
567	Tpm12RequestUseTpm (\r
568	VOID\r
569	)\r
570	{\r
571	return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
572	}\r