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SecurityPkg: Add TPM PTP support in TPM2 device lib.
[mirror_edk2.git] / SecurityPkg / Library / Tpm2DeviceLibDTpm / Tpm2Ptp.c
CommitLineData
79e748cf
JY		 1/** @file\r
2 PTP (Platform TPM Profile) CRB (Command Response Buffer) interface used by dTPM2.0 library.\r
3\r
4Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
5This program and the accompanying materials\r
6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include <IndustryStandard/Tpm20.h>\r
16\r
17#include <Library/BaseLib.h>\r
18#include <Library/BaseMemoryLib.h>\r
19#include <Library/IoLib.h>\r
20#include <Library/TimerLib.h>\r
21#include <Library/DebugLib.h>\r
22#include <Library/Tpm2DeviceLib.h>\r
23#include <Library/PcdLib.h>\r
24\r
25#include <IndustryStandard/TpmPtp.h>\r
26#include <IndustryStandard/TpmTis.h>\r
27\r
28typedef enum {\r
29 PtpInterfaceTis,\r
30 PtpInterfaceFifo,\r
31 PtpInterfaceCrb,\r
32 PtpInterfaceMax,\r
33} PTP_INTERFACE_TYPE;\r
34\r
35//\r
36// Execution of the command may take from several seconds to minutes for certain\r
37// commands, such as key generation.\r
38//\r
39#define PTP_TIMEOUT_MAX (90000 * 1000) // 90s\r
40\r
41//\r
42// Max TPM command/reponse length\r
43//\r
44#define TPMCMDBUFLENGTH 0x500\r
45\r
46/**\r
47 Check whether TPM PTP register exist.\r
48\r
49 @param[in] Reg Pointer to PTP register.\r
50\r
51 @retval TRUE TPM PTP exists.\r
52 @retval FALSE TPM PTP is not found.\r
53**/\r
54BOOLEAN\r
55IsPtpPresence (\r
56 IN VOID *Reg\r
57 )\r
58{\r
59 UINT8 RegRead;\r
60\r
61 RegRead = MmioRead8 ((UINTN)Reg);\r
62 if (RegRead == 0xFF) {\r
63 //\r
64 // No TPM chip\r
65 //\r
66 return FALSE;\r
67 }\r
68 return TRUE;\r
69}\r
70\r
71/**\r
72 Check whether the value of a TPM chip register satisfies the input BIT setting.\r
73\r
74 @param[in] Register Address port of register to be checked.\r
75 @param[in] BitSet Check these data bits are set.\r
76 @param[in] BitClear Check these data bits are clear.\r
77 @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r
78\r
79 @retval EFI_SUCCESS The register satisfies the check bit.\r
80 @retval EFI_TIMEOUT The register can't run into the expected status in time.\r
81**/\r
82EFI_STATUS\r
83PtpCrbWaitRegisterBits (\r
84 IN UINT32 *Register,\r
85 IN UINT32 BitSet,\r
86 IN UINT32 BitClear,\r
87 IN UINT32 TimeOut\r
88 )\r
89{\r
90 UINT32 RegRead;\r
91 UINT32 WaitTime;\r
92\r
93 for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r
94 RegRead = MmioRead32 ((UINTN)Register);\r
95 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {\r
96 return EFI_SUCCESS;\r
97 }\r
98 MicroSecondDelay (30);\r
99 }\r
100 return EFI_TIMEOUT;\r
101}\r
102\r
103/**\r
104 Get the control of TPM chip.\r
105\r
106 @param[in] CrbReg Pointer to CRB register.\r
107\r
108 @retval EFI_SUCCESS Get the control of TPM chip.\r
109 @retval EFI_INVALID_PARAMETER CrbReg is NULL.\r
110 @retval EFI_NOT_FOUND TPM chip doesn't exit.\r
111 @retval EFI_TIMEOUT Can't get the TPM control in time.\r
112**/\r
113EFI_STATUS\r
114PtpCrbRequestUseTpm (\r
115 IN PTP_CRB_REGISTERS_PTR CrbReg\r
116 )\r
117{\r
118 EFI_STATUS Status;\r
119\r
120 if (!IsPtpPresence (CrbReg)) {\r
121 return EFI_NOT_FOUND;\r
122 }\r
123\r
124 MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);\r
125 Status = PtpCrbWaitRegisterBits (\r
126 &CrbReg->LocalityStatus,\r
127 PTP_CRB_LOCALITY_STATUS_GRANTED,\r
128 0,\r
129 PTP_TIMEOUT_A\r
130 );\r
131 return Status;\r
132}\r
133\r
134/**\r
135 Send a command to TPM for execution and return response data.\r
136\r
137 @param[in] CrbReg TPM register space base address.\r
138 @param[in] BufferIn Buffer for command data.\r
139 @param[in] SizeIn Size of command data.\r
140 @param[in, out] BufferOut Buffer for response data.\r
141 @param[in, out] SizeOut Size of response data.\r
142\r
143 @retval EFI_SUCCESS Operation completed successfully.\r
144 @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r
145 @retval EFI_DEVICE_ERROR Unexpected device behavior.\r
146 @retval EFI_UNSUPPORTED Unsupported TPM version\r
147\r
148**/\r
149EFI_STATUS\r
150PtpCrbTpmCommand (\r
151 IN PTP_CRB_REGISTERS_PTR CrbReg,\r
152 IN UINT8 *BufferIn,\r
153 IN UINT32 SizeIn,\r
154 IN OUT UINT8 *BufferOut,\r
155 IN OUT UINT32 *SizeOut\r
156 )\r
157{\r
158 EFI_STATUS Status;\r
159 UINT32 Index;\r
160 UINT32 TpmOutSize;\r
161 UINT16 Data16;\r
162 UINT32 Data32;\r
163\r
164 DEBUG_CODE (\r
165 UINTN DebugSize;\r
166\r
167 DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand Send - "));\r
168 if (SizeIn > 0x100) {\r
169 DebugSize = 0x40;\r
170 } else {\r
171 DebugSize = SizeIn;\r
172 }\r
173 for (Index = 0; Index < DebugSize; Index++) {\r
174 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r
175 }\r
176 if (DebugSize != SizeIn) {\r
177 DEBUG ((EFI_D_VERBOSE, "...... "));\r
178 for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r
179 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r
180 }\r
181 }\r
182 DEBUG ((EFI_D_VERBOSE, "\n"));\r
183 );\r
184 TpmOutSize = 0;\r
185\r
186 //\r
187 // STEP 0:\r
188 // Ready is any time the TPM is ready to receive a command, following a write\r
189 // of 1 by software to Request.cmdReady, as indicated by the Status field\r
190 // being cleared to 0.\r
191 //\r
192 MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);\r
193 Status = PtpCrbWaitRegisterBits (\r
194 &CrbReg->CrbControlRequest,\r
195 0,\r
196 PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY,\r
197 PTP_TIMEOUT_C\r
198 );\r
199 if (EFI_ERROR (Status)) {\r
200 Status = EFI_DEVICE_ERROR;\r
201 goto Exit;\r
202 }\r
203 Status = PtpCrbWaitRegisterBits (\r
204 &CrbReg->CrbControlStatus,\r
205 0,\r
206 PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,\r
207 PTP_TIMEOUT_C\r
208 );\r
209 if (EFI_ERROR (Status)) {\r
210 Status = EFI_DEVICE_ERROR;\r
211 goto Exit;\r
212 }\r
213\r
214 //\r
215 // STEP 1:\r
216 // Command Reception occurs following a Ready state between the write of the\r
217 // first byte of a command to the Command Buffer and the receipt of a write\r
218 // of 1 to Start.\r
219 //\r
220 for (Index = 0; Index < SizeIn; Index++) {\r
221 MmioWrite8 ((UINTN)&CrbReg->CrbDataBuffer[Index], BufferIn[Index]);\r
222 }\r
223 MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));\r
224 MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);\r
225 MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof(CrbReg->CrbDataBuffer));\r
226\r
227 MmioWrite64 ((UINTN)&CrbReg->CrbControlResponseAddrss, (UINT32)(UINTN)CrbReg->CrbDataBuffer);\r
228 MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof(CrbReg->CrbDataBuffer));\r
229\r
230 //\r
231 // STEP 2:\r
232 // Command Execution occurs after receipt of a 1 to Start and the TPM\r
233 // clearing Start to 0.\r
234 //\r
235 MmioWrite32((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);\r
236 Status = PtpCrbWaitRegisterBits (\r
237 &CrbReg->CrbControlStart,\r
238 0,\r
239 PTP_CRB_CONTROL_START,\r
240 PTP_TIMEOUT_MAX\r
241 );\r
242 if (EFI_ERROR (Status)) {\r
243 Status = EFI_DEVICE_ERROR;\r
244 goto Exit;\r
245 }\r
246\r
247 //\r
248 // STEP 3:\r
249 // Command Completion occurs after completion of a command (indicated by the\r
250 // TPM clearing TPM_CRB_CTRL_Start_x to 0) and before a write of a 1 by the\r
251 // software to Request.goIdle.\r
252 //\r
253\r
254 //\r
255 // Get response data header\r
256 //\r
257 for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {\r
258 BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);\r
259 }\r
260 DEBUG_CODE (\r
261 DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand ReceiveHeader - "));\r
262 for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {\r
263 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r
264 }\r
265 DEBUG ((EFI_D_VERBOSE, "\n"));\r
266 );\r
267 //\r
268 // Check the reponse data header (tag, parasize and returncode)\r
269 //\r
270 CopyMem (&Data16, BufferOut, sizeof (UINT16));\r
271 // TPM2 should not use this RSP_COMMAND\r
272 if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {\r
273 DEBUG ((EFI_D_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));\r
274 Status = EFI_UNSUPPORTED;\r
275 goto Exit;\r
276 }\r
277\r
278 CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r
279 TpmOutSize = SwapBytes32 (Data32);\r
280 if (*SizeOut < TpmOutSize) {\r
281 Status = EFI_BUFFER_TOO_SMALL;\r
282 goto Exit;\r
283 }\r
284 *SizeOut = TpmOutSize;\r
285 //\r
286 // Continue reading the remaining data\r
287 //\r
288 for (Index = sizeof (TPM2_RESPONSE_HEADER); Index < TpmOutSize; Index++) {\r
289 BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);\r
290 }\r
291Exit:\r
292 DEBUG_CODE (\r
293 DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand Receive - "));\r
294 for (Index = 0; Index < TpmOutSize; Index++) {\r
295 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r
296 }\r
297 DEBUG ((EFI_D_VERBOSE, "\n"));\r
298 );\r
299\r
300 //\r
301 // STEP 4:\r
302 // Idle is any time TPM_CRB_CTRL_STS_x.Status.goIdle is 1.\r
303 //\r
304 MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);\r
305 return Status;\r
306}\r
307\r
308/**\r
309 Send a command to TPM for execution and return response data.\r
310\r
311 @param[in] TisReg TPM register space base address.\r
312 @param[in] BufferIn Buffer for command data.\r
313 @param[in] SizeIn Size of command data.\r
314 @param[in, out] BufferOut Buffer for response data.\r
315 @param[in, out] SizeOut Size of response data.\r
316\r
317 @retval EFI_SUCCESS Operation completed successfully.\r
318 @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r
319 @retval EFI_DEVICE_ERROR Unexpected device behavior.\r
320 @retval EFI_UNSUPPORTED Unsupported TPM version\r
321\r
322**/\r
323EFI_STATUS\r
324Tpm2TisTpmCommand (\r
325 IN TIS_PC_REGISTERS_PTR TisReg,\r
326 IN UINT8 *BufferIn,\r
327 IN UINT32 SizeIn,\r
328 IN OUT UINT8 *BufferOut,\r
329 IN OUT UINT32 *SizeOut\r
330 );\r
331\r
332/**\r
333 Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE\r
334 to ACCESS Register in the time of default TIS_TIMEOUT_A.\r
335\r
336 @param[in] TisReg Pointer to TIS register.\r
337\r
338 @retval EFI_SUCCESS Get the control of TPM chip.\r
339 @retval EFI_INVALID_PARAMETER TisReg is NULL.\r
340 @retval EFI_NOT_FOUND TPM chip doesn't exit.\r
341 @retval EFI_TIMEOUT Can't get the TPM control in time.\r
342**/\r
343EFI_STATUS\r
344TisPcRequestUseTpm (\r
345 IN TIS_PC_REGISTERS_PTR TisReg\r
346 );\r
347\r
348/**\r
349 Return PTP interface type.\r
350\r
351 @param[in] Register Pointer to PTP register.\r
352\r
353 @return PTP interface type.\r
354**/\r
355PTP_INTERFACE_TYPE\r
356GetPtpInterface (\r
357 IN VOID *Register\r
358 )\r
359{\r
360 PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;\r
361 PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;\r
362\r
363 if (!IsPtpPresence (Register)) {\r
364 return PtpInterfaceMax;\r
365 }\r
366 //\r
367 // Check interface id\r
368 //\r
369 InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r
370 InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);\r
371\r
372 if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&\r
373 (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&\r
374 (InterfaceId.Bits.CapCRB != 0)) {\r
375 return PtpInterfaceCrb;\r
376 }\r
377 if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&\r
378 (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&\r
379 (InterfaceId.Bits.CapFIFO != 0) &&\r
380 (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {\r
381 return PtpInterfaceFifo;\r
382 }\r
383 return PtpInterfaceTis;\r
384}\r
385\r
386/**\r
387 Dump PTP register information.\r
388\r
389 @param[in] Register Pointer to PTP register.\r
390**/\r
391VOID\r
392DumpPtpInfo (\r
393 IN VOID *Register\r
394 )\r
395{\r
396 PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;\r
397 PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;\r
398 UINT8 StatusEx;\r
399 UINT16 Vid;\r
400 UINT16 Did;\r
401 UINT8 Rid;\r
402 PTP_INTERFACE_TYPE PtpInterface;\r
403\r
404 if (!IsPtpPresence (Register)) {\r
405 return ;\r
406 }\r
407\r
408 InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r
409 InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);\r
410 StatusEx = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);\r
411\r
412 //\r
413 // Dump InterfaceId Register for PTP\r
414 //\r
415 DEBUG ((EFI_D_INFO, "InterfaceId - 0x%08x\n", InterfaceId.Uint32));\r
416 DEBUG ((EFI_D_INFO, " InterfaceType - 0x%02x\n", InterfaceId.Bits.InterfaceType));\r
417 if (InterfaceId.Bits.InterfaceType != PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) {\r
418 DEBUG ((EFI_D_INFO, " InterfaceVersion - 0x%02x\n", InterfaceId.Bits.InterfaceVersion));\r
419 DEBUG ((EFI_D_INFO, " CapFIFO - 0x%x\n", InterfaceId.Bits.CapFIFO));\r
420 DEBUG ((EFI_D_INFO, " CapCRB - 0x%x\n", InterfaceId.Bits.CapCRB));\r
421 }\r
422\r
423 //\r
424 // Dump Capability Register for TIS and FIFO\r
425 //\r
426 DEBUG ((EFI_D_INFO, "InterfaceCapability - 0x%08x\n", InterfaceCapability.Uint32));\r
427 if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) ||\r
428 (InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO)) {\r
429 DEBUG ((EFI_D_INFO, " InterfaceVersion - 0x%x\n", InterfaceCapability.Bits.InterfaceVersion));\r
430 }\r
431\r
432 //\r
433 // Dump StatusEx Register for PTP FIFO\r
434 //\r
435 DEBUG ((EFI_D_INFO, "StatusEx - 0x%02x\n", StatusEx));\r
436 if (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP) {\r
437 DEBUG ((EFI_D_INFO, " TpmFamily - 0x%x\n", (StatusEx & PTP_FIFO_STS_EX_TPM_FAMILY) >> PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET));\r
438 }\r
439\r
440 Vid = 0xFFFF;\r
441 Did = 0xFFFF;\r
442 Rid = 0xFF;\r
443 PtpInterface = GetPtpInterface (Register);\r
444 DEBUG ((EFI_D_INFO, "PtpInterface - %x\n", PtpInterface));\r
445 switch (PtpInterface) {\r
446 case PtpInterfaceCrb:\r
447 Vid = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);\r
448 Did = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);\r
449 Rid = (UINT8)InterfaceId.Bits.Rid;\r
450 break;\r
451 case PtpInterfaceFifo:\r
452 case PtpInterfaceTis:\r
453 Vid = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);\r
454 Did = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);\r
455 Rid = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);\r
456 break;\r
457 default:\r
458 break;\r
459 }\r
460 DEBUG ((EFI_D_INFO, "VID - 0x%04x\n", Vid));\r
461 DEBUG ((EFI_D_INFO, "DID - 0x%04x\n", Did));\r
462 DEBUG ((EFI_D_INFO, "RID - 0x%02x\n", Rid));\r
463}\r
464\r
465/**\r
466 This service enables the sending of commands to the TPM2.\r
467\r
468 @param[in] InputParameterBlockSize Size of the TPM2 input parameter block.\r
469 @param[in] InputParameterBlock Pointer to the TPM2 input parameter block.\r
470 @param[in,out] OutputParameterBlockSize Size of the TPM2 output parameter block.\r
471 @param[in] OutputParameterBlock Pointer to the TPM2 output parameter block.\r
472\r
473 @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.\r
474 @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.\r
475 @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.\r
476**/\r
477EFI_STATUS\r
478EFIAPI\r
479DTpm2SubmitCommand (\r
480 IN UINT32 InputParameterBlockSize,\r
481 IN UINT8 *InputParameterBlock,\r
482 IN OUT UINT32 *OutputParameterBlockSize,\r
483 IN UINT8 *OutputParameterBlock\r
484 )\r
485{\r
486 PTP_INTERFACE_TYPE PtpInterface;\r
487\r
488 PtpInterface = GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
489 switch (PtpInterface) {\r
490 case PtpInterfaceCrb:\r
491 return PtpCrbTpmCommand (\r
492 (PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r
493 InputParameterBlock,\r
494 InputParameterBlockSize,\r
495 OutputParameterBlock,\r
496 OutputParameterBlockSize\r
497 );\r
498 case PtpInterfaceFifo:\r
499 case PtpInterfaceTis:\r
500 return Tpm2TisTpmCommand (\r
501 (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r
502 InputParameterBlock,\r
503 InputParameterBlockSize,\r
504 OutputParameterBlock,\r
505 OutputParameterBlockSize\r
506 );\r
507 default:\r
508 return EFI_NOT_FOUND;\r
509 }\r
510}\r
511\r
512/**\r
513 This service requests use TPM2.\r
514\r
515 @retval EFI_SUCCESS Get the control of TPM2 chip.\r
516 @retval EFI_NOT_FOUND TPM2 not found.\r
517 @retval EFI_DEVICE_ERROR Unexpected device behavior.\r
518**/\r
519EFI_STATUS\r
520EFIAPI\r
521DTpm2RequestUseTpm (\r
522 VOID\r
523 )\r
524{\r
525 PTP_INTERFACE_TYPE PtpInterface;\r
526\r
527 PtpInterface = GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
528 switch (PtpInterface) {\r
529 case PtpInterfaceCrb:\r
530 return PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
531 case PtpInterfaceFifo:\r
532 case PtpInterfaceTis:\r
533 return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
534 default:\r
535 return EFI_NOT_FOUND;\r
536 }\r
537}\r
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