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79e748cf JY |
1 | /** @file\r |
2 | PTP (Platform TPM Profile) CRB (Command Response Buffer) interface used by dTPM2.0 library.\r | |
3 | \r | |
11cf02f6 | 4 | Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r |
289b714b | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
79e748cf JY |
6 | \r |
7 | **/\r | |
8 | \r | |
9 | #include <IndustryStandard/Tpm20.h>\r | |
10 | \r | |
11 | #include <Library/BaseLib.h>\r | |
12 | #include <Library/BaseMemoryLib.h>\r | |
13 | #include <Library/IoLib.h>\r | |
14 | #include <Library/TimerLib.h>\r | |
15 | #include <Library/DebugLib.h>\r | |
16 | #include <Library/Tpm2DeviceLib.h>\r | |
17 | #include <Library/PcdLib.h>\r | |
18 | \r | |
19 | #include <IndustryStandard/TpmPtp.h>\r | |
20 | #include <IndustryStandard/TpmTis.h>\r | |
21 | \r | |
79e748cf JY |
22 | //\r |
23 | // Execution of the command may take from several seconds to minutes for certain\r | |
24 | // commands, such as key generation.\r | |
25 | //\r | |
26 | #define PTP_TIMEOUT_MAX (90000 * 1000) // 90s\r | |
27 | \r | |
28 | //\r | |
29 | // Max TPM command/reponse length\r | |
30 | //\r | |
31 | #define TPMCMDBUFLENGTH 0x500\r | |
32 | \r | |
33 | /**\r | |
34 | Check whether TPM PTP register exist.\r | |
35 | \r | |
36 | @param[in] Reg Pointer to PTP register.\r | |
37 | \r | |
38 | @retval TRUE TPM PTP exists.\r | |
39 | @retval FALSE TPM PTP is not found.\r | |
40 | **/\r | |
41 | BOOLEAN\r | |
0e47ac15 | 42 | Tpm2IsPtpPresence (\r |
79e748cf JY |
43 | IN VOID *Reg\r |
44 | )\r | |
45 | {\r | |
46 | UINT8 RegRead;\r | |
47 | \r | |
48 | RegRead = MmioRead8 ((UINTN)Reg);\r | |
49 | if (RegRead == 0xFF) {\r | |
50 | //\r | |
51 | // No TPM chip\r | |
52 | //\r | |
53 | return FALSE;\r | |
54 | }\r | |
55 | return TRUE;\r | |
56 | }\r | |
57 | \r | |
58 | /**\r | |
59 | Check whether the value of a TPM chip register satisfies the input BIT setting.\r | |
60 | \r | |
61 | @param[in] Register Address port of register to be checked.\r | |
62 | @param[in] BitSet Check these data bits are set.\r | |
63 | @param[in] BitClear Check these data bits are clear.\r | |
64 | @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r | |
65 | \r | |
66 | @retval EFI_SUCCESS The register satisfies the check bit.\r | |
67 | @retval EFI_TIMEOUT The register can't run into the expected status in time.\r | |
68 | **/\r | |
69 | EFI_STATUS\r | |
70 | PtpCrbWaitRegisterBits (\r | |
71 | IN UINT32 *Register,\r | |
72 | IN UINT32 BitSet,\r | |
73 | IN UINT32 BitClear,\r | |
74 | IN UINT32 TimeOut\r | |
75 | )\r | |
76 | {\r | |
77 | UINT32 RegRead;\r | |
78 | UINT32 WaitTime;\r | |
79 | \r | |
80 | for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r | |
81 | RegRead = MmioRead32 ((UINTN)Register);\r | |
82 | if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {\r | |
83 | return EFI_SUCCESS;\r | |
84 | }\r | |
85 | MicroSecondDelay (30);\r | |
86 | }\r | |
87 | return EFI_TIMEOUT;\r | |
88 | }\r | |
89 | \r | |
90 | /**\r | |
91 | Get the control of TPM chip.\r | |
92 | \r | |
93 | @param[in] CrbReg Pointer to CRB register.\r | |
94 | \r | |
95 | @retval EFI_SUCCESS Get the control of TPM chip.\r | |
96 | @retval EFI_INVALID_PARAMETER CrbReg is NULL.\r | |
97 | @retval EFI_NOT_FOUND TPM chip doesn't exit.\r | |
98 | @retval EFI_TIMEOUT Can't get the TPM control in time.\r | |
99 | **/\r | |
100 | EFI_STATUS\r | |
101 | PtpCrbRequestUseTpm (\r | |
102 | IN PTP_CRB_REGISTERS_PTR CrbReg\r | |
103 | )\r | |
104 | {\r | |
105 | EFI_STATUS Status;\r | |
106 | \r | |
0e47ac15 | 107 | if (!Tpm2IsPtpPresence (CrbReg)) {\r |
79e748cf JY |
108 | return EFI_NOT_FOUND;\r |
109 | }\r | |
110 | \r | |
111 | MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);\r | |
112 | Status = PtpCrbWaitRegisterBits (\r | |
113 | &CrbReg->LocalityStatus,\r | |
114 | PTP_CRB_LOCALITY_STATUS_GRANTED,\r | |
115 | 0,\r | |
116 | PTP_TIMEOUT_A\r | |
117 | );\r | |
118 | return Status;\r | |
119 | }\r | |
120 | \r | |
121 | /**\r | |
122 | Send a command to TPM for execution and return response data.\r | |
123 | \r | |
124 | @param[in] CrbReg TPM register space base address.\r | |
125 | @param[in] BufferIn Buffer for command data.\r | |
126 | @param[in] SizeIn Size of command data.\r | |
127 | @param[in, out] BufferOut Buffer for response data.\r | |
128 | @param[in, out] SizeOut Size of response data.\r | |
129 | \r | |
130 | @retval EFI_SUCCESS Operation completed successfully.\r | |
131 | @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r | |
132 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
133 | @retval EFI_UNSUPPORTED Unsupported TPM version\r | |
134 | \r | |
135 | **/\r | |
136 | EFI_STATUS\r | |
137 | PtpCrbTpmCommand (\r | |
138 | IN PTP_CRB_REGISTERS_PTR CrbReg,\r | |
139 | IN UINT8 *BufferIn,\r | |
140 | IN UINT32 SizeIn,\r | |
141 | IN OUT UINT8 *BufferOut,\r | |
142 | IN OUT UINT32 *SizeOut\r | |
143 | )\r | |
144 | {\r | |
145 | EFI_STATUS Status;\r | |
146 | UINT32 Index;\r | |
147 | UINT32 TpmOutSize;\r | |
148 | UINT16 Data16;\r | |
149 | UINT32 Data32;\r | |
150 | \r | |
151 | DEBUG_CODE (\r | |
152 | UINTN DebugSize;\r | |
153 | \r | |
154 | DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand Send - "));\r | |
155 | if (SizeIn > 0x100) {\r | |
156 | DebugSize = 0x40;\r | |
157 | } else {\r | |
158 | DebugSize = SizeIn;\r | |
159 | }\r | |
160 | for (Index = 0; Index < DebugSize; Index++) {\r | |
161 | DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r | |
162 | }\r | |
163 | if (DebugSize != SizeIn) {\r | |
164 | DEBUG ((EFI_D_VERBOSE, "...... "));\r | |
165 | for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r | |
166 | DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r | |
167 | }\r | |
168 | }\r | |
169 | DEBUG ((EFI_D_VERBOSE, "\n"));\r | |
170 | );\r | |
63197670 | 171 | TpmOutSize = 0;\r |
79e748cf JY |
172 | \r |
173 | //\r | |
174 | // STEP 0:\r | |
63197670 ZC |
175 | // if CapCRbIdelByPass == 0, enforce Idle state before sending command\r |
176 | //\r | |
177 | if (PcdGet8(PcdCRBIdleByPass) == 0 && (MmioRead32((UINTN)&CrbReg->CrbControlStatus) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0){\r | |
178 | Status = PtpCrbWaitRegisterBits (\r | |
179 | &CrbReg->CrbControlStatus,\r | |
180 | PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,\r | |
181 | 0,\r | |
182 | PTP_TIMEOUT_C\r | |
183 | );\r | |
184 | if (EFI_ERROR (Status)) {\r | |
185 | //\r | |
186 | // Try to goIdle to recover TPM\r | |
187 | //\r | |
188 | Status = EFI_DEVICE_ERROR;\r | |
189 | goto GoIdle_Exit;\r | |
190 | }\r | |
191 | }\r | |
192 | \r | |
193 | //\r | |
194 | // STEP 1:\r | |
79e748cf JY |
195 | // Ready is any time the TPM is ready to receive a command, following a write\r |
196 | // of 1 by software to Request.cmdReady, as indicated by the Status field\r | |
197 | // being cleared to 0.\r | |
198 | //\r | |
199 | MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);\r | |
200 | Status = PtpCrbWaitRegisterBits (\r | |
201 | &CrbReg->CrbControlRequest,\r | |
202 | 0,\r | |
203 | PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY,\r | |
204 | PTP_TIMEOUT_C\r | |
205 | );\r | |
206 | if (EFI_ERROR (Status)) {\r | |
207 | Status = EFI_DEVICE_ERROR;\r | |
63197670 | 208 | goto GoIdle_Exit;\r |
79e748cf JY |
209 | }\r |
210 | Status = PtpCrbWaitRegisterBits (\r | |
211 | &CrbReg->CrbControlStatus,\r | |
212 | 0,\r | |
213 | PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,\r | |
214 | PTP_TIMEOUT_C\r | |
215 | );\r | |
216 | if (EFI_ERROR (Status)) {\r | |
217 | Status = EFI_DEVICE_ERROR;\r | |
63197670 | 218 | goto GoIdle_Exit;\r |
79e748cf JY |
219 | }\r |
220 | \r | |
221 | //\r | |
63197670 | 222 | // STEP 2:\r |
79e748cf JY |
223 | // Command Reception occurs following a Ready state between the write of the\r |
224 | // first byte of a command to the Command Buffer and the receipt of a write\r | |
225 | // of 1 to Start.\r | |
226 | //\r | |
227 | for (Index = 0; Index < SizeIn; Index++) {\r | |
228 | MmioWrite8 ((UINTN)&CrbReg->CrbDataBuffer[Index], BufferIn[Index]);\r | |
229 | }\r | |
230 | MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));\r | |
231 | MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);\r | |
232 | MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof(CrbReg->CrbDataBuffer));\r | |
233 | \r | |
234 | MmioWrite64 ((UINTN)&CrbReg->CrbControlResponseAddrss, (UINT32)(UINTN)CrbReg->CrbDataBuffer);\r | |
235 | MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof(CrbReg->CrbDataBuffer));\r | |
236 | \r | |
237 | //\r | |
63197670 | 238 | // STEP 3:\r |
79e748cf JY |
239 | // Command Execution occurs after receipt of a 1 to Start and the TPM\r |
240 | // clearing Start to 0.\r | |
241 | //\r | |
242 | MmioWrite32((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);\r | |
243 | Status = PtpCrbWaitRegisterBits (\r | |
244 | &CrbReg->CrbControlStart,\r | |
245 | 0,\r | |
246 | PTP_CRB_CONTROL_START,\r | |
247 | PTP_TIMEOUT_MAX\r | |
248 | );\r | |
249 | if (EFI_ERROR (Status)) {\r | |
11cf02f6 ZC |
250 | //\r |
251 | // Command Completion check timeout. Cancel the currently executing command by writing TPM_CRB_CTRL_CANCEL,\r | |
252 | // Expect TPM_RC_CANCELLED or successfully completed response.\r | |
253 | //\r | |
254 | MmioWrite32((UINTN)&CrbReg->CrbControlCancel, PTP_CRB_CONTROL_CANCEL);\r | |
255 | Status = PtpCrbWaitRegisterBits (\r | |
256 | &CrbReg->CrbControlStart,\r | |
257 | 0,\r | |
258 | PTP_CRB_CONTROL_START,\r | |
259 | PTP_TIMEOUT_B\r | |
260 | );\r | |
261 | MmioWrite32((UINTN)&CrbReg->CrbControlCancel, 0);\r | |
262 | \r | |
263 | if (EFI_ERROR(Status)) {\r | |
264 | //\r | |
265 | // Still in Command Execution state. Try to goIdle, the behavior is agnostic.\r | |
266 | //\r | |
267 | Status = EFI_DEVICE_ERROR;\r | |
63197670 | 268 | goto GoIdle_Exit;\r |
11cf02f6 | 269 | }\r |
79e748cf JY |
270 | }\r |
271 | \r | |
272 | //\r | |
63197670 | 273 | // STEP 4:\r |
79e748cf JY |
274 | // Command Completion occurs after completion of a command (indicated by the\r |
275 | // TPM clearing TPM_CRB_CTRL_Start_x to 0) and before a write of a 1 by the\r | |
276 | // software to Request.goIdle.\r | |
277 | //\r | |
278 | \r | |
279 | //\r | |
280 | // Get response data header\r | |
281 | //\r | |
282 | for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {\r | |
283 | BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);\r | |
284 | }\r | |
285 | DEBUG_CODE (\r | |
286 | DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand ReceiveHeader - "));\r | |
287 | for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {\r | |
288 | DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r | |
289 | }\r | |
290 | DEBUG ((EFI_D_VERBOSE, "\n"));\r | |
291 | );\r | |
292 | //\r | |
293 | // Check the reponse data header (tag, parasize and returncode)\r | |
294 | //\r | |
295 | CopyMem (&Data16, BufferOut, sizeof (UINT16));\r | |
296 | // TPM2 should not use this RSP_COMMAND\r | |
297 | if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {\r | |
298 | DEBUG ((EFI_D_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));\r | |
299 | Status = EFI_UNSUPPORTED;\r | |
63197670 | 300 | goto GoIdle_Exit;\r |
79e748cf JY |
301 | }\r |
302 | \r | |
303 | CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r | |
304 | TpmOutSize = SwapBytes32 (Data32);\r | |
305 | if (*SizeOut < TpmOutSize) {\r | |
63197670 ZC |
306 | //\r |
307 | // Command completed, but buffer is not enough\r | |
308 | //\r | |
79e748cf | 309 | Status = EFI_BUFFER_TOO_SMALL;\r |
63197670 | 310 | goto GoReady_Exit;\r |
79e748cf JY |
311 | }\r |
312 | *SizeOut = TpmOutSize;\r | |
313 | //\r | |
314 | // Continue reading the remaining data\r | |
315 | //\r | |
316 | for (Index = sizeof (TPM2_RESPONSE_HEADER); Index < TpmOutSize; Index++) {\r | |
317 | BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);\r | |
318 | }\r | |
63197670 | 319 | \r |
79e748cf JY |
320 | DEBUG_CODE (\r |
321 | DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand Receive - "));\r | |
322 | for (Index = 0; Index < TpmOutSize; Index++) {\r | |
323 | DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r | |
324 | }\r | |
325 | DEBUG ((EFI_D_VERBOSE, "\n"));\r | |
326 | );\r | |
327 | \r | |
63197670 | 328 | GoReady_Exit:\r |
79e748cf | 329 | //\r |
63197670 ZC |
330 | // Goto Ready State if command is completed succesfully and TPM support IdleBypass\r |
331 | // If not supported. flow down to GoIdle\r | |
332 | //\r | |
333 | if (PcdGet8(PcdCRBIdleByPass) == 1) {\r | |
334 | MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);\r | |
335 | return Status;\r | |
336 | }\r | |
337 | \r | |
338 | //\r | |
339 | // Do not wait for state transition for TIMEOUT_C\r | |
340 | // This function will try to wait 2 TIMEOUT_C at the beginning in next call.\r | |
341 | //\r | |
342 | GoIdle_Exit:\r | |
343 | \r | |
344 | //\r | |
345 | // Return to Idle state by setting TPM_CRB_CTRL_STS_x.Status.goIdle to 1.\r | |
79e748cf JY |
346 | //\r |
347 | MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);\r | |
63197670 ZC |
348 | \r |
349 | //\r | |
350 | // Only enforce Idle state transition if execution fails when CRBIndleBypass==1\r | |
351 | // Leave regular Idle delay at the beginning of next command execution\r | |
352 | //\r | |
353 | if (PcdGet8(PcdCRBIdleByPass) == 1){\r | |
354 | Status = PtpCrbWaitRegisterBits (\r | |
355 | &CrbReg->CrbControlStatus,\r | |
356 | PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,\r | |
357 | 0,\r | |
358 | PTP_TIMEOUT_C\r | |
359 | );\r | |
360 | }\r | |
361 | \r | |
79e748cf JY |
362 | return Status;\r |
363 | }\r | |
364 | \r | |
365 | /**\r | |
366 | Send a command to TPM for execution and return response data.\r | |
367 | \r | |
368 | @param[in] TisReg TPM register space base address.\r | |
369 | @param[in] BufferIn Buffer for command data.\r | |
370 | @param[in] SizeIn Size of command data.\r | |
371 | @param[in, out] BufferOut Buffer for response data.\r | |
372 | @param[in, out] SizeOut Size of response data.\r | |
373 | \r | |
374 | @retval EFI_SUCCESS Operation completed successfully.\r | |
375 | @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r | |
376 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
377 | @retval EFI_UNSUPPORTED Unsupported TPM version\r | |
378 | \r | |
379 | **/\r | |
380 | EFI_STATUS\r | |
381 | Tpm2TisTpmCommand (\r | |
382 | IN TIS_PC_REGISTERS_PTR TisReg,\r | |
383 | IN UINT8 *BufferIn,\r | |
384 | IN UINT32 SizeIn,\r | |
385 | IN OUT UINT8 *BufferOut,\r | |
386 | IN OUT UINT32 *SizeOut\r | |
387 | );\r | |
388 | \r | |
389 | /**\r | |
390 | Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE\r | |
391 | to ACCESS Register in the time of default TIS_TIMEOUT_A.\r | |
392 | \r | |
393 | @param[in] TisReg Pointer to TIS register.\r | |
394 | \r | |
395 | @retval EFI_SUCCESS Get the control of TPM chip.\r | |
396 | @retval EFI_INVALID_PARAMETER TisReg is NULL.\r | |
397 | @retval EFI_NOT_FOUND TPM chip doesn't exit.\r | |
398 | @retval EFI_TIMEOUT Can't get the TPM control in time.\r | |
399 | **/\r | |
400 | EFI_STATUS\r | |
401 | TisPcRequestUseTpm (\r | |
402 | IN TIS_PC_REGISTERS_PTR TisReg\r | |
403 | );\r | |
404 | \r | |
405 | /**\r | |
406 | Return PTP interface type.\r | |
407 | \r | |
408 | @param[in] Register Pointer to PTP register.\r | |
409 | \r | |
410 | @return PTP interface type.\r | |
411 | **/\r | |
f15cb995 | 412 | TPM2_PTP_INTERFACE_TYPE\r |
0e47ac15 | 413 | Tpm2GetPtpInterface (\r |
79e748cf JY |
414 | IN VOID *Register\r |
415 | )\r | |
416 | {\r | |
417 | PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;\r | |
418 | PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;\r | |
419 | \r | |
0e47ac15 | 420 | if (!Tpm2IsPtpPresence (Register)) {\r |
f15cb995 | 421 | return Tpm2PtpInterfaceMax;\r |
79e748cf JY |
422 | }\r |
423 | //\r | |
424 | // Check interface id\r | |
425 | //\r | |
426 | InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r | |
427 | InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);\r | |
428 | \r | |
429 | if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&\r | |
430 | (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&\r | |
431 | (InterfaceId.Bits.CapCRB != 0)) {\r | |
f15cb995 | 432 | return Tpm2PtpInterfaceCrb;\r |
79e748cf JY |
433 | }\r |
434 | if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&\r | |
435 | (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&\r | |
436 | (InterfaceId.Bits.CapFIFO != 0) &&\r | |
437 | (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {\r | |
f15cb995 | 438 | return Tpm2PtpInterfaceFifo;\r |
79e748cf | 439 | }\r |
f15cb995 | 440 | return Tpm2PtpInterfaceTis;\r |
79e748cf JY |
441 | }\r |
442 | \r | |
63197670 ZC |
443 | /**\r |
444 | Return PTP CRB interface IdleByPass state.\r | |
445 | \r | |
446 | @param[in] Register Pointer to PTP register.\r | |
447 | \r | |
448 | @return PTP CRB interface IdleByPass state.\r | |
449 | **/\r | |
450 | UINT8\r | |
451 | Tpm2GetIdleByPass (\r | |
452 | IN VOID *Register\r | |
453 | )\r | |
454 | {\r | |
455 | PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;\r | |
456 | \r | |
457 | //\r | |
458 | // Check interface id\r | |
459 | //\r | |
460 | InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r | |
461 | \r | |
462 | return (UINT8)(InterfaceId.Bits.CapCRBIdleBypass);\r | |
463 | }\r | |
464 | \r | |
79e748cf JY |
465 | /**\r |
466 | Dump PTP register information.\r | |
467 | \r | |
468 | @param[in] Register Pointer to PTP register.\r | |
469 | **/\r | |
470 | VOID\r | |
471 | DumpPtpInfo (\r | |
472 | IN VOID *Register\r | |
473 | )\r | |
474 | {\r | |
475 | PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;\r | |
476 | PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;\r | |
477 | UINT8 StatusEx;\r | |
478 | UINT16 Vid;\r | |
479 | UINT16 Did;\r | |
480 | UINT8 Rid;\r | |
f15cb995 | 481 | TPM2_PTP_INTERFACE_TYPE PtpInterface;\r |
79e748cf | 482 | \r |
0e47ac15 | 483 | if (!Tpm2IsPtpPresence (Register)) {\r |
79e748cf JY |
484 | return ;\r |
485 | }\r | |
486 | \r | |
487 | InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r | |
488 | InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);\r | |
489 | StatusEx = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);\r | |
490 | \r | |
491 | //\r | |
492 | // Dump InterfaceId Register for PTP\r | |
493 | //\r | |
494 | DEBUG ((EFI_D_INFO, "InterfaceId - 0x%08x\n", InterfaceId.Uint32));\r | |
495 | DEBUG ((EFI_D_INFO, " InterfaceType - 0x%02x\n", InterfaceId.Bits.InterfaceType));\r | |
496 | if (InterfaceId.Bits.InterfaceType != PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) {\r | |
497 | DEBUG ((EFI_D_INFO, " InterfaceVersion - 0x%02x\n", InterfaceId.Bits.InterfaceVersion));\r | |
498 | DEBUG ((EFI_D_INFO, " CapFIFO - 0x%x\n", InterfaceId.Bits.CapFIFO));\r | |
499 | DEBUG ((EFI_D_INFO, " CapCRB - 0x%x\n", InterfaceId.Bits.CapCRB));\r | |
500 | }\r | |
501 | \r | |
502 | //\r | |
503 | // Dump Capability Register for TIS and FIFO\r | |
504 | //\r | |
505 | DEBUG ((EFI_D_INFO, "InterfaceCapability - 0x%08x\n", InterfaceCapability.Uint32));\r | |
506 | if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) ||\r | |
507 | (InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO)) {\r | |
508 | DEBUG ((EFI_D_INFO, " InterfaceVersion - 0x%x\n", InterfaceCapability.Bits.InterfaceVersion));\r | |
509 | }\r | |
510 | \r | |
511 | //\r | |
512 | // Dump StatusEx Register for PTP FIFO\r | |
513 | //\r | |
514 | DEBUG ((EFI_D_INFO, "StatusEx - 0x%02x\n", StatusEx));\r | |
515 | if (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP) {\r | |
516 | DEBUG ((EFI_D_INFO, " TpmFamily - 0x%x\n", (StatusEx & PTP_FIFO_STS_EX_TPM_FAMILY) >> PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET));\r | |
517 | }\r | |
518 | \r | |
519 | Vid = 0xFFFF;\r | |
520 | Did = 0xFFFF;\r | |
521 | Rid = 0xFF;\r | |
f15cb995 | 522 | PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);\r |
79e748cf JY |
523 | DEBUG ((EFI_D_INFO, "PtpInterface - %x\n", PtpInterface));\r |
524 | switch (PtpInterface) {\r | |
f15cb995 | 525 | case Tpm2PtpInterfaceCrb:\r |
79e748cf JY |
526 | Vid = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);\r |
527 | Did = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);\r | |
528 | Rid = (UINT8)InterfaceId.Bits.Rid;\r | |
529 | break;\r | |
f15cb995 ZC |
530 | case Tpm2PtpInterfaceFifo:\r |
531 | case Tpm2PtpInterfaceTis:\r | |
79e748cf JY |
532 | Vid = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);\r |
533 | Did = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);\r | |
534 | Rid = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);\r | |
535 | break;\r | |
536 | default:\r | |
537 | break;\r | |
538 | }\r | |
539 | DEBUG ((EFI_D_INFO, "VID - 0x%04x\n", Vid));\r | |
540 | DEBUG ((EFI_D_INFO, "DID - 0x%04x\n", Did));\r | |
541 | DEBUG ((EFI_D_INFO, "RID - 0x%02x\n", Rid));\r | |
542 | }\r | |
543 | \r | |
544 | /**\r | |
545 | This service enables the sending of commands to the TPM2.\r | |
546 | \r | |
547 | @param[in] InputParameterBlockSize Size of the TPM2 input parameter block.\r | |
548 | @param[in] InputParameterBlock Pointer to the TPM2 input parameter block.\r | |
549 | @param[in,out] OutputParameterBlockSize Size of the TPM2 output parameter block.\r | |
550 | @param[in] OutputParameterBlock Pointer to the TPM2 output parameter block.\r | |
551 | \r | |
552 | @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.\r | |
553 | @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.\r | |
554 | @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.\r | |
555 | **/\r | |
556 | EFI_STATUS\r | |
557 | EFIAPI\r | |
558 | DTpm2SubmitCommand (\r | |
559 | IN UINT32 InputParameterBlockSize,\r | |
560 | IN UINT8 *InputParameterBlock,\r | |
561 | IN OUT UINT32 *OutputParameterBlockSize,\r | |
562 | IN UINT8 *OutputParameterBlock\r | |
563 | )\r | |
564 | {\r | |
f15cb995 | 565 | TPM2_PTP_INTERFACE_TYPE PtpInterface;\r |
79e748cf | 566 | \r |
f15cb995 | 567 | PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);\r |
79e748cf | 568 | switch (PtpInterface) {\r |
f15cb995 | 569 | case Tpm2PtpInterfaceCrb:\r |
79e748cf JY |
570 | return PtpCrbTpmCommand (\r |
571 | (PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r | |
572 | InputParameterBlock,\r | |
573 | InputParameterBlockSize,\r | |
574 | OutputParameterBlock,\r | |
575 | OutputParameterBlockSize\r | |
576 | );\r | |
f15cb995 ZC |
577 | case Tpm2PtpInterfaceFifo:\r |
578 | case Tpm2PtpInterfaceTis:\r | |
79e748cf JY |
579 | return Tpm2TisTpmCommand (\r |
580 | (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r | |
581 | InputParameterBlock,\r | |
582 | InputParameterBlockSize,\r | |
583 | OutputParameterBlock,\r | |
584 | OutputParameterBlockSize\r | |
585 | );\r | |
586 | default:\r | |
587 | return EFI_NOT_FOUND;\r | |
588 | }\r | |
589 | }\r | |
590 | \r | |
591 | /**\r | |
592 | This service requests use TPM2.\r | |
593 | \r | |
594 | @retval EFI_SUCCESS Get the control of TPM2 chip.\r | |
595 | @retval EFI_NOT_FOUND TPM2 not found.\r | |
596 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
597 | **/\r | |
598 | EFI_STATUS\r | |
599 | EFIAPI\r | |
600 | DTpm2RequestUseTpm (\r | |
601 | VOID\r | |
602 | )\r | |
603 | {\r | |
f15cb995 | 604 | TPM2_PTP_INTERFACE_TYPE PtpInterface;\r |
79e748cf | 605 | \r |
f15cb995 | 606 | PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);\r |
79e748cf | 607 | switch (PtpInterface) {\r |
f15cb995 | 608 | case Tpm2PtpInterfaceCrb:\r |
79e748cf | 609 | return PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r |
f15cb995 ZC |
610 | case Tpm2PtpInterfaceFifo:\r |
611 | case Tpm2PtpInterfaceTis:\r | |
79e748cf JY |
612 | return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r |
613 | default:\r | |
614 | return EFI_NOT_FOUND;\r | |
615 | }\r | |
616 | }\r |