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79e748cf JY |
1 | /** @file\r |
2 | PTP (Platform TPM Profile) CRB (Command Response Buffer) interface used by dTPM2.0 library.\r | |
3 | \r | |
11cf02f6 | 4 | Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r |
7a56650e | 5 | Copyright (c), Microsoft Corporation.\r |
289b714b | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
79e748cf JY |
7 | \r |
8 | **/\r | |
9 | \r | |
10 | #include <IndustryStandard/Tpm20.h>\r | |
11 | \r | |
12 | #include <Library/BaseLib.h>\r | |
13 | #include <Library/BaseMemoryLib.h>\r | |
14 | #include <Library/IoLib.h>\r | |
15 | #include <Library/TimerLib.h>\r | |
16 | #include <Library/DebugLib.h>\r | |
17 | #include <Library/Tpm2DeviceLib.h>\r | |
18 | #include <Library/PcdLib.h>\r | |
19 | \r | |
20 | #include <IndustryStandard/TpmPtp.h>\r | |
21 | #include <IndustryStandard/TpmTis.h>\r | |
22 | \r | |
7a56650e KQ |
23 | #include "Tpm2DeviceLibDTpm.h"\r |
24 | \r | |
79e748cf JY |
25 | //\r |
26 | // Execution of the command may take from several seconds to minutes for certain\r | |
27 | // commands, such as key generation.\r | |
28 | //\r | |
29 | #define PTP_TIMEOUT_MAX (90000 * 1000) // 90s\r | |
30 | \r | |
31 | //\r | |
f9fd0c21 | 32 | // Max TPM command/response length\r |
79e748cf JY |
33 | //\r |
34 | #define TPMCMDBUFLENGTH 0x500\r | |
35 | \r | |
36 | /**\r | |
37 | Check whether TPM PTP register exist.\r | |
38 | \r | |
39 | @param[in] Reg Pointer to PTP register.\r | |
40 | \r | |
41 | @retval TRUE TPM PTP exists.\r | |
42 | @retval FALSE TPM PTP is not found.\r | |
43 | **/\r | |
44 | BOOLEAN\r | |
0e47ac15 | 45 | Tpm2IsPtpPresence (\r |
79e748cf JY |
46 | IN VOID *Reg\r |
47 | )\r | |
48 | {\r | |
49 | UINT8 RegRead;\r | |
50 | \r | |
51 | RegRead = MmioRead8 ((UINTN)Reg);\r | |
52 | if (RegRead == 0xFF) {\r | |
53 | //\r | |
54 | // No TPM chip\r | |
55 | //\r | |
56 | return FALSE;\r | |
57 | }\r | |
58 | return TRUE;\r | |
59 | }\r | |
60 | \r | |
61 | /**\r | |
62 | Check whether the value of a TPM chip register satisfies the input BIT setting.\r | |
63 | \r | |
64 | @param[in] Register Address port of register to be checked.\r | |
65 | @param[in] BitSet Check these data bits are set.\r | |
66 | @param[in] BitClear Check these data bits are clear.\r | |
67 | @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r | |
68 | \r | |
69 | @retval EFI_SUCCESS The register satisfies the check bit.\r | |
70 | @retval EFI_TIMEOUT The register can't run into the expected status in time.\r | |
71 | **/\r | |
72 | EFI_STATUS\r | |
73 | PtpCrbWaitRegisterBits (\r | |
74 | IN UINT32 *Register,\r | |
75 | IN UINT32 BitSet,\r | |
76 | IN UINT32 BitClear,\r | |
77 | IN UINT32 TimeOut\r | |
78 | )\r | |
79 | {\r | |
80 | UINT32 RegRead;\r | |
81 | UINT32 WaitTime;\r | |
82 | \r | |
83 | for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r | |
84 | RegRead = MmioRead32 ((UINTN)Register);\r | |
85 | if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {\r | |
86 | return EFI_SUCCESS;\r | |
87 | }\r | |
88 | MicroSecondDelay (30);\r | |
89 | }\r | |
90 | return EFI_TIMEOUT;\r | |
91 | }\r | |
92 | \r | |
93 | /**\r | |
94 | Get the control of TPM chip.\r | |
95 | \r | |
96 | @param[in] CrbReg Pointer to CRB register.\r | |
97 | \r | |
98 | @retval EFI_SUCCESS Get the control of TPM chip.\r | |
99 | @retval EFI_INVALID_PARAMETER CrbReg is NULL.\r | |
100 | @retval EFI_NOT_FOUND TPM chip doesn't exit.\r | |
101 | @retval EFI_TIMEOUT Can't get the TPM control in time.\r | |
102 | **/\r | |
103 | EFI_STATUS\r | |
104 | PtpCrbRequestUseTpm (\r | |
105 | IN PTP_CRB_REGISTERS_PTR CrbReg\r | |
106 | )\r | |
107 | {\r | |
108 | EFI_STATUS Status;\r | |
109 | \r | |
0e47ac15 | 110 | if (!Tpm2IsPtpPresence (CrbReg)) {\r |
79e748cf JY |
111 | return EFI_NOT_FOUND;\r |
112 | }\r | |
113 | \r | |
114 | MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);\r | |
115 | Status = PtpCrbWaitRegisterBits (\r | |
116 | &CrbReg->LocalityStatus,\r | |
117 | PTP_CRB_LOCALITY_STATUS_GRANTED,\r | |
118 | 0,\r | |
119 | PTP_TIMEOUT_A\r | |
120 | );\r | |
121 | return Status;\r | |
122 | }\r | |
123 | \r | |
124 | /**\r | |
125 | Send a command to TPM for execution and return response data.\r | |
126 | \r | |
127 | @param[in] CrbReg TPM register space base address.\r | |
128 | @param[in] BufferIn Buffer for command data.\r | |
129 | @param[in] SizeIn Size of command data.\r | |
130 | @param[in, out] BufferOut Buffer for response data.\r | |
131 | @param[in, out] SizeOut Size of response data.\r | |
132 | \r | |
133 | @retval EFI_SUCCESS Operation completed successfully.\r | |
134 | @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r | |
135 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
136 | @retval EFI_UNSUPPORTED Unsupported TPM version\r | |
137 | \r | |
138 | **/\r | |
139 | EFI_STATUS\r | |
140 | PtpCrbTpmCommand (\r | |
141 | IN PTP_CRB_REGISTERS_PTR CrbReg,\r | |
142 | IN UINT8 *BufferIn,\r | |
143 | IN UINT32 SizeIn,\r | |
144 | IN OUT UINT8 *BufferOut,\r | |
145 | IN OUT UINT32 *SizeOut\r | |
146 | )\r | |
147 | {\r | |
148 | EFI_STATUS Status;\r | |
149 | UINT32 Index;\r | |
150 | UINT32 TpmOutSize;\r | |
151 | UINT16 Data16;\r | |
152 | UINT32 Data32;\r | |
153 | \r | |
f9f4fb23 | 154 | DEBUG_CODE_BEGIN ();\r |
79e748cf JY |
155 | UINTN DebugSize;\r |
156 | \r | |
e905fbb0 | 157 | DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand Send - "));\r |
79e748cf JY |
158 | if (SizeIn > 0x100) {\r |
159 | DebugSize = 0x40;\r | |
160 | } else {\r | |
161 | DebugSize = SizeIn;\r | |
162 | }\r | |
163 | for (Index = 0; Index < DebugSize; Index++) {\r | |
e905fbb0 | 164 | DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));\r |
79e748cf JY |
165 | }\r |
166 | if (DebugSize != SizeIn) {\r | |
e905fbb0 | 167 | DEBUG ((DEBUG_VERBOSE, "...... "));\r |
79e748cf | 168 | for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r |
e905fbb0 | 169 | DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));\r |
79e748cf JY |
170 | }\r |
171 | }\r | |
e905fbb0 | 172 | DEBUG ((DEBUG_VERBOSE, "\n"));\r |
f9f4fb23 | 173 | DEBUG_CODE_END ();\r |
63197670 | 174 | TpmOutSize = 0;\r |
79e748cf JY |
175 | \r |
176 | //\r | |
177 | // STEP 0:\r | |
63197670 ZC |
178 | // if CapCRbIdelByPass == 0, enforce Idle state before sending command\r |
179 | //\r | |
7a56650e | 180 | if (GetCachedIdleByPass () == 0 && (MmioRead32((UINTN)&CrbReg->CrbControlStatus) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0){\r |
63197670 ZC |
181 | Status = PtpCrbWaitRegisterBits (\r |
182 | &CrbReg->CrbControlStatus,\r | |
183 | PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,\r | |
184 | 0,\r | |
185 | PTP_TIMEOUT_C\r | |
186 | );\r | |
187 | if (EFI_ERROR (Status)) {\r | |
188 | //\r | |
189 | // Try to goIdle to recover TPM\r | |
190 | //\r | |
191 | Status = EFI_DEVICE_ERROR;\r | |
192 | goto GoIdle_Exit;\r | |
193 | }\r | |
194 | }\r | |
195 | \r | |
196 | //\r | |
197 | // STEP 1:\r | |
79e748cf JY |
198 | // Ready is any time the TPM is ready to receive a command, following a write\r |
199 | // of 1 by software to Request.cmdReady, as indicated by the Status field\r | |
200 | // being cleared to 0.\r | |
201 | //\r | |
202 | MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);\r | |
203 | Status = PtpCrbWaitRegisterBits (\r | |
204 | &CrbReg->CrbControlRequest,\r | |
205 | 0,\r | |
206 | PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY,\r | |
207 | PTP_TIMEOUT_C\r | |
208 | );\r | |
209 | if (EFI_ERROR (Status)) {\r | |
210 | Status = EFI_DEVICE_ERROR;\r | |
63197670 | 211 | goto GoIdle_Exit;\r |
79e748cf JY |
212 | }\r |
213 | Status = PtpCrbWaitRegisterBits (\r | |
214 | &CrbReg->CrbControlStatus,\r | |
215 | 0,\r | |
216 | PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,\r | |
217 | PTP_TIMEOUT_C\r | |
218 | );\r | |
219 | if (EFI_ERROR (Status)) {\r | |
220 | Status = EFI_DEVICE_ERROR;\r | |
63197670 | 221 | goto GoIdle_Exit;\r |
79e748cf JY |
222 | }\r |
223 | \r | |
224 | //\r | |
63197670 | 225 | // STEP 2:\r |
79e748cf JY |
226 | // Command Reception occurs following a Ready state between the write of the\r |
227 | // first byte of a command to the Command Buffer and the receipt of a write\r | |
228 | // of 1 to Start.\r | |
229 | //\r | |
230 | for (Index = 0; Index < SizeIn; Index++) {\r | |
231 | MmioWrite8 ((UINTN)&CrbReg->CrbDataBuffer[Index], BufferIn[Index]);\r | |
232 | }\r | |
233 | MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));\r | |
234 | MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);\r | |
235 | MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof(CrbReg->CrbDataBuffer));\r | |
236 | \r | |
237 | MmioWrite64 ((UINTN)&CrbReg->CrbControlResponseAddrss, (UINT32)(UINTN)CrbReg->CrbDataBuffer);\r | |
238 | MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof(CrbReg->CrbDataBuffer));\r | |
239 | \r | |
240 | //\r | |
63197670 | 241 | // STEP 3:\r |
79e748cf JY |
242 | // Command Execution occurs after receipt of a 1 to Start and the TPM\r |
243 | // clearing Start to 0.\r | |
244 | //\r | |
245 | MmioWrite32((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);\r | |
246 | Status = PtpCrbWaitRegisterBits (\r | |
247 | &CrbReg->CrbControlStart,\r | |
248 | 0,\r | |
249 | PTP_CRB_CONTROL_START,\r | |
250 | PTP_TIMEOUT_MAX\r | |
251 | );\r | |
252 | if (EFI_ERROR (Status)) {\r | |
11cf02f6 ZC |
253 | //\r |
254 | // Command Completion check timeout. Cancel the currently executing command by writing TPM_CRB_CTRL_CANCEL,\r | |
255 | // Expect TPM_RC_CANCELLED or successfully completed response.\r | |
256 | //\r | |
257 | MmioWrite32((UINTN)&CrbReg->CrbControlCancel, PTP_CRB_CONTROL_CANCEL);\r | |
258 | Status = PtpCrbWaitRegisterBits (\r | |
259 | &CrbReg->CrbControlStart,\r | |
260 | 0,\r | |
261 | PTP_CRB_CONTROL_START,\r | |
262 | PTP_TIMEOUT_B\r | |
263 | );\r | |
264 | MmioWrite32((UINTN)&CrbReg->CrbControlCancel, 0);\r | |
265 | \r | |
266 | if (EFI_ERROR(Status)) {\r | |
267 | //\r | |
268 | // Still in Command Execution state. Try to goIdle, the behavior is agnostic.\r | |
269 | //\r | |
270 | Status = EFI_DEVICE_ERROR;\r | |
63197670 | 271 | goto GoIdle_Exit;\r |
11cf02f6 | 272 | }\r |
79e748cf JY |
273 | }\r |
274 | \r | |
275 | //\r | |
63197670 | 276 | // STEP 4:\r |
79e748cf JY |
277 | // Command Completion occurs after completion of a command (indicated by the\r |
278 | // TPM clearing TPM_CRB_CTRL_Start_x to 0) and before a write of a 1 by the\r | |
279 | // software to Request.goIdle.\r | |
280 | //\r | |
281 | \r | |
282 | //\r | |
283 | // Get response data header\r | |
284 | //\r | |
285 | for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {\r | |
286 | BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);\r | |
287 | }\r | |
f9f4fb23 | 288 | DEBUG_CODE_BEGIN ();\r |
e905fbb0 | 289 | DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand ReceiveHeader - "));\r |
79e748cf | 290 | for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {\r |
e905fbb0 | 291 | DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));\r |
79e748cf | 292 | }\r |
e905fbb0 | 293 | DEBUG ((DEBUG_VERBOSE, "\n"));\r |
f9f4fb23 | 294 | DEBUG_CODE_END ();\r |
79e748cf | 295 | //\r |
f9fd0c21 | 296 | // Check the response data header (tag, parasize and returncode)\r |
79e748cf JY |
297 | //\r |
298 | CopyMem (&Data16, BufferOut, sizeof (UINT16));\r | |
299 | // TPM2 should not use this RSP_COMMAND\r | |
300 | if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {\r | |
e905fbb0 | 301 | DEBUG ((DEBUG_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));\r |
79e748cf | 302 | Status = EFI_UNSUPPORTED;\r |
63197670 | 303 | goto GoIdle_Exit;\r |
79e748cf JY |
304 | }\r |
305 | \r | |
306 | CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r | |
307 | TpmOutSize = SwapBytes32 (Data32);\r | |
308 | if (*SizeOut < TpmOutSize) {\r | |
63197670 ZC |
309 | //\r |
310 | // Command completed, but buffer is not enough\r | |
311 | //\r | |
79e748cf | 312 | Status = EFI_BUFFER_TOO_SMALL;\r |
63197670 | 313 | goto GoReady_Exit;\r |
79e748cf JY |
314 | }\r |
315 | *SizeOut = TpmOutSize;\r | |
316 | //\r | |
317 | // Continue reading the remaining data\r | |
318 | //\r | |
319 | for (Index = sizeof (TPM2_RESPONSE_HEADER); Index < TpmOutSize; Index++) {\r | |
320 | BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);\r | |
321 | }\r | |
63197670 | 322 | \r |
f9f4fb23 | 323 | DEBUG_CODE_BEGIN ();\r |
e905fbb0 | 324 | DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand Receive - "));\r |
79e748cf | 325 | for (Index = 0; Index < TpmOutSize; Index++) {\r |
e905fbb0 | 326 | DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));\r |
79e748cf | 327 | }\r |
e905fbb0 | 328 | DEBUG ((DEBUG_VERBOSE, "\n"));\r |
f9f4fb23 | 329 | DEBUG_CODE_END ();\r |
79e748cf | 330 | \r |
63197670 | 331 | GoReady_Exit:\r |
79e748cf | 332 | //\r |
d6b926e7 | 333 | // Goto Ready State if command is completed successfully and TPM support IdleBypass\r |
63197670 ZC |
334 | // If not supported. flow down to GoIdle\r |
335 | //\r | |
7a56650e | 336 | if (GetCachedIdleByPass () == 1) {\r |
63197670 ZC |
337 | MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);\r |
338 | return Status;\r | |
339 | }\r | |
340 | \r | |
341 | //\r | |
342 | // Do not wait for state transition for TIMEOUT_C\r | |
343 | // This function will try to wait 2 TIMEOUT_C at the beginning in next call.\r | |
344 | //\r | |
345 | GoIdle_Exit:\r | |
346 | \r | |
347 | //\r | |
348 | // Return to Idle state by setting TPM_CRB_CTRL_STS_x.Status.goIdle to 1.\r | |
79e748cf JY |
349 | //\r |
350 | MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);\r | |
63197670 ZC |
351 | \r |
352 | //\r | |
d6b926e7 | 353 | // Only enforce Idle state transition if execution fails when CRBIdleBypass==1\r |
63197670 ZC |
354 | // Leave regular Idle delay at the beginning of next command execution\r |
355 | //\r | |
7a56650e | 356 | if (GetCachedIdleByPass () == 1){\r |
63197670 ZC |
357 | Status = PtpCrbWaitRegisterBits (\r |
358 | &CrbReg->CrbControlStatus,\r | |
359 | PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,\r | |
360 | 0,\r | |
361 | PTP_TIMEOUT_C\r | |
362 | );\r | |
363 | }\r | |
364 | \r | |
79e748cf JY |
365 | return Status;\r |
366 | }\r | |
367 | \r | |
368 | /**\r | |
369 | Send a command to TPM for execution and return response data.\r | |
370 | \r | |
371 | @param[in] TisReg TPM register space base address.\r | |
372 | @param[in] BufferIn Buffer for command data.\r | |
373 | @param[in] SizeIn Size of command data.\r | |
374 | @param[in, out] BufferOut Buffer for response data.\r | |
375 | @param[in, out] SizeOut Size of response data.\r | |
376 | \r | |
377 | @retval EFI_SUCCESS Operation completed successfully.\r | |
378 | @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r | |
379 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
380 | @retval EFI_UNSUPPORTED Unsupported TPM version\r | |
381 | \r | |
382 | **/\r | |
383 | EFI_STATUS\r | |
384 | Tpm2TisTpmCommand (\r | |
385 | IN TIS_PC_REGISTERS_PTR TisReg,\r | |
386 | IN UINT8 *BufferIn,\r | |
387 | IN UINT32 SizeIn,\r | |
388 | IN OUT UINT8 *BufferOut,\r | |
389 | IN OUT UINT32 *SizeOut\r | |
390 | );\r | |
391 | \r | |
392 | /**\r | |
393 | Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE\r | |
394 | to ACCESS Register in the time of default TIS_TIMEOUT_A.\r | |
395 | \r | |
396 | @param[in] TisReg Pointer to TIS register.\r | |
397 | \r | |
398 | @retval EFI_SUCCESS Get the control of TPM chip.\r | |
399 | @retval EFI_INVALID_PARAMETER TisReg is NULL.\r | |
400 | @retval EFI_NOT_FOUND TPM chip doesn't exit.\r | |
401 | @retval EFI_TIMEOUT Can't get the TPM control in time.\r | |
402 | **/\r | |
403 | EFI_STATUS\r | |
404 | TisPcRequestUseTpm (\r | |
405 | IN TIS_PC_REGISTERS_PTR TisReg\r | |
406 | );\r | |
407 | \r | |
408 | /**\r | |
409 | Return PTP interface type.\r | |
410 | \r | |
411 | @param[in] Register Pointer to PTP register.\r | |
412 | \r | |
413 | @return PTP interface type.\r | |
414 | **/\r | |
f15cb995 | 415 | TPM2_PTP_INTERFACE_TYPE\r |
0e47ac15 | 416 | Tpm2GetPtpInterface (\r |
79e748cf JY |
417 | IN VOID *Register\r |
418 | )\r | |
419 | {\r | |
420 | PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;\r | |
421 | PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;\r | |
422 | \r | |
0e47ac15 | 423 | if (!Tpm2IsPtpPresence (Register)) {\r |
f15cb995 | 424 | return Tpm2PtpInterfaceMax;\r |
79e748cf JY |
425 | }\r |
426 | //\r | |
427 | // Check interface id\r | |
428 | //\r | |
429 | InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r | |
430 | InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);\r | |
431 | \r | |
432 | if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&\r | |
433 | (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&\r | |
434 | (InterfaceId.Bits.CapCRB != 0)) {\r | |
f15cb995 | 435 | return Tpm2PtpInterfaceCrb;\r |
79e748cf JY |
436 | }\r |
437 | if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&\r | |
438 | (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&\r | |
439 | (InterfaceId.Bits.CapFIFO != 0) &&\r | |
440 | (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {\r | |
f15cb995 | 441 | return Tpm2PtpInterfaceFifo;\r |
79e748cf | 442 | }\r |
f15cb995 | 443 | return Tpm2PtpInterfaceTis;\r |
79e748cf JY |
444 | }\r |
445 | \r | |
63197670 ZC |
446 | /**\r |
447 | Return PTP CRB interface IdleByPass state.\r | |
448 | \r | |
449 | @param[in] Register Pointer to PTP register.\r | |
450 | \r | |
451 | @return PTP CRB interface IdleByPass state.\r | |
452 | **/\r | |
453 | UINT8\r | |
454 | Tpm2GetIdleByPass (\r | |
455 | IN VOID *Register\r | |
456 | )\r | |
457 | {\r | |
458 | PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;\r | |
459 | \r | |
460 | //\r | |
461 | // Check interface id\r | |
462 | //\r | |
463 | InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r | |
464 | \r | |
465 | return (UINT8)(InterfaceId.Bits.CapCRBIdleBypass);\r | |
466 | }\r | |
467 | \r | |
79e748cf JY |
468 | /**\r |
469 | Dump PTP register information.\r | |
470 | \r | |
471 | @param[in] Register Pointer to PTP register.\r | |
472 | **/\r | |
473 | VOID\r | |
474 | DumpPtpInfo (\r | |
475 | IN VOID *Register\r | |
476 | )\r | |
477 | {\r | |
478 | PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;\r | |
479 | PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;\r | |
480 | UINT8 StatusEx;\r | |
481 | UINT16 Vid;\r | |
482 | UINT16 Did;\r | |
483 | UINT8 Rid;\r | |
f15cb995 | 484 | TPM2_PTP_INTERFACE_TYPE PtpInterface;\r |
79e748cf | 485 | \r |
0e47ac15 | 486 | if (!Tpm2IsPtpPresence (Register)) {\r |
79e748cf JY |
487 | return ;\r |
488 | }\r | |
489 | \r | |
490 | InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r | |
491 | InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);\r | |
492 | StatusEx = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);\r | |
493 | \r | |
494 | //\r | |
495 | // Dump InterfaceId Register for PTP\r | |
496 | //\r | |
e905fbb0 MK |
497 | DEBUG ((DEBUG_INFO, "InterfaceId - 0x%08x\n", InterfaceId.Uint32));\r |
498 | DEBUG ((DEBUG_INFO, " InterfaceType - 0x%02x\n", InterfaceId.Bits.InterfaceType));\r | |
79e748cf | 499 | if (InterfaceId.Bits.InterfaceType != PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) {\r |
e905fbb0 MK |
500 | DEBUG ((DEBUG_INFO, " InterfaceVersion - 0x%02x\n", InterfaceId.Bits.InterfaceVersion));\r |
501 | DEBUG ((DEBUG_INFO, " CapFIFO - 0x%x\n", InterfaceId.Bits.CapFIFO));\r | |
502 | DEBUG ((DEBUG_INFO, " CapCRB - 0x%x\n", InterfaceId.Bits.CapCRB));\r | |
79e748cf JY |
503 | }\r |
504 | \r | |
505 | //\r | |
506 | // Dump Capability Register for TIS and FIFO\r | |
507 | //\r | |
e905fbb0 | 508 | DEBUG ((DEBUG_INFO, "InterfaceCapability - 0x%08x\n", InterfaceCapability.Uint32));\r |
79e748cf JY |
509 | if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) ||\r |
510 | (InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO)) {\r | |
e905fbb0 | 511 | DEBUG ((DEBUG_INFO, " InterfaceVersion - 0x%x\n", InterfaceCapability.Bits.InterfaceVersion));\r |
79e748cf JY |
512 | }\r |
513 | \r | |
514 | //\r | |
515 | // Dump StatusEx Register for PTP FIFO\r | |
516 | //\r | |
e905fbb0 | 517 | DEBUG ((DEBUG_INFO, "StatusEx - 0x%02x\n", StatusEx));\r |
79e748cf | 518 | if (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP) {\r |
e905fbb0 | 519 | DEBUG ((DEBUG_INFO, " TpmFamily - 0x%x\n", (StatusEx & PTP_FIFO_STS_EX_TPM_FAMILY) >> PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET));\r |
79e748cf JY |
520 | }\r |
521 | \r | |
522 | Vid = 0xFFFF;\r | |
523 | Did = 0xFFFF;\r | |
524 | Rid = 0xFF;\r | |
7a56650e | 525 | PtpInterface = GetCachedPtpInterface ();\r |
e905fbb0 | 526 | DEBUG ((DEBUG_INFO, "PtpInterface - %x\n", PtpInterface));\r |
79e748cf | 527 | switch (PtpInterface) {\r |
f15cb995 | 528 | case Tpm2PtpInterfaceCrb:\r |
79e748cf JY |
529 | Vid = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);\r |
530 | Did = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);\r | |
531 | Rid = (UINT8)InterfaceId.Bits.Rid;\r | |
532 | break;\r | |
f15cb995 ZC |
533 | case Tpm2PtpInterfaceFifo:\r |
534 | case Tpm2PtpInterfaceTis:\r | |
79e748cf JY |
535 | Vid = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);\r |
536 | Did = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);\r | |
537 | Rid = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);\r | |
538 | break;\r | |
539 | default:\r | |
540 | break;\r | |
541 | }\r | |
e905fbb0 MK |
542 | DEBUG ((DEBUG_INFO, "VID - 0x%04x\n", Vid));\r |
543 | DEBUG ((DEBUG_INFO, "DID - 0x%04x\n", Did));\r | |
544 | DEBUG ((DEBUG_INFO, "RID - 0x%02x\n", Rid));\r | |
79e748cf JY |
545 | }\r |
546 | \r | |
547 | /**\r | |
548 | This service enables the sending of commands to the TPM2.\r | |
549 | \r | |
550 | @param[in] InputParameterBlockSize Size of the TPM2 input parameter block.\r | |
551 | @param[in] InputParameterBlock Pointer to the TPM2 input parameter block.\r | |
552 | @param[in,out] OutputParameterBlockSize Size of the TPM2 output parameter block.\r | |
553 | @param[in] OutputParameterBlock Pointer to the TPM2 output parameter block.\r | |
554 | \r | |
555 | @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.\r | |
556 | @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.\r | |
557 | @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.\r | |
558 | **/\r | |
559 | EFI_STATUS\r | |
560 | EFIAPI\r | |
561 | DTpm2SubmitCommand (\r | |
562 | IN UINT32 InputParameterBlockSize,\r | |
563 | IN UINT8 *InputParameterBlock,\r | |
564 | IN OUT UINT32 *OutputParameterBlockSize,\r | |
565 | IN UINT8 *OutputParameterBlock\r | |
566 | )\r | |
567 | {\r | |
f15cb995 | 568 | TPM2_PTP_INTERFACE_TYPE PtpInterface;\r |
79e748cf | 569 | \r |
7a56650e | 570 | PtpInterface = GetCachedPtpInterface ();\r |
79e748cf | 571 | switch (PtpInterface) {\r |
f15cb995 | 572 | case Tpm2PtpInterfaceCrb:\r |
79e748cf JY |
573 | return PtpCrbTpmCommand (\r |
574 | (PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r | |
575 | InputParameterBlock,\r | |
576 | InputParameterBlockSize,\r | |
577 | OutputParameterBlock,\r | |
578 | OutputParameterBlockSize\r | |
579 | );\r | |
f15cb995 ZC |
580 | case Tpm2PtpInterfaceFifo:\r |
581 | case Tpm2PtpInterfaceTis:\r | |
79e748cf JY |
582 | return Tpm2TisTpmCommand (\r |
583 | (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r | |
584 | InputParameterBlock,\r | |
585 | InputParameterBlockSize,\r | |
586 | OutputParameterBlock,\r | |
587 | OutputParameterBlockSize\r | |
588 | );\r | |
589 | default:\r | |
590 | return EFI_NOT_FOUND;\r | |
591 | }\r | |
592 | }\r | |
593 | \r | |
594 | /**\r | |
595 | This service requests use TPM2.\r | |
596 | \r | |
597 | @retval EFI_SUCCESS Get the control of TPM2 chip.\r | |
598 | @retval EFI_NOT_FOUND TPM2 not found.\r | |
599 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
600 | **/\r | |
601 | EFI_STATUS\r | |
602 | EFIAPI\r | |
603 | DTpm2RequestUseTpm (\r | |
604 | VOID\r | |
605 | )\r | |
606 | {\r | |
f15cb995 | 607 | TPM2_PTP_INTERFACE_TYPE PtpInterface;\r |
79e748cf | 608 | \r |
7a56650e | 609 | PtpInterface = GetCachedPtpInterface ();\r |
79e748cf | 610 | switch (PtpInterface) {\r |
f15cb995 | 611 | case Tpm2PtpInterfaceCrb:\r |
79e748cf | 612 | return PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r |
f15cb995 ZC |
613 | case Tpm2PtpInterfaceFifo:\r |
614 | case Tpm2PtpInterfaceTis:\r | |
79e748cf JY |
615 | return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r |
616 | default:\r | |
617 | return EFI_NOT_FOUND;\r | |
618 | }\r | |
619 | }\r |