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79e748cf JY |
1 | /** @file\r |
2 | PTP (Platform TPM Profile) CRB (Command Response Buffer) interface used by dTPM2.0 library.\r | |
3 | \r | |
11cf02f6 | 4 | Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r |
79e748cf JY |
5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <IndustryStandard/Tpm20.h>\r | |
16 | \r | |
17 | #include <Library/BaseLib.h>\r | |
18 | #include <Library/BaseMemoryLib.h>\r | |
19 | #include <Library/IoLib.h>\r | |
20 | #include <Library/TimerLib.h>\r | |
21 | #include <Library/DebugLib.h>\r | |
22 | #include <Library/Tpm2DeviceLib.h>\r | |
23 | #include <Library/PcdLib.h>\r | |
24 | \r | |
25 | #include <IndustryStandard/TpmPtp.h>\r | |
26 | #include <IndustryStandard/TpmTis.h>\r | |
27 | \r | |
79e748cf JY |
28 | //\r |
29 | // Execution of the command may take from several seconds to minutes for certain\r | |
30 | // commands, such as key generation.\r | |
31 | //\r | |
32 | #define PTP_TIMEOUT_MAX (90000 * 1000) // 90s\r | |
33 | \r | |
34 | //\r | |
35 | // Max TPM command/reponse length\r | |
36 | //\r | |
37 | #define TPMCMDBUFLENGTH 0x500\r | |
38 | \r | |
39 | /**\r | |
40 | Check whether TPM PTP register exist.\r | |
41 | \r | |
42 | @param[in] Reg Pointer to PTP register.\r | |
43 | \r | |
44 | @retval TRUE TPM PTP exists.\r | |
45 | @retval FALSE TPM PTP is not found.\r | |
46 | **/\r | |
47 | BOOLEAN\r | |
0e47ac15 | 48 | Tpm2IsPtpPresence (\r |
79e748cf JY |
49 | IN VOID *Reg\r |
50 | )\r | |
51 | {\r | |
52 | UINT8 RegRead;\r | |
53 | \r | |
54 | RegRead = MmioRead8 ((UINTN)Reg);\r | |
55 | if (RegRead == 0xFF) {\r | |
56 | //\r | |
57 | // No TPM chip\r | |
58 | //\r | |
59 | return FALSE;\r | |
60 | }\r | |
61 | return TRUE;\r | |
62 | }\r | |
63 | \r | |
64 | /**\r | |
65 | Check whether the value of a TPM chip register satisfies the input BIT setting.\r | |
66 | \r | |
67 | @param[in] Register Address port of register to be checked.\r | |
68 | @param[in] BitSet Check these data bits are set.\r | |
69 | @param[in] BitClear Check these data bits are clear.\r | |
70 | @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r | |
71 | \r | |
72 | @retval EFI_SUCCESS The register satisfies the check bit.\r | |
73 | @retval EFI_TIMEOUT The register can't run into the expected status in time.\r | |
74 | **/\r | |
75 | EFI_STATUS\r | |
76 | PtpCrbWaitRegisterBits (\r | |
77 | IN UINT32 *Register,\r | |
78 | IN UINT32 BitSet,\r | |
79 | IN UINT32 BitClear,\r | |
80 | IN UINT32 TimeOut\r | |
81 | )\r | |
82 | {\r | |
83 | UINT32 RegRead;\r | |
84 | UINT32 WaitTime;\r | |
85 | \r | |
86 | for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r | |
87 | RegRead = MmioRead32 ((UINTN)Register);\r | |
88 | if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {\r | |
89 | return EFI_SUCCESS;\r | |
90 | }\r | |
91 | MicroSecondDelay (30);\r | |
92 | }\r | |
93 | return EFI_TIMEOUT;\r | |
94 | }\r | |
95 | \r | |
96 | /**\r | |
97 | Get the control of TPM chip.\r | |
98 | \r | |
99 | @param[in] CrbReg Pointer to CRB register.\r | |
100 | \r | |
101 | @retval EFI_SUCCESS Get the control of TPM chip.\r | |
102 | @retval EFI_INVALID_PARAMETER CrbReg is NULL.\r | |
103 | @retval EFI_NOT_FOUND TPM chip doesn't exit.\r | |
104 | @retval EFI_TIMEOUT Can't get the TPM control in time.\r | |
105 | **/\r | |
106 | EFI_STATUS\r | |
107 | PtpCrbRequestUseTpm (\r | |
108 | IN PTP_CRB_REGISTERS_PTR CrbReg\r | |
109 | )\r | |
110 | {\r | |
111 | EFI_STATUS Status;\r | |
112 | \r | |
0e47ac15 | 113 | if (!Tpm2IsPtpPresence (CrbReg)) {\r |
79e748cf JY |
114 | return EFI_NOT_FOUND;\r |
115 | }\r | |
116 | \r | |
117 | MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);\r | |
118 | Status = PtpCrbWaitRegisterBits (\r | |
119 | &CrbReg->LocalityStatus,\r | |
120 | PTP_CRB_LOCALITY_STATUS_GRANTED,\r | |
121 | 0,\r | |
122 | PTP_TIMEOUT_A\r | |
123 | );\r | |
124 | return Status;\r | |
125 | }\r | |
126 | \r | |
127 | /**\r | |
128 | Send a command to TPM for execution and return response data.\r | |
129 | \r | |
130 | @param[in] CrbReg TPM register space base address.\r | |
131 | @param[in] BufferIn Buffer for command data.\r | |
132 | @param[in] SizeIn Size of command data.\r | |
133 | @param[in, out] BufferOut Buffer for response data.\r | |
134 | @param[in, out] SizeOut Size of response data.\r | |
135 | \r | |
136 | @retval EFI_SUCCESS Operation completed successfully.\r | |
137 | @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r | |
138 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
139 | @retval EFI_UNSUPPORTED Unsupported TPM version\r | |
140 | \r | |
141 | **/\r | |
142 | EFI_STATUS\r | |
143 | PtpCrbTpmCommand (\r | |
144 | IN PTP_CRB_REGISTERS_PTR CrbReg,\r | |
145 | IN UINT8 *BufferIn,\r | |
146 | IN UINT32 SizeIn,\r | |
147 | IN OUT UINT8 *BufferOut,\r | |
148 | IN OUT UINT32 *SizeOut\r | |
149 | )\r | |
150 | {\r | |
151 | EFI_STATUS Status;\r | |
152 | UINT32 Index;\r | |
153 | UINT32 TpmOutSize;\r | |
154 | UINT16 Data16;\r | |
155 | UINT32 Data32;\r | |
156 | \r | |
157 | DEBUG_CODE (\r | |
158 | UINTN DebugSize;\r | |
159 | \r | |
160 | DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand Send - "));\r | |
161 | if (SizeIn > 0x100) {\r | |
162 | DebugSize = 0x40;\r | |
163 | } else {\r | |
164 | DebugSize = SizeIn;\r | |
165 | }\r | |
166 | for (Index = 0; Index < DebugSize; Index++) {\r | |
167 | DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r | |
168 | }\r | |
169 | if (DebugSize != SizeIn) {\r | |
170 | DEBUG ((EFI_D_VERBOSE, "...... "));\r | |
171 | for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r | |
172 | DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r | |
173 | }\r | |
174 | }\r | |
175 | DEBUG ((EFI_D_VERBOSE, "\n"));\r | |
176 | );\r | |
177 | TpmOutSize = 0;\r | |
178 | \r | |
179 | //\r | |
180 | // STEP 0:\r | |
181 | // Ready is any time the TPM is ready to receive a command, following a write\r | |
182 | // of 1 by software to Request.cmdReady, as indicated by the Status field\r | |
183 | // being cleared to 0.\r | |
184 | //\r | |
185 | MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);\r | |
186 | Status = PtpCrbWaitRegisterBits (\r | |
187 | &CrbReg->CrbControlRequest,\r | |
188 | 0,\r | |
189 | PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY,\r | |
190 | PTP_TIMEOUT_C\r | |
191 | );\r | |
192 | if (EFI_ERROR (Status)) {\r | |
193 | Status = EFI_DEVICE_ERROR;\r | |
194 | goto Exit;\r | |
195 | }\r | |
196 | Status = PtpCrbWaitRegisterBits (\r | |
197 | &CrbReg->CrbControlStatus,\r | |
198 | 0,\r | |
199 | PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,\r | |
200 | PTP_TIMEOUT_C\r | |
201 | );\r | |
202 | if (EFI_ERROR (Status)) {\r | |
203 | Status = EFI_DEVICE_ERROR;\r | |
204 | goto Exit;\r | |
205 | }\r | |
206 | \r | |
207 | //\r | |
208 | // STEP 1:\r | |
209 | // Command Reception occurs following a Ready state between the write of the\r | |
210 | // first byte of a command to the Command Buffer and the receipt of a write\r | |
211 | // of 1 to Start.\r | |
212 | //\r | |
213 | for (Index = 0; Index < SizeIn; Index++) {\r | |
214 | MmioWrite8 ((UINTN)&CrbReg->CrbDataBuffer[Index], BufferIn[Index]);\r | |
215 | }\r | |
216 | MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));\r | |
217 | MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);\r | |
218 | MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof(CrbReg->CrbDataBuffer));\r | |
219 | \r | |
220 | MmioWrite64 ((UINTN)&CrbReg->CrbControlResponseAddrss, (UINT32)(UINTN)CrbReg->CrbDataBuffer);\r | |
221 | MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof(CrbReg->CrbDataBuffer));\r | |
222 | \r | |
223 | //\r | |
224 | // STEP 2:\r | |
225 | // Command Execution occurs after receipt of a 1 to Start and the TPM\r | |
226 | // clearing Start to 0.\r | |
227 | //\r | |
228 | MmioWrite32((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);\r | |
229 | Status = PtpCrbWaitRegisterBits (\r | |
230 | &CrbReg->CrbControlStart,\r | |
231 | 0,\r | |
232 | PTP_CRB_CONTROL_START,\r | |
233 | PTP_TIMEOUT_MAX\r | |
234 | );\r | |
235 | if (EFI_ERROR (Status)) {\r | |
11cf02f6 ZC |
236 | //\r |
237 | // Command Completion check timeout. Cancel the currently executing command by writing TPM_CRB_CTRL_CANCEL,\r | |
238 | // Expect TPM_RC_CANCELLED or successfully completed response.\r | |
239 | //\r | |
240 | MmioWrite32((UINTN)&CrbReg->CrbControlCancel, PTP_CRB_CONTROL_CANCEL);\r | |
241 | Status = PtpCrbWaitRegisterBits (\r | |
242 | &CrbReg->CrbControlStart,\r | |
243 | 0,\r | |
244 | PTP_CRB_CONTROL_START,\r | |
245 | PTP_TIMEOUT_B\r | |
246 | );\r | |
247 | MmioWrite32((UINTN)&CrbReg->CrbControlCancel, 0);\r | |
248 | \r | |
249 | if (EFI_ERROR(Status)) {\r | |
250 | //\r | |
251 | // Still in Command Execution state. Try to goIdle, the behavior is agnostic.\r | |
252 | //\r | |
253 | Status = EFI_DEVICE_ERROR;\r | |
254 | goto Exit;\r | |
255 | }\r | |
79e748cf JY |
256 | }\r |
257 | \r | |
258 | //\r | |
259 | // STEP 3:\r | |
260 | // Command Completion occurs after completion of a command (indicated by the\r | |
261 | // TPM clearing TPM_CRB_CTRL_Start_x to 0) and before a write of a 1 by the\r | |
262 | // software to Request.goIdle.\r | |
263 | //\r | |
264 | \r | |
265 | //\r | |
266 | // Get response data header\r | |
267 | //\r | |
268 | for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {\r | |
269 | BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);\r | |
270 | }\r | |
271 | DEBUG_CODE (\r | |
272 | DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand ReceiveHeader - "));\r | |
273 | for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {\r | |
274 | DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r | |
275 | }\r | |
276 | DEBUG ((EFI_D_VERBOSE, "\n"));\r | |
277 | );\r | |
278 | //\r | |
279 | // Check the reponse data header (tag, parasize and returncode)\r | |
280 | //\r | |
281 | CopyMem (&Data16, BufferOut, sizeof (UINT16));\r | |
282 | // TPM2 should not use this RSP_COMMAND\r | |
283 | if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {\r | |
284 | DEBUG ((EFI_D_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));\r | |
285 | Status = EFI_UNSUPPORTED;\r | |
286 | goto Exit;\r | |
287 | }\r | |
288 | \r | |
289 | CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r | |
290 | TpmOutSize = SwapBytes32 (Data32);\r | |
291 | if (*SizeOut < TpmOutSize) {\r | |
292 | Status = EFI_BUFFER_TOO_SMALL;\r | |
293 | goto Exit;\r | |
294 | }\r | |
295 | *SizeOut = TpmOutSize;\r | |
296 | //\r | |
297 | // Continue reading the remaining data\r | |
298 | //\r | |
299 | for (Index = sizeof (TPM2_RESPONSE_HEADER); Index < TpmOutSize; Index++) {\r | |
300 | BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);\r | |
301 | }\r | |
302 | Exit:\r | |
303 | DEBUG_CODE (\r | |
304 | DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand Receive - "));\r | |
305 | for (Index = 0; Index < TpmOutSize; Index++) {\r | |
306 | DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r | |
307 | }\r | |
308 | DEBUG ((EFI_D_VERBOSE, "\n"));\r | |
309 | );\r | |
310 | \r | |
311 | //\r | |
312 | // STEP 4:\r | |
313 | // Idle is any time TPM_CRB_CTRL_STS_x.Status.goIdle is 1.\r | |
314 | //\r | |
315 | MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);\r | |
316 | return Status;\r | |
317 | }\r | |
318 | \r | |
319 | /**\r | |
320 | Send a command to TPM for execution and return response data.\r | |
321 | \r | |
322 | @param[in] TisReg TPM register space base address.\r | |
323 | @param[in] BufferIn Buffer for command data.\r | |
324 | @param[in] SizeIn Size of command data.\r | |
325 | @param[in, out] BufferOut Buffer for response data.\r | |
326 | @param[in, out] SizeOut Size of response data.\r | |
327 | \r | |
328 | @retval EFI_SUCCESS Operation completed successfully.\r | |
329 | @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r | |
330 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
331 | @retval EFI_UNSUPPORTED Unsupported TPM version\r | |
332 | \r | |
333 | **/\r | |
334 | EFI_STATUS\r | |
335 | Tpm2TisTpmCommand (\r | |
336 | IN TIS_PC_REGISTERS_PTR TisReg,\r | |
337 | IN UINT8 *BufferIn,\r | |
338 | IN UINT32 SizeIn,\r | |
339 | IN OUT UINT8 *BufferOut,\r | |
340 | IN OUT UINT32 *SizeOut\r | |
341 | );\r | |
342 | \r | |
343 | /**\r | |
344 | Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE\r | |
345 | to ACCESS Register in the time of default TIS_TIMEOUT_A.\r | |
346 | \r | |
347 | @param[in] TisReg Pointer to TIS register.\r | |
348 | \r | |
349 | @retval EFI_SUCCESS Get the control of TPM chip.\r | |
350 | @retval EFI_INVALID_PARAMETER TisReg is NULL.\r | |
351 | @retval EFI_NOT_FOUND TPM chip doesn't exit.\r | |
352 | @retval EFI_TIMEOUT Can't get the TPM control in time.\r | |
353 | **/\r | |
354 | EFI_STATUS\r | |
355 | TisPcRequestUseTpm (\r | |
356 | IN TIS_PC_REGISTERS_PTR TisReg\r | |
357 | );\r | |
358 | \r | |
359 | /**\r | |
360 | Return PTP interface type.\r | |
361 | \r | |
362 | @param[in] Register Pointer to PTP register.\r | |
363 | \r | |
364 | @return PTP interface type.\r | |
365 | **/\r | |
f15cb995 | 366 | TPM2_PTP_INTERFACE_TYPE\r |
0e47ac15 | 367 | Tpm2GetPtpInterface (\r |
79e748cf JY |
368 | IN VOID *Register\r |
369 | )\r | |
370 | {\r | |
371 | PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;\r | |
372 | PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;\r | |
373 | \r | |
0e47ac15 | 374 | if (!Tpm2IsPtpPresence (Register)) {\r |
f15cb995 | 375 | return Tpm2PtpInterfaceMax;\r |
79e748cf JY |
376 | }\r |
377 | //\r | |
378 | // Check interface id\r | |
379 | //\r | |
380 | InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r | |
381 | InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);\r | |
382 | \r | |
383 | if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&\r | |
384 | (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&\r | |
385 | (InterfaceId.Bits.CapCRB != 0)) {\r | |
f15cb995 | 386 | return Tpm2PtpInterfaceCrb;\r |
79e748cf JY |
387 | }\r |
388 | if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&\r | |
389 | (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&\r | |
390 | (InterfaceId.Bits.CapFIFO != 0) &&\r | |
391 | (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {\r | |
f15cb995 | 392 | return Tpm2PtpInterfaceFifo;\r |
79e748cf | 393 | }\r |
f15cb995 | 394 | return Tpm2PtpInterfaceTis;\r |
79e748cf JY |
395 | }\r |
396 | \r | |
397 | /**\r | |
398 | Dump PTP register information.\r | |
399 | \r | |
400 | @param[in] Register Pointer to PTP register.\r | |
401 | **/\r | |
402 | VOID\r | |
403 | DumpPtpInfo (\r | |
404 | IN VOID *Register\r | |
405 | )\r | |
406 | {\r | |
407 | PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;\r | |
408 | PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;\r | |
409 | UINT8 StatusEx;\r | |
410 | UINT16 Vid;\r | |
411 | UINT16 Did;\r | |
412 | UINT8 Rid;\r | |
f15cb995 | 413 | TPM2_PTP_INTERFACE_TYPE PtpInterface;\r |
79e748cf | 414 | \r |
0e47ac15 | 415 | if (!Tpm2IsPtpPresence (Register)) {\r |
79e748cf JY |
416 | return ;\r |
417 | }\r | |
418 | \r | |
419 | InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r | |
420 | InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);\r | |
421 | StatusEx = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);\r | |
422 | \r | |
423 | //\r | |
424 | // Dump InterfaceId Register for PTP\r | |
425 | //\r | |
426 | DEBUG ((EFI_D_INFO, "InterfaceId - 0x%08x\n", InterfaceId.Uint32));\r | |
427 | DEBUG ((EFI_D_INFO, " InterfaceType - 0x%02x\n", InterfaceId.Bits.InterfaceType));\r | |
428 | if (InterfaceId.Bits.InterfaceType != PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) {\r | |
429 | DEBUG ((EFI_D_INFO, " InterfaceVersion - 0x%02x\n", InterfaceId.Bits.InterfaceVersion));\r | |
430 | DEBUG ((EFI_D_INFO, " CapFIFO - 0x%x\n", InterfaceId.Bits.CapFIFO));\r | |
431 | DEBUG ((EFI_D_INFO, " CapCRB - 0x%x\n", InterfaceId.Bits.CapCRB));\r | |
432 | }\r | |
433 | \r | |
434 | //\r | |
435 | // Dump Capability Register for TIS and FIFO\r | |
436 | //\r | |
437 | DEBUG ((EFI_D_INFO, "InterfaceCapability - 0x%08x\n", InterfaceCapability.Uint32));\r | |
438 | if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) ||\r | |
439 | (InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO)) {\r | |
440 | DEBUG ((EFI_D_INFO, " InterfaceVersion - 0x%x\n", InterfaceCapability.Bits.InterfaceVersion));\r | |
441 | }\r | |
442 | \r | |
443 | //\r | |
444 | // Dump StatusEx Register for PTP FIFO\r | |
445 | //\r | |
446 | DEBUG ((EFI_D_INFO, "StatusEx - 0x%02x\n", StatusEx));\r | |
447 | if (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP) {\r | |
448 | DEBUG ((EFI_D_INFO, " TpmFamily - 0x%x\n", (StatusEx & PTP_FIFO_STS_EX_TPM_FAMILY) >> PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET));\r | |
449 | }\r | |
450 | \r | |
451 | Vid = 0xFFFF;\r | |
452 | Did = 0xFFFF;\r | |
453 | Rid = 0xFF;\r | |
f15cb995 | 454 | PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);\r |
79e748cf JY |
455 | DEBUG ((EFI_D_INFO, "PtpInterface - %x\n", PtpInterface));\r |
456 | switch (PtpInterface) {\r | |
f15cb995 | 457 | case Tpm2PtpInterfaceCrb:\r |
79e748cf JY |
458 | Vid = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);\r |
459 | Did = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);\r | |
460 | Rid = (UINT8)InterfaceId.Bits.Rid;\r | |
461 | break;\r | |
f15cb995 ZC |
462 | case Tpm2PtpInterfaceFifo:\r |
463 | case Tpm2PtpInterfaceTis:\r | |
79e748cf JY |
464 | Vid = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);\r |
465 | Did = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);\r | |
466 | Rid = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);\r | |
467 | break;\r | |
468 | default:\r | |
469 | break;\r | |
470 | }\r | |
471 | DEBUG ((EFI_D_INFO, "VID - 0x%04x\n", Vid));\r | |
472 | DEBUG ((EFI_D_INFO, "DID - 0x%04x\n", Did));\r | |
473 | DEBUG ((EFI_D_INFO, "RID - 0x%02x\n", Rid));\r | |
474 | }\r | |
475 | \r | |
476 | /**\r | |
477 | This service enables the sending of commands to the TPM2.\r | |
478 | \r | |
479 | @param[in] InputParameterBlockSize Size of the TPM2 input parameter block.\r | |
480 | @param[in] InputParameterBlock Pointer to the TPM2 input parameter block.\r | |
481 | @param[in,out] OutputParameterBlockSize Size of the TPM2 output parameter block.\r | |
482 | @param[in] OutputParameterBlock Pointer to the TPM2 output parameter block.\r | |
483 | \r | |
484 | @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.\r | |
485 | @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.\r | |
486 | @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.\r | |
487 | **/\r | |
488 | EFI_STATUS\r | |
489 | EFIAPI\r | |
490 | DTpm2SubmitCommand (\r | |
491 | IN UINT32 InputParameterBlockSize,\r | |
492 | IN UINT8 *InputParameterBlock,\r | |
493 | IN OUT UINT32 *OutputParameterBlockSize,\r | |
494 | IN UINT8 *OutputParameterBlock\r | |
495 | )\r | |
496 | {\r | |
f15cb995 | 497 | TPM2_PTP_INTERFACE_TYPE PtpInterface;\r |
79e748cf | 498 | \r |
f15cb995 | 499 | PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);\r |
79e748cf | 500 | switch (PtpInterface) {\r |
f15cb995 | 501 | case Tpm2PtpInterfaceCrb:\r |
79e748cf JY |
502 | return PtpCrbTpmCommand (\r |
503 | (PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r | |
504 | InputParameterBlock,\r | |
505 | InputParameterBlockSize,\r | |
506 | OutputParameterBlock,\r | |
507 | OutputParameterBlockSize\r | |
508 | );\r | |
f15cb995 ZC |
509 | case Tpm2PtpInterfaceFifo:\r |
510 | case Tpm2PtpInterfaceTis:\r | |
79e748cf JY |
511 | return Tpm2TisTpmCommand (\r |
512 | (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r | |
513 | InputParameterBlock,\r | |
514 | InputParameterBlockSize,\r | |
515 | OutputParameterBlock,\r | |
516 | OutputParameterBlockSize\r | |
517 | );\r | |
518 | default:\r | |
519 | return EFI_NOT_FOUND;\r | |
520 | }\r | |
521 | }\r | |
522 | \r | |
523 | /**\r | |
524 | This service requests use TPM2.\r | |
525 | \r | |
526 | @retval EFI_SUCCESS Get the control of TPM2 chip.\r | |
527 | @retval EFI_NOT_FOUND TPM2 not found.\r | |
528 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
529 | **/\r | |
530 | EFI_STATUS\r | |
531 | EFIAPI\r | |
532 | DTpm2RequestUseTpm (\r | |
533 | VOID\r | |
534 | )\r | |
535 | {\r | |
f15cb995 | 536 | TPM2_PTP_INTERFACE_TYPE PtpInterface;\r |
79e748cf | 537 | \r |
f15cb995 | 538 | PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);\r |
79e748cf | 539 | switch (PtpInterface) {\r |
f15cb995 | 540 | case Tpm2PtpInterfaceCrb:\r |
79e748cf | 541 | return PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r |
f15cb995 ZC |
542 | case Tpm2PtpInterfaceFifo:\r |
543 | case Tpm2PtpInterfaceTis:\r | |
79e748cf JY |
544 | return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r |
545 | default:\r | |
546 | return EFI_NOT_FOUND;\r | |
547 | }\r | |
548 | }\r |