[mirror_edk2.git] / SecurityPkg / Tcg / Opal / OpalPassword / OpalNvmeMode.h

/** @file\r
  Header file for NVMe function definitions\r
\r
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __OPAL_PASSWORD_NVME_MODE_H__\r
#define __OPAL_PASSWORD_NVME_MODE_H__\r
\r
\r
#include "OpalNvmeReg.h"\r
\r
#define NVME_MAX_SECTORS            0x10000\r
//\r
// QueueId\r
//\r
#define NVME_ADMIN_QUEUE            0x00\r
#define NVME_IO_QUEUE               0x01\r
\r
typedef struct {\r
  UINT8                             Opcode;\r
  UINT8                             FusedOperation;\r
    #define NORMAL_CMD              0x00\r
    #define FUSED_FIRST_CMD         0x01\r
    #define FUSED_SECOND_CMD        0x02\r
  UINT16                            Cid;\r
} NVME_CDW0;\r
\r
typedef struct {\r
  NVME_CDW0                         Cdw0;\r
  UINT8                             Flags;\r
    #define CDW10_VALID             0x01\r
    #define CDW11_VALID             0x02\r
    #define CDW12_VALID             0x04\r
    #define CDW13_VALID             0x08\r
    #define CDW14_VALID             0x10\r
    #define CDW15_VALID             0x20\r
  UINT32                            Nsid;\r
  UINT32                            Cdw10;\r
  UINT32                            Cdw11;\r
  UINT32                            Cdw12;\r
  UINT32                            Cdw13;\r
  UINT32                            Cdw14;\r
  UINT32                            Cdw15;\r
} NVM_EXPRESS_COMMAND;\r
\r
typedef struct {\r
  UINT32                            Cdw0;\r
  UINT32                            Cdw1;\r
  UINT32                            Cdw2;\r
  UINT32                            Cdw3;\r
} NVM_EXPRESS_RESPONSE;\r
\r
typedef struct {\r
  UINT64                            CommandTimeout;\r
  UINT64                            TransferBuffer;\r
  UINT32                            TransferLength;\r
  UINT64                            MetadataBuffer;\r
  UINT32                            MetadataLength;\r
  UINT8                             QueueId;\r
  NVM_EXPRESS_COMMAND               *NvmeCmd;\r
  NVM_EXPRESS_RESPONSE              *NvmeResponse;\r
} NVM_EXPRESS_PASS_THRU_COMMAND_PACKET;\r
\r
\r
#pragma pack(1)\r
\r
// Internal fields\r
typedef enum {\r
  NvmeStatusUnknown,\r
  NvmeStatusInit,\r
  NvmeStatusInuse,\r
  NvmeStatusMax,\r
} NVME_STATUS;\r
\r
typedef struct {\r
  UINT32                            Nbar;\r
  VOID                              *BaseMem;\r
  VOID                              *BaseMemMapping;\r
  BOOLEAN                           PollCancellation;\r
  UINT16                            NvmeInitWaitTime;\r
\r
  NVME_STATUS                       State;\r
  UINT8                             BusID;\r
  UINT8                             DeviceID;\r
  UINT8                             FuncID;\r
  UINTN                             PciBase;\r
\r
  UINT32                            Nsid;\r
  UINT64                            Nsuuid;\r
  UINT32                            BlockSize;\r
  EFI_LBA                           LastBlock;\r
\r
  //\r
  // Pointers to 4kB aligned submission & completion queues.\r
  //\r
  NVME_SQ                           *SqBuffer[NVME_MAX_IO_QUEUES];\r
  NVME_CQ                           *CqBuffer[NVME_MAX_IO_QUEUES];\r
  UINT16                            Cid[NVME_MAX_IO_QUEUES];\r
\r
  //\r
  // Submission and completion queue indices.\r
  //\r
  NVME_SQTDBL                       SqTdbl[NVME_MAX_IO_QUEUES];\r
  NVME_CQHDBL                       CqHdbl[NVME_MAX_IO_QUEUES];\r
  UINT8                             Pt[NVME_MAX_IO_QUEUES];\r
\r
  UINTN                             SqeCount[NVME_MAX_IO_QUEUES];\r
\r
  //\r
  // Nvme controller capabilities\r
  //\r
  NVME_CAP                          Cap;\r
\r
  //\r
  // pointer to identify controller Data\r
  //\r
  NVME_ADMIN_CONTROLLER_DATA        *ControllerData;\r
  NVME_ADMIN_NAMESPACE_DATA         *NamespaceData;\r
} NVME_CONTEXT;\r
\r
#pragma pack()\r
\r
/**\r
  Transfer MMIO Data to memory.\r
\r
  @param[in,out] MemBuffer - Destination: Memory address\r
  @param[in] MmioAddr      - Source: MMIO address\r
  @param[in] Size          - Size for read\r
\r
  @retval EFI_SUCCESS - MMIO read sucessfully\r
**/\r
EFI_STATUS\r
NvmeMmioRead (\r
  IN OUT VOID *MemBuffer,\r
  IN     UINTN MmioAddr,\r
  IN     UINTN Size\r
  );\r
\r
/**\r
  Transfer memory Data to MMIO.\r
\r
  @param[in,out] MmioAddr - Destination: MMIO address\r
  @param[in] MemBuffer    - Source: Memory address\r
  @param[in] Size         - Size for write\r
\r
  @retval EFI_SUCCESS - MMIO write sucessfully\r
**/\r
EFI_STATUS\r
NvmeMmioWrite (\r
  IN OUT UINTN MmioAddr,\r
  IN     VOID *MemBuffer,\r
  IN     UINTN Size\r
  );\r
\r
/**\r
  Transfer memory data to MMIO.\r
\r
  @param[in,out] MmioAddr - Destination: MMIO address\r
  @param[in] MemBuffer    - Source: Memory address\r
  @param[in] Size         - Size for write\r
\r
  @retval EFI_SUCCESS - MMIO write sucessfully\r
**/\r
EFI_STATUS\r
OpalPciWrite (\r
  IN OUT UINTN MmioAddr,\r
  IN     VOID *MemBuffer,\r
  IN     UINTN Size\r
  );\r
\r
/**\r
  Transfer MMIO data to memory.\r
\r
  @param[in,out] MemBuffer - Destination: Memory address\r
  @param[in] MmioAddr      - Source: MMIO address\r
  @param[in] Size          - Size for read\r
\r
  @retval EFI_SUCCESS - MMIO read sucessfully\r
**/\r
EFI_STATUS\r
OpalPciRead (\r
  IN OUT VOID *MemBuffer,\r
  IN     UINTN MmioAddr,\r
  IN     UINTN Size\r
  );\r
\r
/**\r
  Allocate transfer-related Data struct which is used at Nvme.\r
\r
  @param[in, out] Nvme          The pointer to the NVME_CONTEXT Data structure.\r
\r
  @retval EFI_OUT_OF_RESOURCE   No enough resource.\r
  @retval EFI_SUCCESS           Successful to allocate resource.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
NvmeAllocateResource (\r
  IN OUT NVME_CONTEXT       *Nvme\r
  );\r
\r
/**\r
  Free allocated transfer-related Data struct which is used at NVMe.\r
\r
  @param[in, out] Nvme          The pointer to the NVME_CONTEXT Data structure.\r
\r
**/\r
VOID\r
EFIAPI\r
NvmeFreeResource (\r
  IN OUT NVME_CONTEXT       *Nvme\r
  );\r
\r
/**\r
  Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r
  both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the nonblocking\r
  I/O functionality is optional.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
  @param[in] NamespaceId            - Is a 32 bit Namespace ID to which the Express HCI command packet will be sent.\r
                                      A Value of 0 denotes the NVM Express controller, a Value of all 0FFh in the namespace\r
                                      ID specifies that the command packet should be sent to all valid namespaces.\r
  @param[in] NamespaceUuid          - Is a 64 bit Namespace UUID to which the Express HCI command packet will be sent.\r
                                      A Value of 0 denotes the NVM Express controller, a Value of all 0FFh in the namespace\r
                                      UUID specifies that the command packet should be sent to all valid namespaces.\r
  @param[in,out] Packet             - A pointer to the NVM Express HCI Command Packet to send to the NVMe namespace specified\r
                                      by NamespaceId.\r
\r
  @retval EFI_SUCCESS               - The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r
                                      to, or from DataBuffer.\r
  @retval EFI_NOT_READY             - The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r
                                      may retry again later.\r
  @retval EFI_DEVICE_ERROR          - A device error occurred while attempting to send the NVM Express Command Packet.\r
  @retval EFI_INVALID_PARAMETER     - Namespace, or the contents of NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r
                                      Express Command Packet was not sent, so no additional status information is available.\r
  @retval EFI_UNSUPPORTED           - The command described by the NVM Express Command Packet is not supported by the host adapter.\r
                                      The NVM Express Command Packet was not sent, so no additional status information is available.\r
  @retval EFI_TIMEOUT               - A timeout occurred while waiting for the NVM Express Command Packet to execute.\r
\r
**/\r
EFI_STATUS\r
NvmePassThru (\r
  IN     NVME_CONTEXT                         *Nvme,\r
  IN     UINT32                               NamespaceId,\r
  IN     UINT64                               NamespaceUuid,\r
  IN OUT NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet\r
  );\r
\r
/**\r
  Waits until all NVME commands completed.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
  @param[in] Qid                    - Queue index\r
\r
  @retval EFI_SUCCESS               - All NVME commands have completed\r
  @retval EFI_TIMEOUT               - Timeout occured\r
  @retval EFI_NOT_READY             - Not all NVME commands have completed\r
  @retval others                    - Error occurred on device side.\r
**/\r
EFI_STATUS\r
NvmeWaitAllComplete (\r
  IN NVME_CONTEXT       *Nvme,\r
  IN UINT8              Qid\r
  );\r
\r
/**\r
  Initialize the Nvm Express controller.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
\r
  @retval EFI_SUCCESS               - The NVM Express Controller is initialized successfully.\r
  @retval Others                    - A device error occurred while initializing the controller.\r
\r
**/\r
EFI_STATUS\r
NvmeControllerInit (\r
  IN NVME_CONTEXT       *Nvme\r
  );\r
\r
/**\r
  Un-initialize the Nvm Express controller.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
\r
  @retval EFI_SUCCESS               - The NVM Express Controller is un-initialized successfully.\r
  @retval Others                    - A device error occurred while un-initializing the controller.\r
\r
**/\r
EFI_STATUS\r
NvmeControllerExit (\r
  IN NVME_CONTEXT       *Nvme\r
  );\r
\r
/**\r
  Security send and receive commands.\r
\r
  @param[in]     Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
  @param[in]     SendCommand            - The flag to indicate the command type, TRUE for Send command and FALSE for receive command\r
  @param[in]     SecurityProtocol       - Security Protocol\r
  @param[in]     SpSpecific             - Security Protocol Specific\r
  @param[in]     TransferLength         - Transfer Length of Buffer (in bytes) - always a multiple of 512\r
  @param[in,out] TransferBuffer         - Address of Data to transfer\r
\r
  @return EFI_SUCCESS               - Successfully create io submission queue.\r
  @return others                    - Fail to send/receive commands.\r
\r
**/\r
EFI_STATUS\r
NvmeSecuritySendReceive (\r
  IN NVME_CONTEXT                          *Nvme,\r
  IN BOOLEAN                               SendCommand,\r
  IN UINT8                                 SecurityProtocol,\r
  IN UINT16                                SpSpecific,\r
  IN UINTN                                 TransferLength,\r
  IN OUT VOID                              *TransferBuffer\r
  );\r
\r
#endif\r
Commit	Line	Data
112e584b SZ	1	/** @file\r
	2	Header file for NVMe function definitions\r
	3	\r
	4	Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#ifndef __OPAL_PASSWORD_NVME_MODE_H__\r
	16	#define __OPAL_PASSWORD_NVME_MODE_H__\r
	17	\r
	18	\r
	19	#include "OpalNvmeReg.h"\r
	20	\r
	21	#define NVME_MAX_SECTORS 0x10000\r
	22	//\r
	23	// QueueId\r
	24	//\r
	25	#define NVME_ADMIN_QUEUE 0x00\r
	26	#define NVME_IO_QUEUE 0x01\r
	27	\r
	28	typedef struct {\r
	29	UINT8 Opcode;\r
	30	UINT8 FusedOperation;\r
	31	#define NORMAL_CMD 0x00\r
	32	#define FUSED_FIRST_CMD 0x01\r
	33	#define FUSED_SECOND_CMD 0x02\r
	34	UINT16 Cid;\r
	35	} NVME_CDW0;\r
	36	\r
	37	typedef struct {\r
	38	NVME_CDW0 Cdw0;\r
	39	UINT8 Flags;\r
	40	#define CDW10_VALID 0x01\r
	41	#define CDW11_VALID 0x02\r
	42	#define CDW12_VALID 0x04\r
	43	#define CDW13_VALID 0x08\r
	44	#define CDW14_VALID 0x10\r
	45	#define CDW15_VALID 0x20\r
	46	UINT32 Nsid;\r
	47	UINT32 Cdw10;\r
	48	UINT32 Cdw11;\r
	49	UINT32 Cdw12;\r
	50	UINT32 Cdw13;\r
	51	UINT32 Cdw14;\r
	52	UINT32 Cdw15;\r
	53	} NVM_EXPRESS_COMMAND;\r
	54	\r
	55	typedef struct {\r
	56	UINT32 Cdw0;\r
	57	UINT32 Cdw1;\r
	58	UINT32 Cdw2;\r
	59	UINT32 Cdw3;\r
	60	} NVM_EXPRESS_RESPONSE;\r
	61	\r
	62	typedef struct {\r
	63	UINT64 CommandTimeout;\r
	64	UINT64 TransferBuffer;\r
65	UINT32 TransferLength;\r
66	UINT64 MetadataBuffer;\r
67	UINT32 MetadataLength;\r
68	UINT8 QueueId;\r
69	NVM_EXPRESS_COMMAND *NvmeCmd;\r
70	NVM_EXPRESS_RESPONSE *NvmeResponse;\r
71	} NVM_EXPRESS_PASS_THRU_COMMAND_PACKET;\r
72	\r
73	\r
74	#pragma pack(1)\r
75	\r
76	// Internal fields\r
77	typedef enum {\r
78	NvmeStatusUnknown,\r
79	NvmeStatusInit,\r
80	NvmeStatusInuse,\r
81	NvmeStatusMax,\r
82	} NVME_STATUS;\r
83	\r
84	typedef struct {\r
85	UINT32 Nbar;\r
86	VOID *BaseMem;\r
87	VOID *BaseMemMapping;\r
88	BOOLEAN PollCancellation;\r
89	UINT16 NvmeInitWaitTime;\r
90	\r
91	NVME_STATUS State;\r
92	UINT8 BusID;\r
93	UINT8 DeviceID;\r
94	UINT8 FuncID;\r
95	UINTN PciBase;\r
96	\r
97	UINT32 Nsid;\r
98	UINT64 Nsuuid;\r
99	UINT32 BlockSize;\r
100	EFI_LBA LastBlock;\r
101	\r
102	//\r
103	// Pointers to 4kB aligned submission & completion queues.\r
104	//\r
105	NVME_SQ *SqBuffer[NVME_MAX_IO_QUEUES];\r
106	NVME_CQ *CqBuffer[NVME_MAX_IO_QUEUES];\r
107	UINT16 Cid[NVME_MAX_IO_QUEUES];\r
108	\r
109	//\r
110	// Submission and completion queue indices.\r
111	//\r
112	NVME_SQTDBL SqTdbl[NVME_MAX_IO_QUEUES];\r
113	NVME_CQHDBL CqHdbl[NVME_MAX_IO_QUEUES];\r
114	UINT8 Pt[NVME_MAX_IO_QUEUES];\r
115	\r
116	UINTN SqeCount[NVME_MAX_IO_QUEUES];\r
117	\r
118	//\r
119	// Nvme controller capabilities\r
120	//\r
121	NVME_CAP Cap;\r
122	\r
123	//\r
124	// pointer to identify controller Data\r
125	//\r
126	NVME_ADMIN_CONTROLLER_DATA *ControllerData;\r
127	NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r
128	} NVME_CONTEXT;\r
129	\r
130	#pragma pack()\r
131	\r
132	/**\r
133	Transfer MMIO Data to memory.\r
134	\r
135	@param[in,out] MemBuffer - Destination: Memory address\r
136	@param[in] MmioAddr - Source: MMIO address\r
137	@param[in] Size - Size for read\r
138	\r
139	@retval EFI_SUCCESS - MMIO read sucessfully\r
140	**/\r
141	EFI_STATUS\r
142	NvmeMmioRead (\r
143	IN OUT VOID *MemBuffer,\r
144	IN UINTN MmioAddr,\r
145	IN UINTN Size\r
146	);\r
147	\r
148	/**\r
149	Transfer memory Data to MMIO.\r
150	\r
151	@param[in,out] MmioAddr - Destination: MMIO address\r
152	@param[in] MemBuffer - Source: Memory address\r
153	@param[in] Size - Size for write\r
154	\r
155	@retval EFI_SUCCESS - MMIO write sucessfully\r
156	**/\r
157	EFI_STATUS\r
158	NvmeMmioWrite (\r
159	IN OUT UINTN MmioAddr,\r
160	IN VOID *MemBuffer,\r
161	IN UINTN Size\r
162	);\r
163	\r
164	/**\r
165	Transfer memory data to MMIO.\r
166	\r
167	@param[in,out] MmioAddr - Destination: MMIO address\r
168	@param[in] MemBuffer - Source: Memory address\r
169	@param[in] Size - Size for write\r
170	\r
171	@retval EFI_SUCCESS - MMIO write sucessfully\r
172	**/\r
173	EFI_STATUS\r
174	OpalPciWrite (\r
175	IN OUT UINTN MmioAddr,\r
176	IN VOID *MemBuffer,\r
177	IN UINTN Size\r
178	);\r
179	\r
180	/**\r
181	Transfer MMIO data to memory.\r
182	\r
183	@param[in,out] MemBuffer - Destination: Memory address\r
184	@param[in] MmioAddr - Source: MMIO address\r
185	@param[in] Size - Size for read\r
186	\r
187	@retval EFI_SUCCESS - MMIO read sucessfully\r
188	**/\r
189	EFI_STATUS\r
190	OpalPciRead (\r
191	IN OUT VOID *MemBuffer,\r
192	IN UINTN MmioAddr,\r
193	IN UINTN Size\r
194	);\r
195	\r
196	/**\r
197	Allocate transfer-related Data struct which is used at Nvme.\r
198	\r
199	@param[in, out] Nvme The pointer to the NVME_CONTEXT Data structure.\r
200	\r
201	@retval EFI_OUT_OF_RESOURCE No enough resource.\r
202	@retval EFI_SUCCESS Successful to allocate resource.\r
203	\r
204	**/\r
205	EFI_STATUS\r
206	EFIAPI\r
207	NvmeAllocateResource (\r
208	IN OUT NVME_CONTEXT *Nvme\r
209	);\r
210	\r
211	/**\r
212	Free allocated transfer-related Data struct which is used at NVMe.\r
213	\r
214	@param[in, out] Nvme The pointer to the NVME_CONTEXT Data structure.\r
215	\r
216	**/\r
217	VOID\r
218	EFIAPI\r
219	NvmeFreeResource (\r
220	IN OUT NVME_CONTEXT *Nvme\r
221	);\r
222	\r
223	/**\r
224	Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r
225	both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the nonblocking\r
226	I/O functionality is optional.\r
227	\r
228	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
229	@param[in] NamespaceId - Is a 32 bit Namespace ID to which the Express HCI command packet will be sent.\r
230	A Value of 0 denotes the NVM Express controller, a Value of all 0FFh in the namespace\r
231	ID specifies that the command packet should be sent to all valid namespaces.\r
232	@param[in] NamespaceUuid - Is a 64 bit Namespace UUID to which the Express HCI command packet will be sent.\r
233	A Value of 0 denotes the NVM Express controller, a Value of all 0FFh in the namespace\r
234	UUID specifies that the command packet should be sent to all valid namespaces.\r
235	@param[in,out] Packet - A pointer to the NVM Express HCI Command Packet to send to the NVMe namespace specified\r
236	by NamespaceId.\r
237	\r
238	@retval EFI_SUCCESS - The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r
239	to, or from DataBuffer.\r
240	@retval EFI_NOT_READY - The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r
241	may retry again later.\r
242	@retval EFI_DEVICE_ERROR - A device error occurred while attempting to send the NVM Express Command Packet.\r
243	@retval EFI_INVALID_PARAMETER - Namespace, or the contents of NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r
244	Express Command Packet was not sent, so no additional status information is available.\r
245	@retval EFI_UNSUPPORTED - The command described by the NVM Express Command Packet is not supported by the host adapter.\r
246	The NVM Express Command Packet was not sent, so no additional status information is available.\r
247	@retval EFI_TIMEOUT - A timeout occurred while waiting for the NVM Express Command Packet to execute.\r
248	\r
249	**/\r
250	EFI_STATUS\r
251	NvmePassThru (\r
252	IN NVME_CONTEXT *Nvme,\r
253	IN UINT32 NamespaceId,\r
254	IN UINT64 NamespaceUuid,\r
255	IN OUT NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet\r
256	);\r
257	\r
258	/**\r
259	Waits until all NVME commands completed.\r
260	\r
261	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
262	@param[in] Qid - Queue index\r
263	\r
264	@retval EFI_SUCCESS - All NVME commands have completed\r
265	@retval EFI_TIMEOUT - Timeout occured\r
266	@retval EFI_NOT_READY - Not all NVME commands have completed\r
267	@retval others - Error occurred on device side.\r
268	**/\r
269	EFI_STATUS\r
270	NvmeWaitAllComplete (\r
271	IN NVME_CONTEXT *Nvme,\r
272	IN UINT8 Qid\r
273	);\r
274	\r
275	/**\r
276	Initialize the Nvm Express controller.\r
277	\r
278	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
279	\r
280	@retval EFI_SUCCESS - The NVM Express Controller is initialized successfully.\r
281	@retval Others - A device error occurred while initializing the controller.\r
282	\r
283	**/\r
284	EFI_STATUS\r
285	NvmeControllerInit (\r
286	IN NVME_CONTEXT *Nvme\r
287	);\r
288	\r
289	/**\r
290	Un-initialize the Nvm Express controller.\r
291	\r
292	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
293	\r
294	@retval EFI_SUCCESS - The NVM Express Controller is un-initialized successfully.\r
295	@retval Others - A device error occurred while un-initializing the controller.\r
296	\r
297	**/\r
298	EFI_STATUS\r
299	NvmeControllerExit (\r
300	IN NVME_CONTEXT *Nvme\r
301	);\r
302	\r
112e584b SZ	303	/**\r
	304	Security send and receive commands.\r
	305	\r
	306	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
	307	@param[in] SendCommand - The flag to indicate the command type, TRUE for Send command and FALSE for receive command\r
	308	@param[in] SecurityProtocol - Security Protocol\r
	309	@param[in] SpSpecific - Security Protocol Specific\r
	310	@param[in] TransferLength - Transfer Length of Buffer (in bytes) - always a multiple of 512\r
	311	@param[in,out] TransferBuffer - Address of Data to transfer\r
	312	\r
	313	@return EFI_SUCCESS - Successfully create io submission queue.\r
	314	@return others - Fail to send/receive commands.\r
	315	\r
	316	**/\r
	317	EFI_STATUS\r
	318	NvmeSecuritySendReceive (\r
	319	IN NVME_CONTEXT *Nvme,\r
	320	IN BOOLEAN SendCommand,\r
	321	IN UINT8 SecurityProtocol,\r
	322	IN UINT16 SpSpecific,\r
	323	IN UINTN TransferLength,\r
	324	IN OUT VOID *TransferBuffer\r
	325	);\r
	326	\r
	327	#endif\r