[mirror_edk2.git] / SecurityPkg / Tcg / Opal / OpalPasswordSmm / OpalNvmeMode.h

/** @file\r
  Header file for NVMe function definitions\r
\r
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __OPAL_PASSWORD_NVME_MODE_H__\r
#define __OPAL_PASSWORD_NVME_MODE_H__\r
\r
\r
#include "OpalNvmeReg.h"\r
\r
#define NVME_MAX_SECTORS            0x10000\r
//\r
// QueueId\r
//\r
#define NVME_ADMIN_QUEUE            0x00\r
#define NVME_IO_QUEUE               0x01\r
\r
typedef struct {\r
  UINT8                             Opcode;\r
  UINT8                             FusedOperation;\r
    #define NORMAL_CMD              0x00\r
    #define FUSED_FIRST_CMD         0x01\r
    #define FUSED_SECOND_CMD        0x02\r
  UINT16                            Cid;\r
} NVME_CDW0;\r
\r
typedef struct {\r
  NVME_CDW0                         Cdw0;\r
  UINT8                             Flags;\r
    #define CDW10_VALID             0x01\r
    #define CDW11_VALID             0x02\r
    #define CDW12_VALID             0x04\r
    #define CDW13_VALID             0x08\r
    #define CDW14_VALID             0x10\r
    #define CDW15_VALID             0x20\r
  UINT32                            Nsid;\r
  UINT32                            Cdw10;\r
  UINT32                            Cdw11;\r
  UINT32                            Cdw12;\r
  UINT32                            Cdw13;\r
  UINT32                            Cdw14;\r
  UINT32                            Cdw15;\r
} NVM_EXPRESS_COMMAND;\r
\r
typedef struct {\r
  UINT32                            Cdw0;\r
  UINT32                            Cdw1;\r
  UINT32                            Cdw2;\r
  UINT32                            Cdw3;\r
} NVM_EXPRESS_RESPONSE;\r
\r
typedef struct {\r
  UINT64                            CommandTimeout;\r
  UINT64                            TransferBuffer;\r
  UINT32                            TransferLength;\r
  UINT64                            MetadataBuffer;\r
  UINT32                            MetadataLength;\r
  UINT8                             QueueId;\r
  NVM_EXPRESS_COMMAND               *NvmeCmd;\r
  NVM_EXPRESS_RESPONSE              *NvmeResponse;\r
} NVM_EXPRESS_PASS_THRU_COMMAND_PACKET;\r
\r
\r
#pragma pack(1)\r
\r
// Internal fields\r
typedef enum {\r
  NvmeStatusUnknown,\r
  NvmeStatusInit,\r
  NvmeStatusInuse,\r
  NvmeStatusMax,\r
} NVME_STATUS;\r
\r
typedef struct {\r
  UINT32                            Nbar;\r
  UINT32                            BaseMem;\r
  BOOLEAN                           PollCancellation;\r
  UINT16                            NvmeInitWaitTime;\r
\r
  NVME_STATUS                       State;\r
  UINT8                             BusID;\r
  UINT8                             DeviceID;\r
  UINT8                             FuncID;\r
  UINTN                             PciBase;\r
\r
  UINT32                            Nsid;\r
  UINT64                            Nsuuid;\r
  UINT32                            BlockSize;\r
  EFI_LBA                           LastBlock;\r
\r
  //\r
  // Pointers to 4kB aligned submission & completion queues.\r
  //\r
  NVME_SQ                           *SqBuffer[NVME_MAX_IO_QUEUES];\r
  NVME_CQ                           *CqBuffer[NVME_MAX_IO_QUEUES];\r
  UINT16                            Cid[NVME_MAX_IO_QUEUES];\r
\r
  //\r
  // Submission and completion queue indices.\r
  //\r
  NVME_SQTDBL                       SqTdbl[NVME_MAX_IO_QUEUES];\r
  NVME_CQHDBL                       CqHdbl[NVME_MAX_IO_QUEUES];\r
  UINT8                             Pt[NVME_MAX_IO_QUEUES];\r
\r
  UINTN                             SqeCount[NVME_MAX_IO_QUEUES];\r
\r
  //\r
  // Nvme controller capabilities\r
  //\r
  NVME_CAP                          Cap;\r
\r
  //\r
  // pointer to identify controller Data\r
  //\r
  NVME_ADMIN_CONTROLLER_DATA        *ControllerData;\r
  NVME_ADMIN_NAMESPACE_DATA         *NamespaceData;\r
} NVME_CONTEXT;\r
\r
#pragma pack()\r
\r
/**\r
  Transfer MMIO Data to memory.\r
\r
  @param[in,out] MemBuffer - Destination: Memory address\r
  @param[in] MmioAddr      - Source: MMIO address\r
  @param[in] Size          - Size for read\r
\r
  @retval EFI_SUCCESS - MMIO read sucessfully\r
**/\r
EFI_STATUS\r
NvmeMmioRead (\r
  IN OUT VOID *MemBuffer,\r
  IN     UINTN MmioAddr,\r
  IN     UINTN Size\r
  );\r
\r
/**\r
  Transfer memory Data to MMIO.\r
\r
  @param[in,out] MmioAddr - Destination: MMIO address\r
  @param[in] MemBuffer    - Source: Memory address\r
  @param[in] Size         - Size for write\r
\r
  @retval EFI_SUCCESS - MMIO write sucessfully\r
**/\r
EFI_STATUS\r
NvmeMmioWrite (\r
  IN OUT UINTN MmioAddr,\r
  IN     VOID *MemBuffer,\r
  IN     UINTN Size\r
  );\r
\r
/**\r
  Transfer memory data to MMIO.\r
\r
  @param[in,out] MmioAddr - Destination: MMIO address\r
  @param[in] MemBuffer    - Source: Memory address\r
  @param[in] Size         - Size for write\r
\r
  @retval EFI_SUCCESS - MMIO write sucessfully\r
**/\r
EFI_STATUS\r
OpalPciWrite (\r
  IN OUT UINTN MmioAddr,\r
  IN     VOID *MemBuffer,\r
  IN     UINTN Size\r
  );\r
\r
/**\r
  Transfer MMIO data to memory.\r
\r
  @param[in,out] MemBuffer - Destination: Memory address\r
  @param[in] MmioAddr      - Source: MMIO address\r
  @param[in] Size          - Size for read\r
\r
  @retval EFI_SUCCESS - MMIO read sucessfully\r
**/\r
EFI_STATUS\r
OpalPciRead (\r
  IN OUT VOID *MemBuffer,\r
  IN     UINTN MmioAddr,\r
  IN     UINTN Size\r
  );\r
\r
/**\r
  Allocate transfer-related Data struct which is used at Nvme.\r
\r
  @param[in] ImageHandle         Image handle for this driver image\r
  @param[in] Nvme                The pointer to the NVME_CONTEXT Data structure.\r
\r
  @retval  EFI_OUT_OF_RESOURCE   The allocation is failure.\r
  @retval  EFI_SUCCESS           Successful to allocate memory.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
NvmeAllocateResource (\r
  IN EFI_HANDLE                         ImageHandle,\r
  IN NVME_CONTEXT                       *Nvme\r
  );\r
\r
/**\r
  Free allocated transfer-related Data struct which is used at NVMe.\r
\r
  @param[in] Nvme                The pointer to the NVME_CONTEXT Data structure.\r
\r
**/\r
VOID\r
EFIAPI\r
NvmeFreeResource (\r
  IN NVME_CONTEXT                       *Nvme\r
  );\r
\r
/**\r
  Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r
  both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the nonblocking\r
  I/O functionality is optional.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
  @param[in] NamespaceId            - Is a 32 bit Namespace ID to which the Express HCI command packet will be sent.\r
                                      A Value of 0 denotes the NVM Express controller, a Value of all 0FFh in the namespace\r
                                      ID specifies that the command packet should be sent to all valid namespaces.\r
  @param[in] NamespaceUuid          - Is a 64 bit Namespace UUID to which the Express HCI command packet will be sent.\r
                                      A Value of 0 denotes the NVM Express controller, a Value of all 0FFh in the namespace\r
                                      UUID specifies that the command packet should be sent to all valid namespaces.\r
  @param[in,out] Packet             - A pointer to the NVM Express HCI Command Packet to send to the NVMe namespace specified\r
                                      by NamespaceId.\r
\r
  @retval EFI_SUCCESS               - The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r
                                      to, or from DataBuffer.\r
  @retval EFI_NOT_READY             - The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r
                                      may retry again later.\r
  @retval EFI_DEVICE_ERROR          - A device error occurred while attempting to send the NVM Express Command Packet.\r
  @retval EFI_INVALID_PARAMETER     - Namespace, or the contents of NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r
                                      Express Command Packet was not sent, so no additional status information is available.\r
  @retval EFI_UNSUPPORTED           - The command described by the NVM Express Command Packet is not supported by the host adapter.\r
                                      The NVM Express Command Packet was not sent, so no additional status information is available.\r
  @retval EFI_TIMEOUT               - A timeout occurred while waiting for the NVM Express Command Packet to execute.\r
\r
**/\r
EFI_STATUS\r
NvmePassThru (\r
  IN     NVME_CONTEXT                         *Nvme,\r
  IN     UINT32                               NamespaceId,\r
  IN     UINT64                               NamespaceUuid,\r
  IN OUT NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet\r
  );\r
\r
/**\r
  Waits until all NVME commands completed.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
  @param[in] Qid                    - Queue index\r
\r
  @retval EFI_SUCCESS               - All NVME commands have completed\r
  @retval EFI_TIMEOUT               - Timeout occured\r
  @retval EFI_NOT_READY             - Not all NVME commands have completed\r
  @retval others                    - Error occurred on device side.\r
**/\r
EFI_STATUS\r
NvmeWaitAllComplete (\r
  IN NVME_CONTEXT       *Nvme,\r
  IN UINT8              Qid\r
  );\r
\r
/**\r
  Initialize the Nvm Express controller.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
\r
  @retval EFI_SUCCESS               - The NVM Express Controller is initialized successfully.\r
  @retval Others                    - A device error occurred while initializing the controller.\r
\r
**/\r
EFI_STATUS\r
NvmeControllerInit (\r
  IN NVME_CONTEXT       *Nvme\r
  );\r
\r
/**\r
  Un-initialize the Nvm Express controller.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
\r
  @retval EFI_SUCCESS               - The NVM Express Controller is un-initialized successfully.\r
  @retval Others                    - A device error occurred while un-initializing the controller.\r
\r
**/\r
EFI_STATUS\r
NvmeControllerExit (\r
  IN NVME_CONTEXT       *Nvme\r
  );\r
\r
/**\r
  Check whether there are available command slots.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
  @param[in] Qid                    - Queue index\r
\r
  @retval EFI_SUCCESS               - Available command slot is found\r
  @retval EFI_NOT_READY             - No available command slot is found\r
  @retval EFI_DEVICE_ERROR          - Error occurred on device side.\r
\r
**/\r
EFI_STATUS\r
NvmeHasFreeCmdSlot (\r
  IN NVME_CONTEXT       *Nvme,\r
  IN UINT8              Qid\r
  );\r
\r
/**\r
  Check whether all command slots are clean.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
  @param[in] Qid                    - Queue index\r
\r
  @retval EFI_SUCCESS               - All command slots are clean\r
  @retval EFI_NOT_READY             - Not all command slots are clean\r
  @retval EFI_DEVICE_ERROR          - Error occurred on device side.\r
\r
**/\r
EFI_STATUS\r
NvmeIsAllCmdSlotClean (\r
  IN NVME_CONTEXT       *Nvme,\r
  IN UINT8              Qid\r
  );\r
\r
/**\r
  Read sector Data from the NVMe device.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
  @param[in,out] Buffer             - The Buffer used to store the Data read from the device.\r
  @param[in] Lba                    - The start block number.\r
  @param[in] Blocks                 - Total block number to be read.\r
\r
  @retval EFI_SUCCESS               - Datum are read from the device.\r
  @retval Others                    - Fail to read all the datum.\r
\r
**/\r
EFI_STATUS\r
NvmeReadSectors (\r
  IN NVME_CONTEXT                          *Nvme,\r
  IN OUT UINT64                            Buffer,\r
  IN UINT64                                Lba,\r
  IN UINT32                                Blocks\r
  );\r
\r
/**\r
  Write sector Data to the NVMe device.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
  @param[in] Buffer                 - The Buffer to be written into the device.\r
  @param[in] Lba                    - The start block number.\r
  @param[in] Blocks                 - Total block number to be written.\r
\r
  @retval EFI_SUCCESS               - Datum are written into the Buffer.\r
  @retval Others                    - Fail to write all the datum.\r
\r
**/\r
EFI_STATUS\r
NvmeWriteSectors (\r
  IN NVME_CONTEXT                          *Nvme,\r
  IN UINT64                                Buffer,\r
  IN UINT64                                Lba,\r
  IN UINT32                                Blocks\r
  );\r
\r
/**\r
  Flushes all modified Data to the device.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
\r
  @retval EFI_SUCCESS               - Datum are written into the Buffer.\r
  @retval Others                    - Fail to write all the datum.\r
\r
**/\r
EFI_STATUS\r
NvmeFlush (\r
  IN NVME_CONTEXT                          *Nvme\r
  );\r
\r
/**\r
  Read some blocks from the device.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
  @param[out] Buffer                - The Buffer used to store the Data read from the device.\r
  @param[in] Lba                    - The start block number.\r
  @param[in] Blocks                 - Total block number to be read.\r
\r
  @retval EFI_SUCCESS               - Datum are read from the device.\r
  @retval Others                    - Fail to read all the datum.\r
\r
**/\r
EFI_STATUS\r
NvmeRead (\r
  IN NVME_CONTEXT                  *Nvme,\r
  OUT UINT64                       Buffer,\r
  IN UINT64                        Lba,\r
  IN UINTN                         Blocks\r
  );\r
\r
/**\r
  Write some blocks to the device.\r
\r
  @param[in] Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
  @param[in] Buffer                 - The Buffer to be written into the device.\r
  @param[in] Lba                    - The start block number.\r
  @param[in] Blocks                 - Total block number to be written.\r
\r
  @retval EFI_SUCCESS               - Datum are written into the Buffer.\r
  @retval Others                    - Fail to write all the datum.\r
\r
**/\r
EFI_STATUS\r
NvmeWrite (\r
  IN NVME_CONTEXT                  *Nvme,\r
  IN UINT64                        Buffer,\r
  IN UINT64                        Lba,\r
  IN UINTN                         Blocks\r
  );\r
\r
/**\r
  Security send and receive commands.\r
\r
  @param[in]     Nvme                   - The pointer to the NVME_CONTEXT Data structure.\r
  @param[in]     SendCommand            - The flag to indicate the command type, TRUE for Send command and FALSE for receive command\r
  @param[in]     SecurityProtocol       - Security Protocol\r
  @param[in]     SpSpecific             - Security Protocol Specific\r
  @param[in]     TransferLength         - Transfer Length of Buffer (in bytes) - always a multiple of 512\r
  @param[in,out] TransferBuffer         - Address of Data to transfer\r
\r
  @return EFI_SUCCESS               - Successfully create io submission queue.\r
  @return others                    - Fail to send/receive commands.\r
\r
**/\r
EFI_STATUS\r
NvmeSecuritySendReceive (\r
  IN NVME_CONTEXT                          *Nvme,\r
  IN BOOLEAN                               SendCommand,\r
  IN UINT8                                 SecurityProtocol,\r
  IN UINT16                                SpSpecific,\r
  IN UINTN                                 TransferLength,\r
  IN OUT VOID                              *TransferBuffer\r
  );\r
\r
#endif\r
Commit	Line	Data
cb274a27 ED	1	/** @file\r
	2	Header file for NVMe function definitions\r
	3	\r
	4	Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#ifndef __OPAL_PASSWORD_NVME_MODE_H__\r
	16	#define __OPAL_PASSWORD_NVME_MODE_H__\r
	17	\r
	18	\r
	19	#include "OpalNvmeReg.h"\r
	20	\r
	21	#define NVME_MAX_SECTORS 0x10000\r
	22	//\r
	23	// QueueId\r
	24	//\r
	25	#define NVME_ADMIN_QUEUE 0x00\r
	26	#define NVME_IO_QUEUE 0x01\r
	27	\r
	28	typedef struct {\r
	29	UINT8 Opcode;\r
	30	UINT8 FusedOperation;\r
	31	#define NORMAL_CMD 0x00\r
	32	#define FUSED_FIRST_CMD 0x01\r
	33	#define FUSED_SECOND_CMD 0x02\r
	34	UINT16 Cid;\r
	35	} NVME_CDW0;\r
	36	\r
	37	typedef struct {\r
	38	NVME_CDW0 Cdw0;\r
	39	UINT8 Flags;\r
	40	#define CDW10_VALID 0x01\r
	41	#define CDW11_VALID 0x02\r
	42	#define CDW12_VALID 0x04\r
	43	#define CDW13_VALID 0x08\r
	44	#define CDW14_VALID 0x10\r
	45	#define CDW15_VALID 0x20\r
	46	UINT32 Nsid;\r
	47	UINT32 Cdw10;\r
	48	UINT32 Cdw11;\r
	49	UINT32 Cdw12;\r
	50	UINT32 Cdw13;\r
	51	UINT32 Cdw14;\r
	52	UINT32 Cdw15;\r
	53	} NVM_EXPRESS_COMMAND;\r
	54	\r
	55	typedef struct {\r
	56	UINT32 Cdw0;\r
	57	UINT32 Cdw1;\r
	58	UINT32 Cdw2;\r
	59	UINT32 Cdw3;\r
	60	} NVM_EXPRESS_RESPONSE;\r
	61	\r
	62	typedef struct {\r
	63	UINT64 CommandTimeout;\r
	64	UINT64 TransferBuffer;\r
65	UINT32 TransferLength;\r
66	UINT64 MetadataBuffer;\r
67	UINT32 MetadataLength;\r
68	UINT8 QueueId;\r
69	NVM_EXPRESS_COMMAND *NvmeCmd;\r
70	NVM_EXPRESS_RESPONSE *NvmeResponse;\r
71	} NVM_EXPRESS_PASS_THRU_COMMAND_PACKET;\r
72	\r
73	\r
74	#pragma pack(1)\r
75	\r
76	// Internal fields\r
77	typedef enum {\r
78	NvmeStatusUnknown,\r
79	NvmeStatusInit,\r
80	NvmeStatusInuse,\r
81	NvmeStatusMax,\r
82	} NVME_STATUS;\r
83	\r
84	typedef struct {\r
85	UINT32 Nbar;\r
86	UINT32 BaseMem;\r
87	BOOLEAN PollCancellation;\r
88	UINT16 NvmeInitWaitTime;\r
89	\r
90	NVME_STATUS State;\r
91	UINT8 BusID;\r
92	UINT8 DeviceID;\r
93	UINT8 FuncID;\r
94	UINTN PciBase;\r
95	\r
96	UINT32 Nsid;\r
97	UINT64 Nsuuid;\r
98	UINT32 BlockSize;\r
99	EFI_LBA LastBlock;\r
100	\r
101	//\r
102	// Pointers to 4kB aligned submission & completion queues.\r
103	//\r
104	NVME_SQ *SqBuffer[NVME_MAX_IO_QUEUES];\r
105	NVME_CQ *CqBuffer[NVME_MAX_IO_QUEUES];\r
106	UINT16 Cid[NVME_MAX_IO_QUEUES];\r
107	\r
108	//\r
109	// Submission and completion queue indices.\r
110	//\r
111	NVME_SQTDBL SqTdbl[NVME_MAX_IO_QUEUES];\r
112	NVME_CQHDBL CqHdbl[NVME_MAX_IO_QUEUES];\r
113	UINT8 Pt[NVME_MAX_IO_QUEUES];\r
114	\r
115	UINTN SqeCount[NVME_MAX_IO_QUEUES];\r
116	\r
117	//\r
118	// Nvme controller capabilities\r
119	//\r
120	NVME_CAP Cap;\r
121	\r
122	//\r
123	// pointer to identify controller Data\r
124	//\r
125	NVME_ADMIN_CONTROLLER_DATA *ControllerData;\r
126	NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r
127	} NVME_CONTEXT;\r
128	\r
129	#pragma pack()\r
130	\r
131	/**\r
132	Transfer MMIO Data to memory.\r
133	\r
134	@param[in,out] MemBuffer - Destination: Memory address\r
135	@param[in] MmioAddr - Source: MMIO address\r
136	@param[in] Size - Size for read\r
137	\r
138	@retval EFI_SUCCESS - MMIO read sucessfully\r
139	**/\r
140	EFI_STATUS\r
141	NvmeMmioRead (\r
142	IN OUT VOID *MemBuffer,\r
143	IN UINTN MmioAddr,\r
144	IN UINTN Size\r
145	);\r
146	\r
147	/**\r
148	Transfer memory Data to MMIO.\r
149	\r
150	@param[in,out] MmioAddr - Destination: MMIO address\r
151	@param[in] MemBuffer - Source: Memory address\r
152	@param[in] Size - Size for write\r
153	\r
154	@retval EFI_SUCCESS - MMIO write sucessfully\r
155	**/\r
156	EFI_STATUS\r
157	NvmeMmioWrite (\r
158	IN OUT UINTN MmioAddr,\r
159	IN VOID *MemBuffer,\r
160	IN UINTN Size\r
161	);\r
162	\r
163	/**\r
164	Transfer memory data to MMIO.\r
165	\r
166	@param[in,out] MmioAddr - Destination: MMIO address\r
167	@param[in] MemBuffer - Source: Memory address\r
168	@param[in] Size - Size for write\r
169	\r
170	@retval EFI_SUCCESS - MMIO write sucessfully\r
171	**/\r
172	EFI_STATUS\r
173	OpalPciWrite (\r
174	IN OUT UINTN MmioAddr,\r
175	IN VOID *MemBuffer,\r
176	IN UINTN Size\r
177	);\r
178	\r
179	/**\r
180	Transfer MMIO data to memory.\r
181	\r
182	@param[in,out] MemBuffer - Destination: Memory address\r
183	@param[in] MmioAddr - Source: MMIO address\r
184	@param[in] Size - Size for read\r
185	\r
186	@retval EFI_SUCCESS - MMIO read sucessfully\r
187	**/\r
188	EFI_STATUS\r
189	OpalPciRead (\r
190	IN OUT VOID *MemBuffer,\r
191	IN UINTN MmioAddr,\r
192	IN UINTN Size\r
193	);\r
194	\r
195	/**\r
196	Allocate transfer-related Data struct which is used at Nvme.\r
197	\r
198	@param[in] ImageHandle Image handle for this driver image\r
199	@param[in] Nvme The pointer to the NVME_CONTEXT Data structure.\r
200	\r
201	@retval EFI_OUT_OF_RESOURCE The allocation is failure.\r
202	@retval EFI_SUCCESS Successful to allocate memory.\r
203	\r
204	**/\r
205	EFI_STATUS\r
206	EFIAPI\r
207	NvmeAllocateResource (\r
208	IN EFI_HANDLE ImageHandle,\r
209	IN NVME_CONTEXT *Nvme\r
210	);\r
211	\r
212	/**\r
213	Free allocated transfer-related Data struct which is used at NVMe.\r
214	\r
215	@param[in] Nvme The pointer to the NVME_CONTEXT Data structure.\r
216	\r
217	**/\r
218	VOID\r
219	EFIAPI\r
220	NvmeFreeResource (\r
221	IN NVME_CONTEXT *Nvme\r
222	);\r
223	\r
224	/**\r
225	Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r
226	both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the nonblocking\r
227	I/O functionality is optional.\r
228	\r
229	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
230	@param[in] NamespaceId - Is a 32 bit Namespace ID to which the Express HCI command packet will be sent.\r
231	A Value of 0 denotes the NVM Express controller, a Value of all 0FFh in the namespace\r
232	ID specifies that the command packet should be sent to all valid namespaces.\r
233	@param[in] NamespaceUuid - Is a 64 bit Namespace UUID to which the Express HCI command packet will be sent.\r
234	A Value of 0 denotes the NVM Express controller, a Value of all 0FFh in the namespace\r
235	UUID specifies that the command packet should be sent to all valid namespaces.\r
236	@param[in,out] Packet - A pointer to the NVM Express HCI Command Packet to send to the NVMe namespace specified\r
237	by NamespaceId.\r
238	\r
239	@retval EFI_SUCCESS - The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r
240	to, or from DataBuffer.\r
241	@retval EFI_NOT_READY - The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r
242	may retry again later.\r
243	@retval EFI_DEVICE_ERROR - A device error occurred while attempting to send the NVM Express Command Packet.\r
244	@retval EFI_INVALID_PARAMETER - Namespace, or the contents of NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r
245	Express Command Packet was not sent, so no additional status information is available.\r
246	@retval EFI_UNSUPPORTED - The command described by the NVM Express Command Packet is not supported by the host adapter.\r
247	The NVM Express Command Packet was not sent, so no additional status information is available.\r
248	@retval EFI_TIMEOUT - A timeout occurred while waiting for the NVM Express Command Packet to execute.\r
249	\r
250	**/\r
251	EFI_STATUS\r
252	NvmePassThru (\r
253	IN NVME_CONTEXT *Nvme,\r
254	IN UINT32 NamespaceId,\r
255	IN UINT64 NamespaceUuid,\r
256	IN OUT NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet\r
257	);\r
258	\r
259	/**\r
260	Waits until all NVME commands completed.\r
261	\r
262	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
263	@param[in] Qid - Queue index\r
264	\r
265	@retval EFI_SUCCESS - All NVME commands have completed\r
266	@retval EFI_TIMEOUT - Timeout occured\r
267	@retval EFI_NOT_READY - Not all NVME commands have completed\r
268	@retval others - Error occurred on device side.\r
269	**/\r
270	EFI_STATUS\r
271	NvmeWaitAllComplete (\r
272	IN NVME_CONTEXT *Nvme,\r
273	IN UINT8 Qid\r
274	);\r
275	\r
276	/**\r
277	Initialize the Nvm Express controller.\r
278	\r
279	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
280	\r
281	@retval EFI_SUCCESS - The NVM Express Controller is initialized successfully.\r
282	@retval Others - A device error occurred while initializing the controller.\r
283	\r
284	**/\r
285	EFI_STATUS\r
286	NvmeControllerInit (\r
287	IN NVME_CONTEXT *Nvme\r
288	);\r
289	\r
290	/**\r
291	Un-initialize the Nvm Express controller.\r
292	\r
293	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
294	\r
295	@retval EFI_SUCCESS - The NVM Express Controller is un-initialized successfully.\r
296	@retval Others - A device error occurred while un-initializing the controller.\r
297	\r
298	**/\r
299	EFI_STATUS\r
300	NvmeControllerExit (\r
301	IN NVME_CONTEXT *Nvme\r
302	);\r
303	\r
304	/**\r
305	Check whether there are available command slots.\r
306	\r
307	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
308	@param[in] Qid - Queue index\r
309	\r
310	@retval EFI_SUCCESS - Available command slot is found\r
311	@retval EFI_NOT_READY - No available command slot is found\r
312	@retval EFI_DEVICE_ERROR - Error occurred on device side.\r
313	\r
314	**/\r
315	EFI_STATUS\r
316	NvmeHasFreeCmdSlot (\r
317	IN NVME_CONTEXT *Nvme,\r
318	IN UINT8 Qid\r
319	);\r
320	\r
321	/**\r
322	Check whether all command slots are clean.\r
323	\r
324	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
325	@param[in] Qid - Queue index\r
326	\r
327	@retval EFI_SUCCESS - All command slots are clean\r
328	@retval EFI_NOT_READY - Not all command slots are clean\r
329	@retval EFI_DEVICE_ERROR - Error occurred on device side.\r
330	\r
331	**/\r
332	EFI_STATUS\r
333	NvmeIsAllCmdSlotClean (\r
334	IN NVME_CONTEXT *Nvme,\r
335	IN UINT8 Qid\r
336	);\r
337	\r
338	/**\r
339	Read sector Data from the NVMe device.\r
340	\r
341	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
342	@param[in,out] Buffer - The Buffer used to store the Data read from the device.\r
343	@param[in] Lba - The start block number.\r
344	@param[in] Blocks - Total block number to be read.\r
345	\r
346	@retval EFI_SUCCESS - Datum are read from the device.\r
347	@retval Others - Fail to read all the datum.\r
348	\r
349	**/\r
350	EFI_STATUS\r
351	NvmeReadSectors (\r
352	IN NVME_CONTEXT *Nvme,\r
353	IN OUT UINT64 Buffer,\r
354	IN UINT64 Lba,\r
355	IN UINT32 Blocks\r
356	);\r
357	\r
358	/**\r
359	Write sector Data to the NVMe device.\r
360	\r
361	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
362	@param[in] Buffer - The Buffer to be written into the device.\r
363	@param[in] Lba - The start block number.\r
364	@param[in] Blocks - Total block number to be written.\r
365	\r
366	@retval EFI_SUCCESS - Datum are written into the Buffer.\r
367	@retval Others - Fail to write all the datum.\r
368	\r
369	**/\r
370	EFI_STATUS\r
371	NvmeWriteSectors (\r
372	IN NVME_CONTEXT *Nvme,\r
373	IN UINT64 Buffer,\r
374	IN UINT64 Lba,\r
375	IN UINT32 Blocks\r
376	);\r
377	\r
378	/**\r
379	Flushes all modified Data to the device.\r
380	\r
381	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
382	\r
383	@retval EFI_SUCCESS - Datum are written into the Buffer.\r
384	@retval Others - Fail to write all the datum.\r
385	\r
386	**/\r
387	EFI_STATUS\r
388	NvmeFlush (\r
389	IN NVME_CONTEXT *Nvme\r
390	);\r
391	\r
392	/**\r
393	Read some blocks from the device.\r
394	\r
395	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
396	@param[out] Buffer - The Buffer used to store the Data read from the device.\r
397	@param[in] Lba - The start block number.\r
398	@param[in] Blocks - Total block number to be read.\r
399	\r
400	@retval EFI_SUCCESS - Datum are read from the device.\r
401	@retval Others - Fail to read all the datum.\r
402	\r
403	**/\r
404	EFI_STATUS\r
405	NvmeRead (\r
406	IN NVME_CONTEXT *Nvme,\r
407	OUT UINT64 Buffer,\r
408	IN UINT64 Lba,\r
409	IN UINTN Blocks\r
410	);\r
411	\r
412	/**\r
413	Write some blocks to the device.\r
414	\r
415	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
416	@param[in] Buffer - The Buffer to be written into the device.\r
417	@param[in] Lba - The start block number.\r
418	@param[in] Blocks - Total block number to be written.\r
419	\r
420	@retval EFI_SUCCESS - Datum are written into the Buffer.\r
421	@retval Others - Fail to write all the datum.\r
422	\r
423	**/\r
424	EFI_STATUS\r
425	NvmeWrite (\r
426	IN NVME_CONTEXT *Nvme,\r
427	IN UINT64 Buffer,\r
428	IN UINT64 Lba,\r
429	IN UINTN Blocks\r
430	);\r
431	\r
432	/**\r
433	Security send and receive commands.\r
434	\r
435	@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
436	@param[in] SendCommand - The flag to indicate the command type, TRUE for Send command and FALSE for receive command\r
437	@param[in] SecurityProtocol - Security Protocol\r
438	@param[in] SpSpecific - Security Protocol Specific\r
439	@param[in] TransferLength - Transfer Length of Buffer (in bytes) - always a multiple of 512\r
440	@param[in,out] TransferBuffer - Address of Data to transfer\r
441	\r
442	@return EFI_SUCCESS - Successfully create io submission queue.\r
443	@return others - Fail to send/receive commands.\r
444	\r
445	**/\r
446	EFI_STATUS\r
447	NvmeSecuritySendReceive (\r
448	IN NVME_CONTEXT *Nvme,\r
449	IN BOOLEAN SendCommand,\r
450	IN UINT8 SecurityProtocol,\r
451	IN UINT16 SpSpecific,\r
452	IN UINTN TransferLength,\r
453	IN OUT VOID *TransferBuffer\r
454	);\r
455	\r
456	#endif\r