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18b144ea 1/** @file\r
2 X64 register defintions needed by debug transfer protocol.\r
3\r
4 Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php.\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#ifndef _ARCH_REGISTERS_H_\r
16#define _ARCH_REGISTERS_H_\r
17\r
18///\r
19/// FXSAVE_STATE (promoted operation)\r
20/// FP / MMX / XMM registers (see fxrstor instruction definition)\r
21///\r
22typedef struct {\r
23 UINT16 Fcw;\r
24 UINT16 Fsw;\r
25 UINT16 Ftw;\r
26 UINT16 Opcode;\r
27 UINT64 Rip;\r
28 UINT64 DataOffset;\r
29 UINT32 Mxcsr;\r
30 UINT32 Mxcsr_Mask;\r
31 UINT8 St0Mm0[10];\r
32 UINT8 Reserved2[6];\r
33 UINT8 St1Mm1[10];\r
34 UINT8 Reserved3[6];\r
35 UINT8 St2Mm2[10];\r
36 UINT8 Reserved4[6];\r
37 UINT8 St3Mm3[10];\r
38 UINT8 Reserved5[6];\r
39 UINT8 St4Mm4[10];\r
40 UINT8 Reserved6[6];\r
41 UINT8 St5Mm5[10];\r
42 UINT8 Reserved7[6];\r
43 UINT8 St6Mm6[10];\r
44 UINT8 Reserved8[6];\r
45 UINT8 St7Mm7[10];\r
46 UINT8 Reserved9[6];\r
47 UINT8 Xmm0[16];\r
48 UINT8 Xmm1[16];\r
49 UINT8 Xmm2[16];\r
50 UINT8 Xmm3[16];\r
51 UINT8 Xmm4[16];\r
52 UINT8 Xmm5[16];\r
53 UINT8 Xmm6[16];\r
54 UINT8 Xmm7[16];\r
55 UINT8 Xmm8[16];\r
56 UINT8 Xmm9[16];\r
57 UINT8 Xmm10[16];\r
58 UINT8 Xmm11[16];\r
59 UINT8 Xmm12[16];\r
60 UINT8 Xmm13[16];\r
61 UINT8 Xmm14[16];\r
62 UINT8 Xmm15[16];\r
63 UINT8 Reserved11[6 * 16];\r
64} DEBUG_DATA_X64_FX_SAVE_STATE;\r
65\r
66///\r
67/// x64 processor context definition\r
68///\r
69typedef struct {\r
70 DEBUG_DATA_X64_FX_SAVE_STATE FxSaveState;\r
71 UINT64 Dr0;\r
72 UINT64 Dr1;\r
73 UINT64 Dr2;\r
74 UINT64 Dr3;\r
75 UINT64 Dr6;\r
76 UINT64 Dr7;\r
77 UINT64 Eflags;\r
78 UINT64 Ldtr;\r
79 UINT64 Tr;\r
80 UINT64 Gdtr[2];\r
81 UINT64 Idtr[2];\r
82 UINT64 Eip;\r
83 UINT64 Gs;\r
84 UINT64 Fs;\r
85 UINT64 Es;\r
86 UINT64 Ds;\r
87 UINT64 Cs;\r
88 UINT64 Ss;\r
89 UINT64 Cr0;\r
90 UINT64 Cr1; /* Reserved */\r
91 UINT64 Cr2;\r
92 UINT64 Cr3;\r
93 UINT64 Cr4;\r
94 UINT64 Rdi;\r
95 UINT64 Rsi;\r
96 UINT64 Rbp;\r
97 UINT64 Rsp;\r
98 UINT64 Rdx;\r
99 UINT64 Rcx;\r
100 UINT64 Rbx;\r
101 UINT64 Rax;\r
102 UINT64 Cr8;\r
103 UINT64 R8;\r
104 UINT64 R9;\r
105 UINT64 R10;\r
106 UINT64 R11;\r
107 UINT64 R12;\r
108 UINT64 R13;\r
109 UINT64 R14;\r
110 UINT64 R15;\r
111} DEBUG_DATA_X64_SYSTEM_CONTEXT;\r
112\r
113\r
114///\r
115/// x64 GROUP register\r
116///\r
117typedef struct {\r
118 UINT16 Cs;\r
119 UINT16 Ds;\r
120 UINT16 Es;\r
121 UINT16 Fs;\r
122 UINT16 Gs;\r
123 UINT16 Ss;\r
124 UINT32 Eflags;\r
125 UINT64 Rbp;\r
126 UINT64 Eip;\r
127 UINT64 Rsp;\r
128 UINT64 Eax;\r
129 UINT64 Rbx;\r
130 UINT64 Rcx;\r
131 UINT64 Rdx;\r
132 UINT64 Rsi;\r
133 UINT64 Rdi;\r
134 UINT64 R8;\r
135 UINT64 R9;\r
136 UINT64 R10;\r
137 UINT64 R11;\r
138 UINT64 R12;\r
139 UINT64 R13;\r
140 UINT64 R14;\r
141 UINT64 R15;\r
142 UINT64 Dr0;\r
143 UINT64 Dr1;\r
144 UINT64 Dr2;\r
145 UINT64 Dr3;\r
146 UINT64 Dr6;\r
147 UINT64 Dr7;\r
148 UINT64 Cr0;\r
149 UINT64 Cr2;\r
150 UINT64 Cr3;\r
151 UINT64 Cr4;\r
152 UINT64 Cr8;\r
153 UINT8 Xmm0[16];\r
154 UINT8 Xmm1[16];\r
155 UINT8 Xmm2[16];\r
156 UINT8 Xmm3[16];\r
157 UINT8 Xmm4[16];\r
158 UINT8 Xmm5[16];\r
159 UINT8 Xmm6[16];\r
160 UINT8 Xmm7[16];\r
161 UINT8 Xmm8[16];\r
162 UINT8 Xmm9[16];\r
163 UINT8 Xmm10[16];\r
164 UINT8 Xmm11[16];\r
165 UINT8 Xmm12[16];\r
166 UINT8 Xmm13[16];\r
167 UINT8 Xmm14[16];\r
168 UINT8 Xmm15[16];\r
169} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_X64;\r
170\r
171///\r
172/// x64 Segment Limit GROUP register\r
173///\r
174typedef struct {\r
175 UINT64 CsLim;\r
176 UINT64 SsLim;\r
177 UINT64 GsLim;\r
178 UINT64 FsLim;\r
179 UINT64 EsLim;\r
180 UINT64 DsLim;\r
181 UINT64 LdtLim;\r
182 UINT64 TssLim;\r
183} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_X64;\r
184\r
185///\r
186/// x64 Segment Base GROUP register\r
187///\r
188typedef struct {\r
189 UINT64 CsBas;\r
190 UINT64 SsBas;\r
191 UINT64 GsBas;\r
192 UINT64 FsBas;\r
193 UINT64 EsBas;\r
194 UINT64 DsBas;\r
195 UINT64 LdtBas;\r
196 UINT64 TssBas;\r
197} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_X64;\r
198\r
199///\r
200/// x64 Segment Base/Limit GROUP register\r
201///\r
202typedef struct {\r
203 UINT64 IdtBas;\r
204 UINT64 IdtLim;\r
205 UINT64 GdtBas;\r
206 UINT64 GdtLim;\r
207 UINT64 CsLim;\r
208 UINT64 SsLim;\r
209 UINT64 GsLim;\r
210 UINT64 FsLim;\r
211 UINT64 EsLim;\r
212 UINT64 DsLim;\r
213 UINT64 LdtLim;\r
214 UINT64 TssLim;\r
215 UINT64 CsBas;\r
216 UINT64 SsBas;\r
217 UINT64 GsBas;\r
218 UINT64 FsBas;\r
219 UINT64 EsBas;\r
220 UINT64 DsBas;\r
221 UINT64 LdtBas;\r
222 UINT64 TssBas;\r
223} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BAS_LIM;\r
224\r
225///\r
226/// x64 register GROUP register\r
227///\r
228typedef struct {\r
229 UINT32 Eflags;\r
230 UINT64 Rbp;\r
231 UINT64 Eip;\r
232 UINT64 Rsp;\r
233} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_GP2;\r
234\r
235///\r
236/// x64 general register GROUP register\r
237///\r
238typedef struct {\r
239 UINT64 Eax;\r
240 UINT64 Rbx;\r
241 UINT64 Rcx;\r
242 UINT64 Rdx;\r
243 UINT64 Rsi;\r
244 UINT64 Rdi;\r
245 UINT64 R8;\r
246 UINT64 R9;\r
247 UINT64 R10;\r
248 UINT64 R11;\r
249 UINT64 R12;\r
250 UINT64 R13;\r
251 UINT64 R14;\r
252 UINT64 R15;\r
253} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_GP;\r
254\r
255///\r
256/// x64 Segment GROUP register\r
257///\r
258typedef struct {\r
259 UINT16 Cs;\r
260 UINT16 Ds;\r
261 UINT16 Es;\r
262 UINT16 Fs;\r
263 UINT16 Gs;\r
264 UINT16 Ss;\r
265} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT;\r
266\r
267///\r
268/// x64 Debug Register GROUP register\r
269///\r
270typedef struct {\r
271 UINT64 Dr0;\r
272 UINT64 Dr1;\r
273 UINT64 Dr2;\r
274 UINT64 Dr3;\r
275 UINT64 Dr6;\r
276 UINT64 Dr7;\r
277} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_DR;\r
278\r
279///\r
280/// x64 Control Register GROUP register\r
281///\r
282typedef struct {\r
283 UINT64 Cr0;\r
284 UINT64 Cr2;\r
285 UINT64 Cr3;\r
286 UINT64 Cr4;\r
287 UINT64 Cr8;\r
288} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_CR;\r
289\r
290///\r
291/// x64 XMM Register GROUP register\r
292///\r
293typedef struct {\r
294 UINT8 Xmm0[16];\r
295 UINT8 Xmm1[16];\r
296 UINT8 Xmm2[16];\r
297 UINT8 Xmm3[16];\r
298 UINT8 Xmm4[16];\r
299 UINT8 Xmm5[16];\r
300 UINT8 Xmm6[16];\r
301 UINT8 Xmm7[16];\r
302 UINT8 Xmm8[16];\r
303 UINT8 Xmm9[16];\r
304 UINT8 Xmm10[16];\r
305 UINT8 Xmm11[16];\r
306 UINT8 Xmm12[16];\r
307 UINT8 Xmm13[16];\r
308 UINT8 Xmm14[16];\r
309 UINT8 Xmm15[16];\r
310} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_XMM;\r
311\r
312///\r
313/// x64 Segment Base GROUP register\r
314///\r
315typedef struct {\r
316 UINT16 Ldtr;\r
317 UINT16 Tr;\r
318 UINT64 Csas;\r
319 UINT64 Ssas;\r
320 UINT64 Gsas;\r
321 UINT64 Fsas;\r
322 UINT64 Esas;\r
323 UINT64 Dsas;\r
324 UINT64 Ldtas;\r
325 UINT64 Tssas;\r
326} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BASES_X64;\r
327\r
328\r
329#endif\r
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