| 2aa62f2b |
1 | /* $NetBSD: fpu.h,v 1.1 2003/04/26 18:39:40 fvdl Exp $ */\r |
| 2 | \r |
| 3 | #ifndef _AMD64_FPU_H_\r |
| 4 | #define _AMD64_FPU_H_\r |
| 5 | \r |
| 6 | /*\r |
| 7 | * NetBSD/amd64 only uses the extended save/restore format used\r |
| 8 | * by fxsave/fsrestore, to always deal with the SSE registers,\r |
| 9 | * which are part of the ABI to pass floating point values.\r |
| 10 | * Must be stored in memory on a 16-byte boundary.\r |
| 11 | */\r |
| 12 | \r |
| 13 | struct fxsave64 {\r |
| 14 | u_int16_t fx_fcw;\r |
| 15 | u_int16_t fx_fsw;\r |
| 16 | u_int8_t fx_ftw;\r |
| 17 | u_int8_t fx_unused1;\r |
| 18 | u_int16_t fx_fop;\r |
| 19 | u_int64_t fx_rip;\r |
| 20 | u_int64_t fx_rdp;\r |
| 21 | u_int32_t fx_mxcsr;\r |
| 22 | u_int32_t fx_mxcsr_mask;\r |
| 23 | u_int64_t fx_st[8][2]; /* 8 normal FP regs */\r |
| 24 | u_int64_t fx_xmm[16][2]; /* 16 SSE2 registers */\r |
| 25 | u_int8_t fx_unused3[96];\r |
| 26 | } __attribute__((packed));\r |
| 27 | \r |
| 28 | struct savefpu {\r |
| 29 | struct fxsave64 fp_fxsave; /* see above */\r |
| 30 | u_int16_t fp_ex_sw; /* saved status from last exception */\r |
| 31 | u_int16_t fp_ex_tw; /* saved tag from last exception */\r |
| 32 | };\r |
| 33 | \r |
| 34 | #ifdef _KERNEL\r |
| 35 | \r |
| 36 | /*\r |
| 37 | * This one only used for backward compat coredumping.\r |
| 38 | */\r |
| 39 | struct oldfsave {\r |
| 40 | u_int16_t fs_control;\r |
| 41 | u_int16_t fs_unused0;\r |
| 42 | u_int16_t fs_status;\r |
| 43 | u_int16_t fs_unused1;\r |
| 44 | u_int16_t fs_tag;\r |
| 45 | u_int16_t fs_unused2;\r |
| 46 | u_int32_t fs_ipoff;\r |
| 47 | u_int16_t fs_ipsel;\r |
| 48 | u_int16_t fs_op;\r |
| 49 | u_int32_t fs_opoff;\r |
| 50 | u_int16_t fs_opsel;\r |
| 51 | } __attribute__ ((packed));\r |
| 52 | \r |
| 53 | #endif\r |
| 54 | \r |
| 55 | \r |
| 56 | /*\r |
| 57 | * The i387 defaults to Intel extended precision mode and round to nearest,\r |
| 58 | * with all exceptions masked.\r |
| 59 | */\r |
| 60 | #define __INITIAL_NPXCW__ 0x037f\r |
| 61 | #define __INITIAL_MXCSR__ 0x1f80\r |
| 62 | #define __INITIAL_MXCSR_MASK__ 0xffbf\r |
| 63 | \r |
| 64 | /* NetBSD uses IEEE double precision. */\r |
| 65 | #define __NetBSD_NPXCW__ 0x127f\r |
| 66 | /* Linux just uses the default control word. */\r |
| 67 | #define __Linux_NPXCW__ 0x037f\r |
| 68 | \r |
| 69 | /*\r |
| 70 | * The standard control word from finit is 0x37F, giving:\r |
| 71 | * round to nearest\r |
| 72 | * 64-bit precision\r |
| 73 | * all exceptions masked.\r |
| 74 | *\r |
| 75 | * Now we want:\r |
| 76 | * affine mode (if we decide to support 287's)\r |
| 77 | * round to nearest\r |
| 78 | * 53-bit precision\r |
| 79 | * all exceptions masked.\r |
| 80 | *\r |
| 81 | * 64-bit precision often gives bad results with high level languages\r |
| 82 | * because it makes the results of calculations depend on whether\r |
| 83 | * intermediate values are stored in memory or in FPU registers.\r |
| 84 | */\r |
| 85 | \r |
| 86 | #ifdef _KERNEL\r |
| 87 | /*\r |
| 88 | * XXX\r |
| 89 | */\r |
| 90 | struct trapframe;\r |
| 91 | struct cpu_info;\r |
| 92 | \r |
| 93 | void fpuinit(struct cpu_info *);\r |
| 94 | void fpudrop(void);\r |
| 95 | void fpusave(struct lwp *);\r |
| 96 | void fpudiscard(struct lwp *);\r |
| 97 | void fputrap(struct trapframe *);\r |
| 98 | void fpusave_lwp(struct lwp *, int);\r |
| 99 | void fpusave_cpu(struct cpu_info *, int);\r |
| 100 | \r |
| 101 | #endif\r |
| 102 | \r |
| 103 | #endif /* _AMD64_FPU_H_ */\r |
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