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[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuGdt.c
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a47463f2 1/** @file\r
2 C based implemention of IA32 interrupt handling only\r
3 requiring a minimal assembly interrupt entry point.\r
4\r
01a1c0fc
HT
5 Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
6 This program and the accompanying materials\r
a47463f2 7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "CpuDxe.h"\r
17\r
18\r
19//\r
20// Local structure definitions\r
21//\r
22\r
23#pragma pack (1)\r
24\r
25//\r
26// Global Descriptor Entry structures\r
27//\r
28\r
29typedef\r
30struct _GDT_ENTRY {\r
31 UINT16 limit15_0;\r
32 UINT16 base15_0;\r
33 UINT8 base23_16;\r
34 UINT8 type;\r
35 UINT8 limit19_16_and_flags;\r
36 UINT8 base31_24;\r
37} GDT_ENTRY;\r
38\r
39typedef\r
40struct _GDT_ENTRIES {\r
41 GDT_ENTRY Null;\r
42 GDT_ENTRY Linear;\r
43 GDT_ENTRY LinearCode;\r
44 GDT_ENTRY SysData;\r
45 GDT_ENTRY SysCode;\r
46 GDT_ENTRY LinearCode64;\r
47 GDT_ENTRY Spare4;\r
48 GDT_ENTRY Spare5;\r
49} GDT_ENTRIES;\r
50\r
51#define NULL_SEL OFFSET_OF (GDT_ENTRIES, Null)\r
52#define LINEAR_SEL OFFSET_OF (GDT_ENTRIES, Linear)\r
53#define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode)\r
54#define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData)\r
55#define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode)\r
56#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)\r
57#define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4)\r
58#define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5)\r
59\r
60#if defined (MDE_CPU_IA32)\r
61#define CPU_CODE_SEL LINEAR_CODE_SEL\r
62#define CPU_DATA_SEL LINEAR_SEL\r
63#elif defined (MDE_CPU_X64)\r
64#define CPU_CODE_SEL LINEAR_CODE64_SEL\r
65#define CPU_DATA_SEL LINEAR_SEL\r
66#else\r
67#error CPU type not supported for CPU GDT initialization!\r
68#endif\r
69\r
70//\r
71// Global descriptor table (GDT) Template\r
72//\r
73STATIC GDT_ENTRIES GdtTemplate = {\r
74 //\r
75 // NULL_SEL\r
76 //\r
77 {\r
78 0x0, // limit 15:0\r
79 0x0, // base 15:0\r
80 0x0, // base 23:16\r
81 0x0, // type\r
82 0x0, // limit 19:16, flags\r
83 0x0, // base 31:24\r
84 },\r
85 //\r
86 // LINEAR_SEL\r
87 //\r
88 {\r
89 0x0FFFF, // limit 0xFFFFF\r
90 0x0, // base 0\r
91 0x0,\r
92 0x092, // present, ring 0, data, expand-up, writable\r
93 0x0CF, // page-granular, 32-bit\r
94 0x0,\r
95 },\r
96 //\r
97 // LINEAR_CODE_SEL\r
98 //\r
99 {\r
100 0x0FFFF, // limit 0xFFFFF\r
101 0x0, // base 0\r
102 0x0,\r
103 0x09A, // present, ring 0, data, expand-up, writable\r
104 0x0CF, // page-granular, 32-bit\r
105 0x0,\r
106 },\r
107 //\r
108 // SYS_DATA_SEL\r
109 //\r
110 {\r
111 0x0FFFF, // limit 0xFFFFF\r
112 0x0, // base 0\r
113 0x0,\r
114 0x092, // present, ring 0, data, expand-up, writable\r
115 0x0CF, // page-granular, 32-bit\r
116 0x0,\r
117 },\r
118 //\r
119 // SYS_CODE_SEL\r
120 //\r
121 {\r
122 0x0FFFF, // limit 0xFFFFF\r
123 0x0, // base 0\r
124 0x0,\r
125 0x09A, // present, ring 0, data, expand-up, writable\r
126 0x0CF, // page-granular, 32-bit\r
127 0x0,\r
128 },\r
129 //\r
130 // LINEAR_CODE64_SEL\r
131 //\r
132 {\r
133 0x0FFFF, // limit 0xFFFFF\r
134 0x0, // base 0\r
135 0x0,\r
136 0x09B, // present, ring 0, code, expand-up, writable\r
137 0x0AF, // LimitHigh (CS.L=1, CS.D=0)\r
138 0x0, // base (high)\r
139 },\r
140 //\r
141 // SPARE4_SEL\r
142 //\r
143 {\r
144 0x0, // limit 0\r
145 0x0, // base 0\r
146 0x0,\r
147 0x0, // present, ring 0, data, expand-up, writable\r
148 0x0, // page-granular, 32-bit\r
149 0x0,\r
150 },\r
151 //\r
152 // SPARE5_SEL\r
153 //\r
154 {\r
155 0x0, // limit 0\r
156 0x0, // base 0\r
157 0x0,\r
158 0x0, // present, ring 0, data, expand-up, writable\r
159 0x0, // page-granular, 32-bit\r
160 0x0,\r
161 },\r
162};\r
163\r
164/**\r
165 Initialize Global Descriptor Table\r
166\r
167**/\r
168VOID\r
169InitGlobalDescriptorTable (\r
170 )\r
171{\r
172 GDT_ENTRIES *gdt;\r
173 IA32_DESCRIPTOR gdtPtr;\r
174\r
175 //\r
176 // Allocate Runtime Data for the GDT\r
177 //\r
178 gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);\r
179 ASSERT (gdt != NULL);\r
180 gdt = ALIGN_POINTER (gdt, 8);\r
181\r
182 //\r
183 // Initialize all GDT entries\r
184 //\r
185 CopyMem (gdt, &GdtTemplate, sizeof (GdtTemplate));\r
186\r
187 //\r
188 // Write GDT register\r
189 //\r
190 gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;\r
191 gdtPtr.Limit = sizeof (GdtTemplate) - 1;\r
192 AsmWriteGdtr (&gdtPtr);\r
193\r
194 //\r
195 // Update selector (segment) registers base on new GDT\r
196 //\r
197 SetCodeSelector ((UINT16)CPU_CODE_SEL);\r
198 SetDataSelectors ((UINT16)CPU_DATA_SEL);\r
199}\r
200\r