UefiCpuPkg/CpuDxe: Rename variables to follow EDKII coding standard

[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuGdt.c

/** @file\r
  C based implementation of IA32 interrupt handling only\r
  requiring a minimal assembly interrupt entry point.\r
\r
  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "CpuDxe.h"\r
#include "CpuGdt.h"\r
\r
//\r
// Global descriptor table (GDT) Template\r
//\r
STATIC GDT_ENTRIES mGdtTemplate = {\r
  //\r
  // NULL_SEL\r
  //\r
  {\r
    0x0,            // limit 15:0\r
    0x0,            // base 15:0\r
    0x0,            // base 23:16\r
    0x0,            // type\r
    0x0,            // limit 19:16, flags\r
    0x0,            // base 31:24\r
  },\r
  //\r
  // LINEAR_SEL\r
  //\r
  {\r
    0x0FFFF,        // limit 15:0\r
    0x0,            // base 15:0\r
    0x0,            // base 23:16\r
    0x092,          // present, ring 0, data, read/write\r
    0x0CF,          // page-granular, 32-bit\r
    0x0,\r
  },\r
  //\r
  // LINEAR_CODE_SEL\r
  //\r
  {\r
    0x0FFFF,        // limit 15:0\r
    0x0,            // base 15:0\r
    0x0,            // base 23:16\r
    0x09F,          // present, ring 0, code, execute/read, conforming, accessed\r
    0x0CF,          // page-granular, 32-bit\r
    0x0,\r
  },\r
  //\r
  // SYS_DATA_SEL\r
  //\r
  {\r
    0x0FFFF,        // limit 15:0\r
    0x0,            // base 15:0\r
    0x0,            // base 23:16\r
    0x093,          // present, ring 0, data, read/write, accessed\r
    0x0CF,          // page-granular, 32-bit\r
    0x0,\r
  },\r
  //\r
  // SYS_CODE_SEL\r
  //\r
  {\r
    0x0FFFF,        // limit 15:0\r
    0x0,            // base 15:0\r
    0x0,            // base 23:16\r
    0x09A,          // present, ring 0, code, execute/read\r
    0x0CF,          // page-granular, 32-bit\r
    0x0,\r
  },\r
  //\r
  // SYS_CODE16_SEL\r
  //\r
  {\r
    0x0FFFF,        // limit 15:0\r
    0x0,            // base 15:0\r
    0x0,            // base 23:16\r
    0x09A,          // present, ring 0, code, execute/read\r
    0x08F,          // page-granular, 16-bit\r
    0x0,            // base 31:24\r
  },\r
  //\r
  // LINEAR_DATA64_SEL\r
  //\r
  {\r
    0x0FFFF,        // limit 15:0\r
    0x0,            // base 15:0\r
    0x0,            // base 23:16\r
    0x092,          // present, ring 0, data, read/write\r
    0x0CF,          // page-granular, 32-bit\r
    0x0,\r
  },\r
  //\r
  // LINEAR_CODE64_SEL\r
  //\r
  {\r
    0x0FFFF,        // limit 15:0\r
    0x0,            // base 15:0\r
    0x0,            // base 23:16\r
    0x09A,          // present, ring 0, code, execute/read\r
    0x0AF,          // page-granular, 64-bit code\r
    0x0,            // base (high)\r
  },\r
  //\r
  // SPARE5_SEL\r
  //\r
  {\r
    0x0,            // limit 15:0\r
    0x0,            // base 15:0\r
    0x0,            // base 23:16\r
    0x0,            // type\r
    0x0,            // limit 19:16, flags\r
    0x0,            // base 31:24\r
  },\r
};\r
\r
/**\r
  Initialize Global Descriptor Table.\r
\r
**/\r
VOID\r
InitGlobalDescriptorTable (\r
  VOID\r
  )\r
{\r
  GDT_ENTRIES           *Gdt;\r
  IA32_DESCRIPTOR       Gdtr;\r
\r
  //\r
  // Allocate Runtime Data for the GDT\r
  //\r
  Gdt = AllocateRuntimePool (sizeof (mGdtTemplate) + 8);\r
  ASSERT (Gdt != NULL);\r
  Gdt = ALIGN_POINTER (Gdt, 8);\r
\r
  //\r
  // Initialize all GDT entries\r
  //\r
  CopyMem (Gdt, &mGdtTemplate, sizeof (mGdtTemplate));\r
\r
  //\r
  // Write GDT register\r
  //\r
  Gdtr.Base  = (UINT32) (UINTN) Gdt;\r
  Gdtr.Limit = (UINT16) (sizeof (mGdtTemplate) - 1);\r
  AsmWriteGdtr (&Gdtr);\r
\r
  //\r
  // Update selector (segment) registers base on new GDT\r
  //\r
  SetCodeSelector ((UINT16)CPU_CODE_SEL);\r
  SetDataSelectors ((UINT16)CPU_DATA_SEL);\r
}\r