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1 | /** @file\r |
2 | Definitions for CPU S3 data.\r | |
3 | \r | |
fcd92f16 | 4 | Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r |
1c27f926 MK |
5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef _ACPI_CPU_DATA_H_\r | |
16 | #define _ACPI_CPU_DATA_H_\r | |
17 | \r | |
18 | //\r | |
19 | // Register types in register table\r | |
20 | //\r | |
af381fda | 21 | typedef enum {\r |
1c27f926 MK |
22 | Msr,\r |
23 | ControlRegister,\r | |
24 | MemoryMapped,\r | |
25 | CacheControl\r | |
26 | } REGISTER_TYPE;\r | |
27 | \r | |
28 | //\r | |
29 | // Element of register table entry\r | |
30 | //\r | |
31 | typedef struct {\r | |
30b7a50b JF |
32 | REGISTER_TYPE RegisterType; // offset 0 - 3\r |
33 | UINT32 Index; // offset 4 - 7\r | |
34 | UINT8 ValidBitStart; // offset 8\r | |
35 | UINT8 ValidBitLength; // offset 9\r | |
36 | UINT16 Reserved; // offset 10 - 11\r | |
37 | UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped\r | |
38 | UINT64 Value; // offset 16-23\r | |
1c27f926 MK |
39 | } CPU_REGISTER_TABLE_ENTRY;\r |
40 | \r | |
41 | //\r | |
42 | // Register table definition, including current table length,\r | |
43 | // allocated size of this table, and pointer to the list of table entries.\r | |
44 | //\r | |
45 | typedef struct {\r | |
af381fda MK |
46 | //\r |
47 | // The number of valid entries in the RegisterTableEntry buffer\r | |
48 | //\r | |
49 | UINT32 TableLength;\r | |
50 | UINT32 NumberBeforeReset;\r | |
51 | //\r | |
52 | // The size, in bytes, of the RegisterTableEntry buffer\r | |
53 | //\r | |
54 | UINT32 AllocatedSize;\r | |
55 | //\r | |
56 | // The initial APIC ID of the CPU this register table applies to\r | |
57 | //\r | |
58 | UINT32 InitialApicId;\r | |
59 | //\r | |
fcd92f16 | 60 | // Physical address of CPU_REGISTER_TABLE_ENTRY structures.\r |
af381fda | 61 | //\r |
9cc45009 | 62 | EFI_PHYSICAL_ADDRESS RegisterTableEntry;\r |
1c27f926 MK |
63 | } CPU_REGISTER_TABLE;\r |
64 | \r | |
af381fda | 65 | //\r |
fcd92f16 | 66 | // Data structure that is required for ACPI S3 resume. The PCD\r |
af381fda MK |
67 | // PcdCpuS3DataAddress must be set to the physical address where this structure\r |
68 | // is allocated\r | |
69 | //\r | |
1c27f926 | 70 | typedef struct {\r |
af381fda MK |
71 | //\r |
72 | // Physical address of 4KB buffer allocated below 1MB from memory of type\r | |
73 | // EfiReservedMemoryType. The buffer is not required to be initialized, but\r | |
74 | // it is recommended that the buffer be zero-filled. This buffer is used to\r | |
75 | // wake APs during an ACPI S3 resume.\r | |
76 | //\r | |
1c27f926 | 77 | EFI_PHYSICAL_ADDRESS StartupVector;\r |
af381fda | 78 | //\r |
fcd92f16 | 79 | // Physical address of structure of type IA32_DESCRIPTOR. The\r |
af381fda | 80 | // IA32_DESCRIPTOR structure provides the base address and length of a GDT\r |
fcd92f16 | 81 | // The GDT must be filled in with the GDT contents that are\r |
af381fda MK |
82 | // used during an ACPI S3 resume. This is typically the contents of the GDT\r |
83 | // used by the boot processor when the platform is booted.\r | |
84 | //\r | |
1c27f926 | 85 | EFI_PHYSICAL_ADDRESS GdtrProfile;\r |
af381fda | 86 | //\r |
fcd92f16 | 87 | // Physical address of structure of type IA32_DESCRIPTOR. The\r |
af381fda | 88 | // IA32_DESCRIPTOR structure provides the base address and length of an IDT.\r |
fcd92f16 | 89 | // The IDT must be filled in with the IDT contents that are\r |
af381fda MK |
90 | // used during an ACPI S3 resume. This is typically the contents of the IDT\r |
91 | // used by the boot processor when the platform is booted.\r | |
92 | //\r | |
1c27f926 | 93 | EFI_PHYSICAL_ADDRESS IdtrProfile;\r |
af381fda MK |
94 | //\r |
95 | // Physical address of a buffer that is used as stacks during ACPI S3 resume.\r | |
96 | // The total size of this buffer, in bytes, is NumberOfCpus * StackSize. This\r | |
fcd92f16 | 97 | // structure must be allocated from memory of type EfiACPIMemoryNVS.\r |
af381fda | 98 | //\r |
1c27f926 | 99 | EFI_PHYSICAL_ADDRESS StackAddress;\r |
af381fda MK |
100 | //\r |
101 | // The size, in bytes, of the stack provided to each CPU during ACPI S3 resume.\r | |
102 | //\r | |
1c27f926 | 103 | UINT32 StackSize;\r |
af381fda MK |
104 | //\r |
105 | // The number of CPUs. If a platform does not support hot plug CPUs, then\r | |
106 | // this is the number of CPUs detected when the platform is booted, regardless\r | |
107 | // of being enabled or disabled. If a platform does support hot plug CPUs,\r | |
108 | // then this is the maximum number of CPUs that the platform supports.\r | |
109 | //\r | |
1c27f926 | 110 | UINT32 NumberOfCpus;\r |
af381fda MK |
111 | //\r |
112 | // Physical address of structure of type MTRR_SETTINGS that contains a copy\r | |
113 | // of the MTRR settings that are compatible with the MTRR settings used by\r | |
114 | // the boot processor when the platform was booted. These MTRR settings are\r | |
fcd92f16 | 115 | // used during an ACPI S3 resume.\r |
af381fda | 116 | //\r |
1c27f926 MK |
117 | EFI_PHYSICAL_ADDRESS MtrrTable;\r |
118 | //\r | |
af381fda | 119 | // Physical address of an array of CPU_REGISTER_TABLE structures, with\r |
fcd92f16 | 120 | // NumberOfCpus entries. If a register table is not required, then the\r |
af381fda MK |
121 | // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.\r |
122 | // If TableLength is > 0, then elements of RegisterTableEntry are used to\r | |
123 | // initialize the CPU that matches InitialApicId, during an ACPI S3 resume,\r | |
124 | // before SMBASE relocation is performed.\r | |
1c27f926 MK |
125 | //\r |
126 | EFI_PHYSICAL_ADDRESS PreSmmInitRegisterTable;\r | |
127 | //\r | |
af381fda | 128 | // Physical address of an array of CPU_REGISTER_TABLE structures, with\r |
fcd92f16 | 129 | // NumberOfCpus entries. If a register table is not required, then the\r |
af381fda MK |
130 | // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.\r |
131 | // If TableLength is > 0, then elements of RegisterTableEntry are used to\r | |
132 | // initialize the CPU that matches InitialApicId, during an ACPI S3 resume,\r | |
133 | // after SMBASE relocation is performed.\r | |
1c27f926 MK |
134 | //\r |
135 | EFI_PHYSICAL_ADDRESS RegisterTable;\r | |
af381fda MK |
136 | //\r |
137 | // Physical address of a buffer that contains the machine check handler that\r | |
fcd92f16 | 138 | // is used during an ACPI S3 Resume. In order for this machine check\r |
af381fda MK |
139 | // handler to be active on an AP during an ACPI S3 resume, the machine check\r |
140 | // vector in the IDT provided by IdtrProfile must be initialized to transfer\r | |
141 | // control to this physical address.\r | |
142 | //\r | |
1c27f926 | 143 | EFI_PHYSICAL_ADDRESS ApMachineCheckHandlerBase;\r |
af381fda MK |
144 | //\r |
145 | // The size, in bytes, of the machine check handler that is used during an\r | |
146 | // ACPI S3 Resume. If this field is 0, then a machine check handler is not\r | |
147 | // provided.\r | |
148 | //\r | |
1c27f926 MK |
149 | UINT32 ApMachineCheckHandlerSize;\r |
150 | } ACPI_CPU_DATA;\r | |
151 | \r | |
152 | #endif\r |