[mirror_edk2.git] / UefiCpuPkg / Include / Library / SmmCpuFeaturesLib.h

/** @file\r
Library that provides CPU specific functions to support the PiSmmCpuDxeSmm module.\r
\r
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __SMM_FEATURES_LIB_H__\r
#define __SMM_FEATURES_LIB_H__\r
\r
#include <Protocol/MpService.h>\r
#include <Protocol/SmmCpu.h>\r
#include <Register/Intel/SmramSaveStateMap.h>\r
#include <CpuHotPlugData.h>\r
\r
///\r
/// Enumeration of SMM registers that are accessed using the library functions\r
/// SmmCpuFeaturesIsSmmRegisterSupported (), SmmCpuFeaturesGetSmmRegister (),\r
/// and SmmCpuFeaturesSetSmmRegister ().\r
///\r
typedef enum {\r
  ///\r
  /// Read-write register to provides access to MSR_SMM_FEATURE_CONTROL if the\r
  /// CPU supports this MSR.\r
  ///\r
  SmmRegFeatureControl,\r
  ///\r
  /// Read-only register that returns a non-zero value if the CPU is able to\r
  /// respond to SMIs.\r
  ///\r
  SmmRegSmmEnable,\r
  ///\r
  /// Read-only register that returns a non-zero value if the CPU is able to\r
  /// respond to SMIs, but is busy with other actions that are causing a delay\r
  /// in responding to an SMI.  This register abstracts access to MSR_SMM_DELAYED\r
  /// if the CPU supports this MSR.\r
  ///\r
  SmmRegSmmDelayed,\r
  ///\r
  /// Read-only register that returns a non-zero value if the CPU is able to\r
  /// respond to SMIs, but is busy with other actions that are blocking its\r
  /// ability to respond to an SMI.  This register abstracts access to\r
  /// MSR_SMM_BLOCKED if the CPU supports this MSR.\r
  ///\r
  SmmRegSmmBlocked\r
} SMM_REG_NAME;\r
\r
/**\r
  Called during the very first SMI into System Management Mode to initialize\r
  CPU features, including SMBASE, for the currently executing CPU.  Since this\r
  is the first SMI, the SMRAM Save State Map is at the default address of\r
  SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET.  The currently executing\r
  CPU is specified by CpuIndex and CpuIndex can be used to access information\r
  about the currently executing CPU in the ProcessorInfo array and the\r
  HotPlugCpuData data structure.\r
\r
  @param[in] CpuIndex        The index of the CPU to initialize.  The value\r
                             must be between 0 and the NumberOfCpus field in\r
                             the System Management System Table (SMST).\r
  @param[in] IsMonarch       TRUE if the CpuIndex is the index of the CPU that\r
                             was elected as monarch during System Management\r
                             Mode initialization.\r
                             FALSE if the CpuIndex is not the index of the CPU\r
                             that was elected as monarch during System\r
                             Management Mode initialization.\r
  @param[in] ProcessorInfo   Pointer to an array of EFI_PROCESSOR_INFORMATION\r
                             structures.  ProcessorInfo[CpuIndex] contains the\r
                             information for the currently executing CPU.\r
  @param[in] CpuHotPlugData  Pointer to the CPU_HOT_PLUG_DATA structure that\r
                             contains the ApidId and SmBase arrays.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesInitializeProcessor (\r
  IN UINTN                      CpuIndex,\r
  IN BOOLEAN                    IsMonarch,\r
  IN EFI_PROCESSOR_INFORMATION  *ProcessorInfo,\r
  IN CPU_HOT_PLUG_DATA          *CpuHotPlugData\r
  );\r
\r
/**\r
  This function updates the SMRAM save state on the currently executing CPU\r
  to resume execution at a specific address after an RSM instruction.  This\r
  function must evaluate the SMRAM save state to determine the execution mode\r
  the RSM instruction resumes and update the resume execution address with\r
  either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart\r
  flag in the SMRAM save state must always be cleared.  This function returns\r
  the value of the instruction pointer from the SMRAM save state that was\r
  replaced.  If this function returns 0, then the SMRAM save state was not\r
  modified.\r
\r
  This function is called during the very first SMI on each CPU after\r
  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
  to signal that the SMBASE of each CPU has been updated before the default\r
  SMBASE address is used for the first SMI to the next CPU.\r
\r
  @param[in] CpuIndex                 The index of the CPU to hook.  The value\r
                                      must be between 0 and the NumberOfCpus\r
                                      field in the System Management System Table\r
                                      (SMST).\r
  @param[in] CpuState                 Pointer to SMRAM Save State Map for the\r
                                      currently executing CPU.\r
  @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to\r
                                      32-bit execution mode from 64-bit SMM.\r
  @param[in] NewInstructionPointer    Instruction pointer to use if resuming to\r
                                      same execution mode as SMM.\r
\r
  @retval 0    This function did modify the SMRAM save state.\r
  @retval > 0  The original instruction pointer value from the SMRAM save state\r
               before it was replaced.\r
**/\r
UINT64\r
EFIAPI\r
SmmCpuFeaturesHookReturnFromSmm (\r
  IN UINTN                 CpuIndex,\r
  IN SMRAM_SAVE_STATE_MAP  *CpuState,\r
  IN UINT64                NewInstructionPointer32,\r
  IN UINT64                NewInstructionPointer\r
  );\r
\r
/**\r
  Hook point in normal execution mode that allows the one CPU that was elected\r
  as monarch during System Management Mode initialization to perform additional\r
  initialization actions immediately after all of the CPUs have processed their\r
  first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
  into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesSmmRelocationComplete (\r
  VOID\r
  );\r
\r
/**\r
  Return the size, in bytes, of a custom SMI Handler in bytes.  If 0 is\r
  returned, then a custom SMI handler is not provided by this library,\r
  and the default SMI handler must be used.\r
\r
  @retval 0    Use the default SMI handler.\r
  @retval > 0  Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
               The caller is required to allocate enough SMRAM for each CPU to\r
               support the size of the custom SMI handler.\r
**/\r
UINTN\r
EFIAPI\r
SmmCpuFeaturesGetSmiHandlerSize (\r
  VOID\r
  );\r
\r
/**\r
  Install a custom SMI handler for the CPU specified by CpuIndex.  This function\r
  is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
  than zero and is called by the CPU that was elected as monarch during System\r
  Management Mode initialization.\r
\r
    //\r
    // Append Shadow Stack after normal stack\r
    //\r
    // |= SmiStack\r
    // +--------------------------------------------------+---------------------------------------------------------------+\r
    // | Known Good Stack | Guard Page |    SMM Stack     | Known Good Shadow Stack | Guard Page |    SMM Shadow Stack    |\r
    // +--------------------------------------------------+---------------------------------------------------------------+\r
    // |                               |PcdCpuSmmStackSize|                                      |PcdCpuSmmShadowStackSize|\r
    // |<-------------------- StackSize ----------------->|<------------------------- ShadowStackSize ------------------->|\r
    // |                                                                                                                  |\r
    // |<-------------------------------------------- Processor N ------------------------------------------------------->|\r
    // | low address (bottom)                                                                          high address (top) |\r
    //\r
\r
  @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.\r
                        The value must be between 0 and the NumberOfCpus field\r
                        in the System Management System Table (SMST).\r
  @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.\r
  @param[in] SmiStack   The bottom of stack to use when an SMI is processed by the\r
                        the CPU specified by CpuIndex.\r
  @param[in] StackSize  The size, in bytes, if the stack used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
                        StackSize should be PcdCpuSmmStackSize, with 2 more pages\r
                        if PcdCpuSmmStackGuard is true.\r
                        If ShadowStack is enabled, the shadow stack is allocated\r
                        after the normal Stack. The size is PcdCpuSmmShadowStackSize.\r
                        with 2 more pages if PcdCpuSmmStackGuard is true.\r
  @param[in] GdtBase    The base address of the GDT to use when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] IdtBase    The base address of the IDT to use when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] Cr3        The base address of the page tables to use when an SMI\r
                        is processed by the CPU specified by CpuIndex.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesInstallSmiHandler (\r
  IN UINTN   CpuIndex,\r
  IN UINT32  SmBase,\r
  IN VOID    *SmiStack,\r
  IN UINTN   StackSize,\r
  IN UINTN   GdtBase,\r
  IN UINTN   GdtSize,\r
  IN UINTN   IdtBase,\r
  IN UINTN   IdtSize,\r
  IN UINT32  Cr3\r
  );\r
\r
/**\r
  Determines if MTRR registers must be configured to set SMRAM cache-ability\r
  when executing in System Management Mode.\r
\r
  @retval TRUE   MTRR registers must be configured to set SMRAM cache-ability.\r
  @retval FALSE  MTRR registers do not need to be configured to set SMRAM\r
                 cache-ability.\r
**/\r
BOOLEAN\r
EFIAPI\r
SmmCpuFeaturesNeedConfigureMtrrs (\r
  VOID\r
  );\r
\r
/**\r
  Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
  returns TRUE.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesDisableSmrr (\r
  VOID\r
  );\r
\r
/**\r
  Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
  returns TRUE.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesReenableSmrr (\r
  VOID\r
  );\r
\r
/**\r
  Processor specific hook point each time a CPU enters System Management Mode.\r
\r
  @param[in] CpuIndex  The index of the CPU that has entered SMM.  The value\r
                       must be between 0 and the NumberOfCpus field in the\r
                       System Management System Table (SMST).\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesRendezvousEntry (\r
  IN UINTN  CpuIndex\r
  );\r
\r
/**\r
  Processor specific hook point each time a CPU exits System Management Mode.\r
\r
  @param[in] CpuIndex  The index of the CPU that is exiting SMM.  The value must\r
                       be between 0 and the NumberOfCpus field in the System\r
                       Management System Table (SMST).\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesRendezvousExit (\r
  IN UINTN  CpuIndex\r
  );\r
\r
/**\r
  Check to see if an SMM register is supported by a specified CPU.\r
\r
  @param[in] CpuIndex  The index of the CPU to check for SMM register support.\r
                       The value must be between 0 and the NumberOfCpus field\r
                       in the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to check for support.\r
\r
  @retval TRUE   The SMM register specified by RegName is supported by the CPU\r
                 specified by CpuIndex.\r
  @retval FALSE  The SMM register specified by RegName is not supported by the\r
                 CPU specified by CpuIndex.\r
**/\r
BOOLEAN\r
EFIAPI\r
SmmCpuFeaturesIsSmmRegisterSupported (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName\r
  );\r
\r
/**\r
  Returns the current value of the SMM register for the specified CPU.\r
  If the SMM register is not supported, then 0 is returned.\r
\r
  @param[in] CpuIndex  The index of the CPU to read the SMM register.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to read.\r
\r
  @return  The value of the SMM register specified by RegName from the CPU\r
           specified by CpuIndex.\r
**/\r
UINT64\r
EFIAPI\r
SmmCpuFeaturesGetSmmRegister (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName\r
  );\r
\r
/**\r
  Sets the value of an SMM register on a specified CPU.\r
  If the SMM register is not supported, then no action is performed.\r
\r
  @param[in] CpuIndex  The index of the CPU to write the SMM register.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to write.\r
                       registers are read-only.\r
  @param[in] Value     The value to write to the SMM register.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesSetSmmRegister (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName,\r
  IN UINT64        Value\r
  );\r
\r
/**\r
  Read an SMM Save State register on the target processor.  If this function\r
  returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
  SMM Save Sate register.\r
\r
  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The\r
                        value must be between 0 and the NumberOfCpus field in\r
                        the System Management System Table (SMST).\r
  @param[in]  Register  The SMM Save State register to read.\r
  @param[in]  Width     The number of bytes to read from the CPU save state.\r
  @param[out] Buffer    Upon return, this holds the CPU register value read\r
                        from the save state.\r
\r
  @retval EFI_SUCCESS           The register was read from Save State.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED       This function does not support reading Register.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmCpuFeaturesReadSaveStateRegister (\r
  IN  UINTN                        CpuIndex,\r
  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN  UINTN                        Width,\r
  OUT VOID                         *Buffer\r
  );\r
\r
/**\r
  Writes an SMM Save State register on the target processor.  If this function\r
  returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
  SMM Save Sate register.\r
\r
  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] Register  The SMM Save State register to write.\r
  @param[in] Width     The number of bytes to write to the CPU save state.\r
  @param[in] Buffer    Upon entry, this holds the new CPU register value.\r
\r
  @retval EFI_SUCCESS           The register was written to Save State.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED       This function does not support writing Register.\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmCpuFeaturesWriteSaveStateRegister (\r
  IN UINTN                        CpuIndex,\r
  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN UINTN                        Width,\r
  IN CONST VOID                   *Buffer\r
  );\r
\r
/**\r
  This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
  notification is completely processed.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesCompleteSmmReadyToLock (\r
  VOID\r
  );\r
\r
/**\r
  This API provides a method for a CPU to allocate a specific region for storing page tables.\r
\r
  This API can be called more once to allocate memory for page tables.\r
\r
  Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL\r
  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is\r
  returned.\r
\r
  This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
\r
  @param  Pages                 The number of 4 KB pages to allocate.\r
\r
  @return A pointer to the allocated buffer for page tables.\r
  @retval NULL      Fail to allocate a specific region for storing page tables,\r
                    Or there is no preference on where the page tables are allocated in SMRAM.\r
\r
**/\r
VOID *\r
EFIAPI\r
SmmCpuFeaturesAllocatePageTableMemory (\r
  IN UINTN           Pages\r
  );\r
\r
#endif\r
Commit	Line	Data
a9764e68 MK	1	/** @file\r
	2	Library that provides CPU specific functions to support the PiSmmCpuDxeSmm module.\r
	3	\r
3eb69b08	4	Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
0acd8697	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
a9764e68 MK	6	\r
	7	**/\r
	8	\r
	9	#ifndef __SMM_FEATURES_LIB_H__\r
	10	#define __SMM_FEATURES_LIB_H__\r
	11	\r
	12	#include <Protocol/MpService.h>\r
	13	#include <Protocol/SmmCpu.h>\r
01acb06c	14	#include <Register/Intel/SmramSaveStateMap.h>\r
a9764e68 MK	15	#include <CpuHotPlugData.h>\r
	16	\r
	17	///\r
	18	/// Enumeration of SMM registers that are accessed using the library functions\r
	19	/// SmmCpuFeaturesIsSmmRegisterSupported (), SmmCpuFeaturesGetSmmRegister (),\r
	20	/// and SmmCpuFeaturesSetSmmRegister ().\r
	21	///\r
	22	typedef enum {\r
	23	///\r
	24	/// Read-write register to provides access to MSR_SMM_FEATURE_CONTROL if the\r
	25	/// CPU supports this MSR.\r
	26	///\r
	27	SmmRegFeatureControl,\r
	28	///\r
	29	/// Read-only register that returns a non-zero value if the CPU is able to\r
	30	/// respond to SMIs.\r
	31	///\r
	32	SmmRegSmmEnable,\r
	33	///\r
	34	/// Read-only register that returns a non-zero value if the CPU is able to\r
	35	/// respond to SMIs, but is busy with other actions that are causing a delay\r
	36	/// in responding to an SMI. This register abstracts access to MSR_SMM_DELAYED\r
	37	/// if the CPU supports this MSR.\r
	38	///\r
	39	SmmRegSmmDelayed,\r
	40	///\r
	41	/// Read-only register that returns a non-zero value if the CPU is able to\r
	42	/// respond to SMIs, but is busy with other actions that are blocking its\r
	43	/// ability to respond to an SMI. This register abstracts access to\r
	44	/// MSR_SMM_BLOCKED if the CPU supports this MSR.\r
	45	///\r
	46	SmmRegSmmBlocked\r
	47	} SMM_REG_NAME;\r
	48	\r
	49	/**\r
	50	Called during the very first SMI into System Management Mode to initialize\r
	51	CPU features, including SMBASE, for the currently executing CPU. Since this\r
	52	is the first SMI, the SMRAM Save State Map is at the default address of\r
	53	SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r
	54	CPU is specified by CpuIndex and CpuIndex can be used to access information\r
	55	about the currently executing CPU in the ProcessorInfo array and the\r
	56	HotPlugCpuData data structure.\r
	57	\r
	58	@param[in] CpuIndex The index of the CPU to initialize. The value\r
	59	must be between 0 and the NumberOfCpus field in\r
	60	the System Management System Table (SMST).\r
	61	@param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r
	62	was elected as monarch during System Management\r
	63	Mode initialization.\r
	64	FALSE if the CpuIndex is not the index of the CPU\r
	65	that was elected as monarch during System\r
	66	Management Mode initialization.\r
	67	@param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r
	68	structures. ProcessorInfo[CpuIndex] contains the\r
	69	information for the currently executing CPU.\r
	70	@param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r
	71	contains the ApidId and SmBase arrays.\r
	72	**/\r
	73	VOID\r
	74	EFIAPI\r
	75	SmmCpuFeaturesInitializeProcessor (\r
	76	IN UINTN CpuIndex,\r
	77	IN BOOLEAN IsMonarch,\r
	78	IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r
79	IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r
80	);\r
81	\r
82	/**\r
83	This function updates the SMRAM save state on the currently executing CPU\r
84	to resume execution at a specific address after an RSM instruction. This\r
85	function must evaluate the SMRAM save state to determine the execution mode\r
86	the RSM instruction resumes and update the resume execution address with\r
87	either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r
88	flag in the SMRAM save state must always be cleared. This function returns\r
89	the value of the instruction pointer from the SMRAM save state that was\r
90	replaced. If this function returns 0, then the SMRAM save state was not\r
91	modified.\r
92	\r
93	This function is called during the very first SMI on each CPU after\r
94	SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
95	to signal that the SMBASE of each CPU has been updated before the default\r
96	SMBASE address is used for the first SMI to the next CPU.\r
97	\r
98	@param[in] CpuIndex The index of the CPU to hook. The value\r
99	must be between 0 and the NumberOfCpus\r
100	field in the System Management System Table\r
101	(SMST).\r
102	@param[in] CpuState Pointer to SMRAM Save State Map for the\r
103	currently executing CPU.\r
104	@param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
105	32-bit execution mode from 64-bit SMM.\r
106	@param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
107	same execution mode as SMM.\r
108	\r
109	@retval 0 This function did modify the SMRAM save state.\r
110	@retval > 0 The original instruction pointer value from the SMRAM save state\r
111	before it was replaced.\r
112	**/\r
113	UINT64\r
114	EFIAPI\r
115	SmmCpuFeaturesHookReturnFromSmm (\r
116	IN UINTN CpuIndex,\r
117	IN SMRAM_SAVE_STATE_MAP *CpuState,\r
118	IN UINT64 NewInstructionPointer32,\r
119	IN UINT64 NewInstructionPointer\r
120	);\r
121	\r
122	/**\r
123	Hook point in normal execution mode that allows the one CPU that was elected\r
124	as monarch during System Management Mode initialization to perform additional\r
125	initialization actions immediately after all of the CPUs have processed their\r
126	first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
127	into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
128	**/\r
129	VOID\r
130	EFIAPI\r
131	SmmCpuFeaturesSmmRelocationComplete (\r
132	VOID\r
133	);\r
134	\r
135	/**\r
136	Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is\r
137	returned, then a custom SMI handler is not provided by this library,\r
138	and the default SMI handler must be used.\r
139	\r
140	@retval 0 Use the default SMI handler.\r
141	@retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
142	The caller is required to allocate enough SMRAM for each CPU to\r
143	support the size of the custom SMI handler.\r
144	**/\r
145	UINTN\r
146	EFIAPI\r
147	SmmCpuFeaturesGetSmiHandlerSize (\r
148	VOID\r
149	);\r
150	\r
151	/**\r
152	Install a custom SMI handler for the CPU specified by CpuIndex. This function\r
153	is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
154	than zero and is called by the CPU that was elected as monarch during System\r
155	Management Mode initialization.\r
156	\r
3eb69b08 JY	157	//\r
	158	// Append Shadow Stack after normal stack\r
	159	//\r
	160	// \|= SmiStack\r
	161	// +--------------------------------------------------+---------------------------------------------------------------+\r
	162	// \| Known Good Stack \| Guard Page \| SMM Stack \| Known Good Shadow Stack \| Guard Page \| SMM Shadow Stack \|\r
	163	// +--------------------------------------------------+---------------------------------------------------------------+\r
	164	// \| \|PcdCpuSmmStackSize\| \|PcdCpuSmmShadowStackSize\|\r
	165	// \|<-------------------- StackSize ----------------->\|<------------------------- ShadowStackSize ------------------->\|\r
	166	// \| \|\r
	167	// \|<-------------------------------------------- Processor N ------------------------------------------------------->\|\r
	168	// \| low address (bottom) high address (top) \|\r
	169	//\r
	170	\r
a9764e68 MK	171	@param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
	172	The value must be between 0 and the NumberOfCpus field\r
	173	in the System Management System Table (SMST).\r
	174	@param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
3eb69b08	175	@param[in] SmiStack The bottom of stack to use when an SMI is processed by the\r
a9764e68 MK	176	the CPU specified by CpuIndex.\r
	177	@param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
	178	processed by the CPU specified by CpuIndex.\r
3eb69b08 JY	179	StackSize should be PcdCpuSmmStackSize, with 2 more pages\r
	180	if PcdCpuSmmStackGuard is true.\r
	181	If ShadowStack is enabled, the shadow stack is allocated\r
	182	after the normal Stack. The size is PcdCpuSmmShadowStackSize.\r
	183	with 2 more pages if PcdCpuSmmStackGuard is true.\r
a9764e68 MK	184	@param[in] GdtBase The base address of the GDT to use when an SMI is\r
	185	processed by the CPU specified by CpuIndex.\r
	186	@param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
	187	processed by the CPU specified by CpuIndex.\r
	188	@param[in] IdtBase The base address of the IDT to use when an SMI is\r
	189	processed by the CPU specified by CpuIndex.\r
	190	@param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
	191	processed by the CPU specified by CpuIndex.\r
	192	@param[in] Cr3 The base address of the page tables to use when an SMI\r
	193	is processed by the CPU specified by CpuIndex.\r
	194	**/\r
	195	VOID\r
	196	EFIAPI\r
	197	SmmCpuFeaturesInstallSmiHandler (\r
	198	IN UINTN CpuIndex,\r
	199	IN UINT32 SmBase,\r
	200	IN VOID *SmiStack,\r
	201	IN UINTN StackSize,\r
	202	IN UINTN GdtBase,\r
	203	IN UINTN GdtSize,\r
	204	IN UINTN IdtBase,\r
	205	IN UINTN IdtSize,\r
	206	IN UINT32 Cr3\r
	207	);\r
	208	\r
	209	/**\r
	210	Determines if MTRR registers must be configured to set SMRAM cache-ability\r
	211	when executing in System Management Mode.\r
	212	\r
	213	@retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r
	214	@retval FALSE MTRR registers do not need to be configured to set SMRAM\r
	215	cache-ability.\r
	216	**/\r
	217	BOOLEAN\r
	218	EFIAPI\r
	219	SmmCpuFeaturesNeedConfigureMtrrs (\r
	220	VOID\r
	221	);\r
	222	\r
	223	/**\r
	224	Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
	225	returns TRUE.\r
	226	**/\r
	227	VOID\r
	228	EFIAPI\r
	229	SmmCpuFeaturesDisableSmrr (\r
	230	VOID\r
	231	);\r
	232	\r
	233	/**\r
	234	Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
	235	returns TRUE.\r
	236	**/\r
	237	VOID\r
	238	EFIAPI\r
	239	SmmCpuFeaturesReenableSmrr (\r
	240	VOID\r
	241	);\r
	242	\r
	243	/**\r
	244	Processor specific hook point each time a CPU enters System Management Mode.\r
	245	\r
	246	@param[in] CpuIndex The index of the CPU that has entered SMM. The value\r
	247	must be between 0 and the NumberOfCpus field in the\r
248	System Management System Table (SMST).\r
249	**/\r
250	VOID\r
251	EFIAPI\r
252	SmmCpuFeaturesRendezvousEntry (\r
253	IN UINTN CpuIndex\r
254	);\r
255	\r
256	/**\r
257	Processor specific hook point each time a CPU exits System Management Mode.\r
258	\r
259	@param[in] CpuIndex The index of the CPU that is exiting SMM. The value must\r
260	be between 0 and the NumberOfCpus field in the System\r
261	Management System Table (SMST).\r
262	**/\r
263	VOID\r
264	EFIAPI\r
265	SmmCpuFeaturesRendezvousExit (\r
266	IN UINTN CpuIndex\r
267	);\r
268	\r
269	/**\r
270	Check to see if an SMM register is supported by a specified CPU.\r
271	\r
272	@param[in] CpuIndex The index of the CPU to check for SMM register support.\r
273	The value must be between 0 and the NumberOfCpus field\r
274	in the System Management System Table (SMST).\r
275	@param[in] RegName Identifies the SMM register to check for support.\r
276	\r
277	@retval TRUE The SMM register specified by RegName is supported by the CPU\r
278	specified by CpuIndex.\r
279	@retval FALSE The SMM register specified by RegName is not supported by the\r
280	CPU specified by CpuIndex.\r
281	**/\r
282	BOOLEAN\r
283	EFIAPI\r
284	SmmCpuFeaturesIsSmmRegisterSupported (\r
285	IN UINTN CpuIndex,\r
286	IN SMM_REG_NAME RegName\r
287	);\r
288	\r
289	/**\r
290	Returns the current value of the SMM register for the specified CPU.\r
291	If the SMM register is not supported, then 0 is returned.\r
292	\r
293	@param[in] CpuIndex The index of the CPU to read the SMM register. The\r
294	value must be between 0 and the NumberOfCpus field in\r
295	the System Management System Table (SMST).\r
296	@param[in] RegName Identifies the SMM register to read.\r
297	\r
298	@return The value of the SMM register specified by RegName from the CPU\r
299	specified by CpuIndex.\r
300	**/\r
301	UINT64\r
302	EFIAPI\r
303	SmmCpuFeaturesGetSmmRegister (\r
304	IN UINTN CpuIndex,\r
305	IN SMM_REG_NAME RegName\r
306	);\r
307	\r
308	/**\r
309	Sets the value of an SMM register on a specified CPU.\r
310	If the SMM register is not supported, then no action is performed.\r
311	\r
312	@param[in] CpuIndex The index of the CPU to write the SMM register. The\r
313	value must be between 0 and the NumberOfCpus field in\r
314	the System Management System Table (SMST).\r
315	@param[in] RegName Identifies the SMM register to write.\r
316	registers are read-only.\r
317	@param[in] Value The value to write to the SMM register.\r
318	**/\r
319	VOID\r
320	EFIAPI\r
321	SmmCpuFeaturesSetSmmRegister (\r
322	IN UINTN CpuIndex,\r
323	IN SMM_REG_NAME RegName,\r
324	IN UINT64 Value\r
325	);\r
326	\r
327	/**\r
328	Read an SMM Save State register on the target processor. If this function\r
329	returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
330	SMM Save Sate register.\r
331	\r
332	@param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r
333	value must be between 0 and the NumberOfCpus field in\r
334	the System Management System Table (SMST).\r
335	@param[in] Register The SMM Save State register to read.\r
336	@param[in] Width The number of bytes to read from the CPU save state.\r
337	@param[out] Buffer Upon return, this holds the CPU register value read\r
338	from the save state.\r
339	\r
340	@retval EFI_SUCCESS The register was read from Save State.\r
418aded9	341	@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
a9764e68 MK	342	@retval EFI_UNSUPPORTED This function does not support reading Register.\r
	343	\r
	344	**/\r
	345	EFI_STATUS\r
	346	EFIAPI\r
	347	SmmCpuFeaturesReadSaveStateRegister (\r
	348	IN UINTN CpuIndex,\r
	349	IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
	350	IN UINTN Width,\r
	351	OUT VOID *Buffer\r
	352	);\r
	353	\r
	354	/**\r
	355	Writes an SMM Save State register on the target processor. If this function\r
	356	returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
	357	SMM Save Sate register.\r
	358	\r
	359	@param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r
	360	value must be between 0 and the NumberOfCpus field in\r
	361	the System Management System Table (SMST).\r
	362	@param[in] Register The SMM Save State register to write.\r
	363	@param[in] Width The number of bytes to write to the CPU save state.\r
	364	@param[in] Buffer Upon entry, this holds the new CPU register value.\r
	365	\r
	366	@retval EFI_SUCCESS The register was written to Save State.\r
418aded9	367	@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
a9764e68 MK	368	@retval EFI_UNSUPPORTED This function does not support writing Register.\r
	369	**/\r
	370	EFI_STATUS\r
	371	EFIAPI\r
	372	SmmCpuFeaturesWriteSaveStateRegister (\r
	373	IN UINTN CpuIndex,\r
	374	IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
	375	IN UINTN Width,\r
	376	IN CONST VOID *Buffer\r
	377	);\r
	378	\r
e3840072 JY	379	/**\r
	380	This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
	381	notification is completely processed.\r
	382	**/\r
	383	VOID\r
	384	EFIAPI\r
	385	SmmCpuFeaturesCompleteSmmReadyToLock (\r
	386	VOID\r
	387	);\r
	388	\r
	389	/**\r
	390	This API provides a method for a CPU to allocate a specific region for storing page tables.\r
	391	\r
	392	This API can be called more once to allocate memory for page tables.\r
	393	\r
	394	Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
	395	allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
	396	is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
	397	returned.\r
	398	\r
	399	This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
	400	\r
	401	@param Pages The number of 4 KB pages to allocate.\r
	402	\r
	403	@return A pointer to the allocated buffer for page tables.\r
	404	@retval NULL Fail to allocate a specific region for storing page tables,\r
	405	Or there is no preference on where the page tables are allocated in SMRAM.\r
	406	\r
	407	**/\r
	408	VOID *\r
	409	EFIAPI\r
	410	SmmCpuFeaturesAllocatePageTableMemory (\r
	411	IN UINTN Pages\r
	412	);\r
	413	\r
a9764e68	414	#endif\r