[mirror_edk2.git] / UefiCpuPkg / Include / Register / LocalApic.h

/** @file\r
  IA32 Local APIC Definitions.\r
\r
  Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __LOCAL_APIC_H__\r
#define __LOCAL_APIC_H__\r
\r
//\r
// Definitions for IA32 architectural MSRs\r
//\r
#define MSR_IA32_APIC_BASE_ADDRESS              0x1B\r
\r
//\r
// Definitions for CPUID instruction\r
//\r
#define CPUID_SIGNATURE                         0x0\r
#define CPUID_VERSION_INFO                      0x1\r
#define CPUID_EXTENDED_TOPOLOGY                 0xB\r
#define CPUID_EXTENDED_FUNCTION                 0x80000000\r
#define CPUID_VIR_PHY_ADDRESS_SIZE              0x80000008\r
\r
//\r
// Definition for Local APIC registers and related values\r
//\r
#define XAPIC_ID_OFFSET                         0x20\r
#define XAPIC_VERSION_OFFSET                    0x30\r
#define XAPIC_EOI_OFFSET                        0x0b0\r
#define XAPIC_ICR_DFR_OFFSET                    0x0e0\r
#define XAPIC_SPURIOUS_VECTOR_OFFSET            0x0f0\r
#define XAPIC_ICR_LOW_OFFSET                    0x300\r
#define XAPIC_ICR_HIGH_OFFSET                   0x310\r
#define XAPIC_LVT_TIMER_OFFSET                  0x320\r
#define XAPIC_LVT_LINT0_OFFSET                  0x350\r
#define XAPIC_LVT_LINT1_OFFSET                  0x360\r
#define XAPIC_TIMER_INIT_COUNT_OFFSET           0x380\r
#define XAPIC_TIMER_CURRENT_COUNT_OFFSET        0x390\r
#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r
\r
#define X2APIC_MSR_BASE_ADDRESS                 0x800\r
#define X2APIC_MSR_ICR_ADDRESS                  0x830\r
\r
#define LOCAL_APIC_DELIVERY_MODE_FIXED           0\r
#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r
#define LOCAL_APIC_DELIVERY_MODE_SMI             2\r
#define LOCAL_APIC_DELIVERY_MODE_NMI             4\r
#define LOCAL_APIC_DELIVERY_MODE_INIT            5\r
#define LOCAL_APIC_DELIVERY_MODE_STARTUP         6\r
#define LOCAL_APIC_DELIVERY_MODE_EXTINT          7\r
\r
#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND       0\r
#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF               1\r
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
\r
typedef union {\r
  struct {\r
    UINT32  Reserved0:8;     ///< Reserved.\r
    UINT32  Bsp:1;           ///< Processor is BSP.\r
    UINT32  Reserved1:1;     ///< Reserved.\r
    UINT32  Extd:1;          ///< Enable x2APIC mode.\r
    UINT32  En:1;            ///< xAPIC global enable/disable.\r
    UINT32  ApicBaseLow:20;  ///< APIC Base physical address. The actual field width depends on physical address width.\r
    UINT32  ApicBaseHigh:32;\r
  } Bits;\r
  UINT64    Uint64;\r
} MSR_IA32_APIC_BASE;\r
\r
//\r
// Local APIC Version Register.\r
//\r
typedef union {\r
  struct {\r
    UINT32  Version:8;                  ///< The version numbers of the local APIC.\r
    UINT32  Reserved0:8;                ///< Reserved.\r
    UINT32  MaxLvtEntry:8;              ///< Number of LVT entries minus 1.\r
    UINT32  EoiBroadcastSuppression:1;  ///< 1 if EOI-broadcast suppression supported.\r
    UINT32  Reserved1:7;                ///< Reserved.\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_VERSION;\r
\r
//\r
// Low half of Interrupt Command Register (ICR).\r
//\r
typedef union {\r
  struct {\r
    UINT32  Vector:8;                ///< The vector number of the interrupt being sent.\r
    UINT32  DeliveryMode:3;          ///< Specifies the type of IPI to be sent.\r
    UINT32  DestinationMode:1;       ///< 0: physical destination mode, 1: logical destination mode.\r
    UINT32  DeliveryStatus:1;        ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.\r
    UINT32  Reserved0:1;             ///< Reserved.\r
    UINT32  Level:1;                 ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.\r
    UINT32  TriggerMode:1;           ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.\r
    UINT32  Reserved1:2;             ///< Reserved.\r
    UINT32  DestinationShorthand:2;  ///< A shorthand notation to specify the destination of the interrupt.\r
    UINT32  Reserved2:12;            ///< Reserved.\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_ICR_LOW;\r
\r
//\r
// High half of Interrupt Command Register (ICR)\r
//\r
typedef union {\r
  struct {\r
    UINT32  Reserved0:24;   ///< Reserved.\r
    UINT32  Destination:8;  ///< Specifies the target processor or processors in xAPIC mode.\r
  } Bits;\r
  UINT32    Uint32;         ///< Destination field expanded to 32-bit in x2APIC mode.\r
} LOCAL_APIC_ICR_HIGH;\r
\r
//\r
// Spurious-Interrupt Vector Register (SVR)\r
//\r
typedef union {\r
  struct {\r
    UINT32  SpuriousVector:8;           ///< Spurious Vector.\r
    UINT32  SoftwareEnable:1;           ///< APIC Software Enable/Disable.\r
    UINT32  FocusProcessorChecking:1;   ///< Focus Processor Checking.\r
    UINT32  Reserved0:2;                ///< Reserved.\r
    UINT32  EoiBroadcastSuppression:1;  ///< EOI-Broadcast Suppression.\r
    UINT32  Reserved1:19;               ///< Reserved.\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_SVR;\r
\r
//\r
// Divide Configuration Register (DCR)\r
//\r
typedef union {\r
  struct {\r
    UINT32  DivideValue1:2;  ///< Low 2 bits of the divide value.\r
    UINT32  Reserved0:1;     ///< Always 0.\r
    UINT32  DivideValue2:1;  ///< Highest 1 bit of the divide value.\r
    UINT32  Reserved1:28;    ///< Reserved.\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_DCR;\r
\r
//\r
// LVT Timer Register\r
//\r
typedef union {\r
  struct {\r
    UINT32  Vector:8;          ///< The vector number of the interrupt being sent.\r
    UINT32  Reserved0:4;       ///< Reserved.\r
    UINT32  DeliveryStatus:1;  ///< 0: Idle, 1: send pending.\r
    UINT32  Reserved1:3;       ///< Reserved.\r
    UINT32  Mask:1;            ///< 0: Not masked, 1: Masked.\r
    UINT32  TimerMode:1;       ///< 0: One-shot, 1: Periodic.\r
    UINT32  Reserved2:14;      ///< Reserved.\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_LVT_TIMER;\r
\r
//\r
// LVT LINT0/LINT1 Register\r
//\r
typedef union {\r
  struct {\r
    UINT32  Vector:8;            ///< The vector number of the interrupt being sent.\r
    UINT32  DeliveryMode:3;      ///< Specifies the type of interrupt to be sent.\r
    UINT32  Reserved0:1;         ///< Reserved.\r
    UINT32  DeliveryStatus:1;    ///< 0: Idle, 1: send pending.\r
    UINT32  InputPinPolarity:1;  ///< Interrupt Input Pin Polarity.\r
    UINT32  RemoteIrr:1;         ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.\r
    UINT32  TriggerMode:1;       ///< 0:edge, 1:level.\r
    UINT32  Mask:1;              ///< 0: Not masked, 1: Masked.\r
    UINT32  Reserved1:15;        ///< Reserved.\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_LVT_LINT;\r
\r
//\r
// MSI Address Register\r
//\r
typedef union {\r
  struct {\r
    UINT32  Reserved0:2;         ///< Reserved\r
    UINT32  DestinationMode:1;   ///< Specifies the Destination Mode.\r
    UINT32  RedirectionHint:1;   ///< Specifies the Redirection Hint.\r
    UINT32  Reserved1:8;         ///< Reserved.\r
    UINT32  DestinationId:8;     ///< Specifies the Destination ID.\r
    UINT32  BaseAddress:12;      ///< Must be 0FEEH\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_MSI_ADDRESS;\r
\r
//\r
// MSI Address Register\r
//\r
typedef union {\r
  struct {\r
    UINT32  Vector:8;            ///< Interrupt vector in range 010h..0FEH\r
    UINT32  DeliveryMode:3;      ///< Specifies the type of interrupt to be sent.\r
    UINT32  Reserved0:3;         ///< Reserved.\r
    UINT32  Level:1;             ///< 0:Deassert, 1:Assert.  Ignored for Edge triggered interrupts.\r
    UINT32  TriggerMode:1;       ///< 0:Edge,     1:Level.\r
    UINT32  Reserved1:16;        ///< Reserved.\r
    UINT32  Reserved2:32;        ///< Reserved.\r
  } Bits;\r
  UINT64    Uint64;\r
} LOCAL_APIC_MSI_DATA;\r
\r
#endif\r
\r
Commit	Line	Data
bf73cc4b	1	/** @file\r
	2	IA32 Local APIC Definitions.\r
	3	\r
6e3e4d70	4	Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>\r
bf73cc4b	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#ifndef __LOCAL_APIC_H__\r
	16	#define __LOCAL_APIC_H__\r
	17	\r
	18	//\r
	19	// Definitions for IA32 architectural MSRs\r
	20	//\r
	21	#define MSR_IA32_APIC_BASE_ADDRESS 0x1B\r
	22	\r
	23	//\r
	24	// Definitions for CPUID instruction\r
	25	//\r
6e3e4d70	26	#define CPUID_SIGNATURE 0x0\r
bf73cc4b	27	#define CPUID_VERSION_INFO 0x1\r
6e3e4d70	28	#define CPUID_EXTENDED_TOPOLOGY 0xB\r
bf73cc4b	29	#define CPUID_EXTENDED_FUNCTION 0x80000000\r
	30	#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r
	31	\r
	32	//\r
	33	// Definition for Local APIC registers and related values\r
	34	//\r
ae40aef1	35	#define XAPIC_ID_OFFSET 0x20\r
ae40aef1	36	#define XAPIC_VERSION_OFFSET 0x30\r
bf73cc4b	37	#define XAPIC_EOI_OFFSET 0x0b0\r
	38	#define XAPIC_ICR_DFR_OFFSET 0x0e0\r
	39	#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0\r
	40	#define XAPIC_ICR_LOW_OFFSET 0x300\r
	41	#define XAPIC_ICR_HIGH_OFFSET 0x310\r
	42	#define XAPIC_LVT_TIMER_OFFSET 0x320\r
ae40aef1	43	#define XAPIC_LVT_LINT0_OFFSET 0x350\r
ae40aef1	44	#define XAPIC_LVT_LINT1_OFFSET 0x360\r
bf73cc4b	45	#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380\r
	46	#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390\r
	47	#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r
	48	\r
	49	#define X2APIC_MSR_BASE_ADDRESS 0x800\r
	50	#define X2APIC_MSR_ICR_ADDRESS 0x830\r
	51	\r
	52	#define LOCAL_APIC_DELIVERY_MODE_FIXED 0\r
	53	#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r
	54	#define LOCAL_APIC_DELIVERY_MODE_SMI 2\r
	55	#define LOCAL_APIC_DELIVERY_MODE_NMI 4\r
	56	#define LOCAL_APIC_DELIVERY_MODE_INIT 5\r
	57	#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6\r
	58	#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7\r
	59	\r
	60	#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0\r
	61	#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1\r
	62	#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
	63	#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
	64	\r
	65	typedef union {\r
	66	struct {\r
23394428	67	UINT32 Reserved0:8; ///< Reserved.\r
	68	UINT32 Bsp:1; ///< Processor is BSP.\r
	69	UINT32 Reserved1:1; ///< Reserved.\r
	70	UINT32 Extd:1; ///< Enable x2APIC mode.\r
	71	UINT32 En:1; ///< xAPIC global enable/disable.\r
	72	UINT32 ApicBaseLow:20; ///< APIC Base physical address. The actual field width depends on physical address width.\r
	73	UINT32 ApicBaseHigh:32;\r
bf73cc4b	74	} Bits;\r
	75	UINT64 Uint64;\r
	76	} MSR_IA32_APIC_BASE;\r
	77	\r
ae40aef1	78	//\r
	79	// Local APIC Version Register.\r
	80	//\r
	81	typedef union {\r
	82	struct {\r
	83	UINT32 Version:8; ///< The version numbers of the local APIC.\r
	84	UINT32 Reserved0:8; ///< Reserved.\r
	85	UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.\r
	86	UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.\r
	87	UINT32 Reserved1:7; ///< Reserved.\r
	88	} Bits;\r
	89	UINT32 Uint32;\r
	90	} LOCAL_APIC_VERSION;\r
	91	\r
bf73cc4b	92	//\r
	93	// Low half of Interrupt Command Register (ICR).\r
	94	//\r
	95	typedef union {\r
	96	struct {\r
	97	UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
	98	UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.\r
	99	UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.\r
	100	UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.\r
	101	UINT32 Reserved0:1; ///< Reserved.\r
	102	UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.\r
	103	UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.\r
	104	UINT32 Reserved1:2; ///< Reserved.\r
	105	UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.\r
	106	UINT32 Reserved2:12; ///< Reserved.\r
	107	} Bits;\r
	108	UINT32 Uint32;\r
	109	} LOCAL_APIC_ICR_LOW;\r
	110	\r
	111	//\r
	112	// High half of Interrupt Command Register (ICR)\r
	113	//\r
	114	typedef union {\r
	115	struct {\r
	116	UINT32 Reserved0:24; ///< Reserved.\r
	117	UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.\r
	118	} Bits;\r
	119	UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.\r
	120	} LOCAL_APIC_ICR_HIGH;\r
	121	\r
	122	//\r
	123	// Spurious-Interrupt Vector Register (SVR)\r
	124	//\r
	125	typedef union {\r
	126	struct {\r
	127	UINT32 SpuriousVector:8; ///< Spurious Vector.\r
	128	UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.\r
	129	UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.\r
	130	UINT32 Reserved0:2; ///< Reserved.\r
	131	UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.\r
	132	UINT32 Reserved1:19; ///< Reserved.\r
	133	} Bits;\r
	134	UINT32 Uint32;\r
	135	} LOCAL_APIC_SVR;\r
	136	\r
	137	//\r
	138	// Divide Configuration Register (DCR)\r
	139	//\r
	140	typedef union {\r
	141	struct {\r
	142	UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.\r
	143	UINT32 Reserved0:1; ///< Always 0.\r
	144	UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.\r
	145	UINT32 Reserved1:28; ///< Reserved.\r
	146	} Bits;\r
	147	UINT32 Uint32;\r
	148	} LOCAL_APIC_DCR;\r
	149	\r
	150	//\r
	151	// LVT Timer Register\r
	152	//\r
	153	typedef union {\r
	154	struct {\r
	155	UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
156	UINT32 Reserved0:4; ///< Reserved.\r
157	UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r
158	UINT32 Reserved1:3; ///< Reserved.\r
159	UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r
160	UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.\r
161	UINT32 Reserved2:14; ///< Reserved.\r
162	} Bits;\r
163	UINT32 Uint32;\r
164	} LOCAL_APIC_LVT_TIMER;\r
165	\r
166	//\r
167	// LVT LINT0/LINT1 Register\r
168	//\r
169	typedef union {\r
170	struct {\r
171	UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
172	UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r
173	UINT32 Reserved0:1; ///< Reserved.\r
174	UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r
175	UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.\r
176	UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.\r
177	UINT32 TriggerMode:1; ///< 0:edge, 1:level.\r
178	UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r
179	UINT32 Reserved1:15; ///< Reserved.\r
180	} Bits;\r
181	UINT32 Uint32;\r
182	} LOCAL_APIC_LVT_LINT;\r
183	\r
5f867ad0	184	//\r
	185	// MSI Address Register\r
	186	//\r
	187	typedef union {\r
	188	struct {\r
	189	UINT32 Reserved0:2; ///< Reserved\r
	190	UINT32 DestinationMode:1; ///< Specifies the Destination Mode.\r
	191	UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.\r
	192	UINT32 Reserved1:8; ///< Reserved.\r
	193	UINT32 DestinationId:8; ///< Specifies the Destination ID.\r
	194	UINT32 BaseAddress:12; ///< Must be 0FEEH\r
	195	} Bits;\r
	196	UINT32 Uint32;\r
	197	} LOCAL_APIC_MSI_ADDRESS;\r
	198	\r
	199	//\r
	200	// MSI Address Register\r
	201	//\r
	202	typedef union {\r
	203	struct {\r
	204	UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH\r
	205	UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r
	206	UINT32 Reserved0:3; ///< Reserved.\r
	207	UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.\r
	208	UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.\r
	209	UINT32 Reserved1:16; ///< Reserved.\r
	210	UINT32 Reserved2:32; ///< Reserved.\r
	211	} Bits;\r
	212	UINT64 Uint64;\r
	213	} LOCAL_APIC_MSI_DATA;\r
	214	\r
bf73cc4b	215	#endif\r
bf73cc4b	216	\r