projects / mirror_edk2.git / blame
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| bf73cc4b | 1 | /** @file\r |
| 2 | IA32 Local APIC Definitions.\r | |
| 3 | \r | |
| d32c7f6c | 4 | Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r |
| bf73cc4b | 5 | This program and the accompanying materials\r |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #ifndef __LOCAL_APIC_H__\r | |
| 16 | #define __LOCAL_APIC_H__\r | |
| 17 | \r | |
| 18 | //\r | |
| 19 | // Definitions for IA32 architectural MSRs\r | |
| 20 | //\r | |
| 21 | #define MSR_IA32_APIC_BASE_ADDRESS 0x1B\r | |
| 22 | \r | |
| 23 | //\r | |
| 24 | // Definitions for CPUID instruction\r | |
| 25 | //\r | |
| 6e3e4d70 | 26 | #define CPUID_SIGNATURE 0x0\r |
| bf73cc4b | 27 | #define CPUID_VERSION_INFO 0x1\r |
| d32c7f6c | 28 | #define CPUID_CACHE_PARAMS 0x4\r |
| 6e3e4d70 | 29 | #define CPUID_EXTENDED_TOPOLOGY 0xB\r |
| d32c7f6c JF |
30 | #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x0\r |
| 31 | #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x1\r | |
| 32 | #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x2\r | |
| bf73cc4b | 33 | #define CPUID_EXTENDED_FUNCTION 0x80000000\r |
| 34 | #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r | |
| 35 | \r | |
| 36 | //\r | |
| 37 | // Definition for Local APIC registers and related values\r | |
| 38 | //\r | |
| ae40aef1 | 39 | #define XAPIC_ID_OFFSET 0x20\r |
| 40 | #define XAPIC_VERSION_OFFSET 0x30\r | |
| bf73cc4b | 41 | #define XAPIC_EOI_OFFSET 0x0b0\r |
| 42 | #define XAPIC_ICR_DFR_OFFSET 0x0e0\r | |
| 43 | #define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0\r | |
| 44 | #define XAPIC_ICR_LOW_OFFSET 0x300\r | |
| 45 | #define XAPIC_ICR_HIGH_OFFSET 0x310\r | |
| 46 | #define XAPIC_LVT_TIMER_OFFSET 0x320\r | |
| ae40aef1 | 47 | #define XAPIC_LVT_LINT0_OFFSET 0x350\r |
| 48 | #define XAPIC_LVT_LINT1_OFFSET 0x360\r | |
| bf73cc4b | 49 | #define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380\r |
| 50 | #define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390\r | |
| 51 | #define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r | |
| 52 | \r | |
| 53 | #define X2APIC_MSR_BASE_ADDRESS 0x800\r | |
| 54 | #define X2APIC_MSR_ICR_ADDRESS 0x830\r | |
| 55 | \r | |
| 56 | #define LOCAL_APIC_DELIVERY_MODE_FIXED 0\r | |
| 57 | #define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r | |
| 58 | #define LOCAL_APIC_DELIVERY_MODE_SMI 2\r | |
| 59 | #define LOCAL_APIC_DELIVERY_MODE_NMI 4\r | |
| 60 | #define LOCAL_APIC_DELIVERY_MODE_INIT 5\r | |
| 61 | #define LOCAL_APIC_DELIVERY_MODE_STARTUP 6\r | |
| 62 | #define LOCAL_APIC_DELIVERY_MODE_EXTINT 7\r | |
| 63 | \r | |
| 64 | #define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0\r | |
| 65 | #define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1\r | |
| 66 | #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r | |
| 67 | #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r | |
| 68 | \r | |
| 69 | typedef union {\r | |
| 70 | struct {\r | |
| 23394428 | 71 | UINT32 Reserved0:8; ///< Reserved.\r |
| 72 | UINT32 Bsp:1; ///< Processor is BSP.\r | |
| 73 | UINT32 Reserved1:1; ///< Reserved.\r | |
| 74 | UINT32 Extd:1; ///< Enable x2APIC mode.\r | |
| 75 | UINT32 En:1; ///< xAPIC global enable/disable.\r | |
| 76 | UINT32 ApicBaseLow:20; ///< APIC Base physical address. The actual field width depends on physical address width.\r | |
| 77 | UINT32 ApicBaseHigh:32;\r | |
| bf73cc4b | 78 | } Bits;\r |
| 79 | UINT64 Uint64;\r | |
| 80 | } MSR_IA32_APIC_BASE;\r | |
| 81 | \r | |
| ae40aef1 | 82 | //\r |
| 83 | // Local APIC Version Register.\r | |
| 84 | //\r | |
| 85 | typedef union {\r | |
| 86 | struct {\r | |
| 87 | UINT32 Version:8; ///< The version numbers of the local APIC.\r | |
| 88 | UINT32 Reserved0:8; ///< Reserved.\r | |
| 89 | UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.\r | |
| 90 | UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.\r | |
| 91 | UINT32 Reserved1:7; ///< Reserved.\r | |
| 92 | } Bits;\r | |
| 93 | UINT32 Uint32;\r | |
| 94 | } LOCAL_APIC_VERSION;\r | |
| 95 | \r | |
| bf73cc4b | 96 | //\r |
| 97 | // Low half of Interrupt Command Register (ICR).\r | |
| 98 | //\r | |
| 99 | typedef union {\r | |
| 100 | struct {\r | |
| 101 | UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r | |
| 102 | UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.\r | |
| 103 | UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.\r | |
| 104 | UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.\r | |
| 105 | UINT32 Reserved0:1; ///< Reserved.\r | |
| 106 | UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.\r | |
| 107 | UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.\r | |
| 108 | UINT32 Reserved1:2; ///< Reserved.\r | |
| 109 | UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.\r | |
| 110 | UINT32 Reserved2:12; ///< Reserved.\r | |
| 111 | } Bits;\r | |
| 112 | UINT32 Uint32;\r | |
| 113 | } LOCAL_APIC_ICR_LOW;\r | |
| 114 | \r | |
| 115 | //\r | |
| 116 | // High half of Interrupt Command Register (ICR)\r | |
| 117 | //\r | |
| 118 | typedef union {\r | |
| 119 | struct {\r | |
| 120 | UINT32 Reserved0:24; ///< Reserved.\r | |
| 121 | UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.\r | |
| 122 | } Bits;\r | |
| 123 | UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.\r | |
| 124 | } LOCAL_APIC_ICR_HIGH;\r | |
| 125 | \r | |
| 126 | //\r | |
| 127 | // Spurious-Interrupt Vector Register (SVR)\r | |
| 128 | //\r | |
| 129 | typedef union {\r | |
| 130 | struct {\r | |
| 131 | UINT32 SpuriousVector:8; ///< Spurious Vector.\r | |
| 132 | UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.\r | |
| 133 | UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.\r | |
| 134 | UINT32 Reserved0:2; ///< Reserved.\r | |
| 135 | UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.\r | |
| 136 | UINT32 Reserved1:19; ///< Reserved.\r | |
| 137 | } Bits;\r | |
| 138 | UINT32 Uint32;\r | |
| 139 | } LOCAL_APIC_SVR;\r | |
| 140 | \r | |
| 141 | //\r | |
| 142 | // Divide Configuration Register (DCR)\r | |
| 143 | //\r | |
| 144 | typedef union {\r | |
| 145 | struct {\r | |
| 146 | UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.\r | |
| 147 | UINT32 Reserved0:1; ///< Always 0.\r | |
| 148 | UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.\r | |
| 149 | UINT32 Reserved1:28; ///< Reserved.\r | |
| 150 | } Bits;\r | |
| 151 | UINT32 Uint32;\r | |
| 152 | } LOCAL_APIC_DCR;\r | |
| 153 | \r | |
| 154 | //\r | |
| 155 | // LVT Timer Register\r | |
| 156 | //\r | |
| 157 | typedef union {\r | |
| 158 | struct {\r | |
| 159 | UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r | |
| 160 | UINT32 Reserved0:4; ///< Reserved.\r | |
| 161 | UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r | |
| 162 | UINT32 Reserved1:3; ///< Reserved.\r | |
| 163 | UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r | |
| 164 | UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.\r | |
| 165 | UINT32 Reserved2:14; ///< Reserved.\r | |
| 166 | } Bits;\r | |
| 167 | UINT32 Uint32;\r | |
| 168 | } LOCAL_APIC_LVT_TIMER;\r | |
| 169 | \r | |
| 170 | //\r | |
| 171 | // LVT LINT0/LINT1 Register\r | |
| 172 | //\r | |
| 173 | typedef union {\r | |
| 174 | struct {\r | |
| 175 | UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r | |
| 176 | UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r | |
| 177 | UINT32 Reserved0:1; ///< Reserved.\r | |
| 178 | UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r | |
| 179 | UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.\r | |
| 180 | UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.\r | |
| 181 | UINT32 TriggerMode:1; ///< 0:edge, 1:level.\r | |
| 182 | UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r | |
| 183 | UINT32 Reserved1:15; ///< Reserved.\r | |
| 184 | } Bits;\r | |
| 185 | UINT32 Uint32;\r | |
| 186 | } LOCAL_APIC_LVT_LINT;\r | |
| 187 | \r | |
| 5f867ad0 | 188 | //\r |
| 189 | // MSI Address Register\r | |
| 190 | //\r | |
| 191 | typedef union {\r | |
| 192 | struct {\r | |
| 193 | UINT32 Reserved0:2; ///< Reserved\r | |
| 194 | UINT32 DestinationMode:1; ///< Specifies the Destination Mode.\r | |
| 195 | UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.\r | |
| 196 | UINT32 Reserved1:8; ///< Reserved.\r | |
| 197 | UINT32 DestinationId:8; ///< Specifies the Destination ID.\r | |
| 198 | UINT32 BaseAddress:12; ///< Must be 0FEEH\r | |
| 199 | } Bits;\r | |
| 200 | UINT32 Uint32;\r | |
| 201 | } LOCAL_APIC_MSI_ADDRESS;\r | |
| 202 | \r | |
| 203 | //\r | |
| 204 | // MSI Address Register\r | |
| 205 | //\r | |
| 206 | typedef union {\r | |
| 207 | struct {\r | |
| 208 | UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH\r | |
| 209 | UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r | |
| 210 | UINT32 Reserved0:3; ///< Reserved.\r | |
| 211 | UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.\r | |
| 212 | UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.\r | |
| 213 | UINT32 Reserved1:16; ///< Reserved.\r | |
| 214 | UINT32 Reserved2:32; ///< Reserved.\r | |
| 215 | } Bits;\r | |
| 216 | UINT64 Uint64;\r | |
| 217 | } LOCAL_APIC_MSI_DATA;\r | |
| 218 | \r | |
| bf73cc4b | 219 | #endif\r |
| 220 | \r |