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c67b579c
MK		 1/** @file\r
2 MSR Definitions for Intel processors based on the Haswell-E microarchitecture.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11.\r
21\r
22**/\r
23\r
24#ifndef __HASWELL_E_MSR_H__\r
25#define __HASWELL_E_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
29/**\r
30 Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
31 specific C-state code names, unrelated to MWAIT extension C-state parameters\r
32 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
33\r
34 @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
35 @param EAX Lower 32-bits of MSR value.\r
36 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.\r
37 @param EDX Upper 32-bits of MSR value.\r
38 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.\r
39\r
40 <b>Example usage</b>\r
41 @code\r
42 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
43\r
44 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);\r
45 AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
46 @endcode\r
a73ab083 47 @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
c67b579c
MK		 48**/\r
49#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2\r
50\r
51/**\r
52 MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL\r
53**/\r
54typedef union {\r
55 ///\r
56 /// Individual bit fields\r
57 ///\r
58 struct {\r
59 ///\r
60 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
61 /// processor-specific C-state code name (consuming the least power) for\r
62 /// the package. The default is set as factory-configured package C-state\r
63 /// limit. The following C-state code name encodings are supported: 000b:\r
64 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
65 /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
66 /// supported by the processor are available.\r
67 ///\r
68 UINT32 Limit:3;\r
69 UINT32 Reserved1:7;\r
70 ///\r
71 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
72 ///\r
73 UINT32 IO_MWAIT:1;\r
74 UINT32 Reserved2:4;\r
75 ///\r
76 /// [Bit 15] CFG Lock (R/WO).\r
77 ///\r
78 UINT32 CFGLock:1;\r
79 UINT32 Reserved3:9;\r
80 ///\r
81 /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
82 ///\r
83 UINT32 C3AutoDemotion:1;\r
84 ///\r
85 /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
86 ///\r
87 UINT32 C1AutoDemotion:1;\r
88 ///\r
89 /// [Bit 27] Enable C3 Undemotion (R/W).\r
90 ///\r
91 UINT32 C3Undemotion:1;\r
92 ///\r
93 /// [Bit 28] Enable C1 Undemotion (R/W).\r
94 ///\r
95 UINT32 C1Undemotion:1;\r
96 ///\r
97 /// [Bit 29] Package C State Demotion Enable (R/W).\r
98 ///\r
99 UINT32 CStateDemotion:1;\r
100 ///\r
101 /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
102 ///\r
103 UINT32 CStateUndemotion:1;\r
104 UINT32 Reserved4:1;\r
105 UINT32 Reserved5:32;\r
106 } Bits;\r
107 ///\r
108 /// All bit fields as a 32-bit value\r
109 ///\r
110 UINT32 Uint32;\r
111 ///\r
112 /// All bit fields as a 64-bit value\r
113 ///\r
114 UINT64 Uint64;\r
115} MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;\r
116\r
117\r
118/**\r
119 Thread. Global Machine Check Capability (R/O).\r
120\r
121 @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)\r
122 @param EAX Lower 32-bits of MSR value.\r
123 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.\r
124 @param EDX Upper 32-bits of MSR value.\r
125 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.\r
126\r
127 <b>Example usage</b>\r
128 @code\r
129 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr;\r
130\r
131 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);\r
132 @endcode\r
a73ab083 133 @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
c67b579c
MK		 134**/\r
135#define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179\r
136\r
137/**\r
138 MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP\r
139**/\r
140typedef union {\r
141 ///\r
142 /// Individual bit fields\r
143 ///\r
144 struct {\r
145 ///\r
146 /// [Bits 7:0] Count.\r
147 ///\r
148 UINT32 Count:8;\r
149 ///\r
150 /// [Bit 8] MCG_CTL_P.\r
151 ///\r
152 UINT32 MCG_CTL_P:1;\r
153 ///\r
154 /// [Bit 9] MCG_EXT_P.\r
155 ///\r
156 UINT32 MCG_EXT_P:1;\r
157 ///\r
158 /// [Bit 10] MCP_CMCI_P.\r
159 ///\r
160 UINT32 MCP_CMCI_P:1;\r
161 ///\r
162 /// [Bit 11] MCG_TES_P.\r
163 ///\r
164 UINT32 MCG_TES_P:1;\r
165 UINT32 Reserved1:4;\r
166 ///\r
167 /// [Bits 23:16] MCG_EXT_CNT.\r
168 ///\r
169 UINT32 MCG_EXT_CNT:8;\r
170 ///\r
171 /// [Bit 24] MCG_SER_P.\r
172 ///\r
173 UINT32 MCG_SER_P:1;\r
174 ///\r
175 /// [Bit 25] MCG_EM_P.\r
176 ///\r
177 UINT32 MCG_EM_P:1;\r
178 ///\r
179 /// [Bit 26] MCG_ELOG_P.\r
180 ///\r
181 UINT32 MCG_ELOG_P:1;\r
182 UINT32 Reserved2:5;\r
183 UINT32 Reserved3:32;\r
184 } Bits;\r
185 ///\r
186 /// All bit fields as a 32-bit value\r
187 ///\r
188 UINT32 Uint32;\r
189 ///\r
190 /// All bit fields as a 64-bit value\r
191 ///\r
192 UINT64 Uint64;\r
193} MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;\r
194\r
195\r
196/**\r
197 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
198 Enhancement. Accessible only while in SMM.\r
199\r
200 @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)\r
201 @param EAX Lower 32-bits of MSR value.\r
202 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.\r
203 @param EDX Upper 32-bits of MSR value.\r
204 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.\r
205\r
206 <b>Example usage</b>\r
207 @code\r
208 MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr;\r
209\r
210 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);\r
211 AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);\r
212 @endcode\r
a73ab083 213 @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
c67b579c
MK		 214**/\r
215#define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D\r
216\r
217/**\r
218 MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP\r
219**/\r
220typedef union {\r
221 ///\r
222 /// Individual bit fields\r
223 ///\r
224 struct {\r
225 UINT32 Reserved1:32;\r
226 UINT32 Reserved2:26;\r
227 ///\r
228 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
229 /// SMM code access restriction is supported and a host-space interface\r
230 /// available to SMM handler.\r
231 ///\r
232 UINT32 SMM_Code_Access_Chk:1;\r
233 ///\r
234 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
235 /// SMM long flow indicator is supported and a host-space interface\r
236 /// available to SMM handler.\r
237 ///\r
238 UINT32 Long_Flow_Indication:1;\r
239 UINT32 Reserved3:4;\r
240 } Bits;\r
241 ///\r
242 /// All bit fields as a 64-bit value\r
243 ///\r
244 UINT64 Uint64;\r
245} MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;\r
246\r
247\r
248/**\r
249 Package. MC Bank Error Configuration (R/W).\r
250\r
251 @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)\r
252 @param EAX Lower 32-bits of MSR value.\r
253 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.\r
254 @param EDX Upper 32-bits of MSR value.\r
255 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.\r
256\r
257 <b>Example usage</b>\r
258 @code\r
259 MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr;\r
260\r
261 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);\r
262 AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);\r
263 @endcode\r
a73ab083 264 @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
c67b579c
MK		 265**/\r
266#define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F\r
267\r
268/**\r
269 MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL\r
270**/\r
271typedef union {\r
272 ///\r
273 /// Individual bit fields\r
274 ///\r
275 struct {\r
276 UINT32 Reserved1:1;\r
277 ///\r
278 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
279 /// to log additional info in bits 36:32.\r
280 ///\r
281 UINT32 MemErrorLogEnable:1;\r
282 UINT32 Reserved2:30;\r
283 UINT32 Reserved3:32;\r
284 } Bits;\r
285 ///\r
286 /// All bit fields as a 32-bit value\r
287 ///\r
288 UINT32 Uint32;\r
289 ///\r
290 /// All bit fields as a 64-bit value\r
291 ///\r
292 UINT64 Uint64;\r
293} MSR_HASWELL_E_ERROR_CONTROL_REGISTER;\r
294\r
295\r
296/**\r
297 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
298 RW if MSR_PLATFORM_INFO.[28] = 1.\r
299\r
300 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)\r
301 @param EAX Lower 32-bits of MSR value.\r
302 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.\r
303 @param EDX Upper 32-bits of MSR value.\r
304 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.\r
305\r
306 <b>Example usage</b>\r
307 @code\r
308 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr;\r
309\r
310 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);\r
311 @endcode\r
a73ab083 312 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
c67b579c
MK		 313**/\r
314#define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD\r
315\r
316/**\r
317 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT\r
318**/\r
319typedef union {\r
320 ///\r
321 /// Individual bit fields\r
322 ///\r
323 struct {\r
324 ///\r
325 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
326 /// limit of 1 core active.\r
327 ///\r
328 UINT32 Maximum1C:8;\r
329 ///\r
330 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
331 /// limit of 2 core active.\r
332 ///\r
333 UINT32 Maximum2C:8;\r
334 ///\r
335 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
336 /// limit of 3 core active.\r
337 ///\r
338 UINT32 Maximum3C:8;\r
339 ///\r
340 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
341 /// limit of 4 core active.\r
342 ///\r
343 UINT32 Maximum4C:8;\r
344 ///\r
345 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
346 /// limit of 5 core active.\r
347 ///\r
348 UINT32 Maximum5C:8;\r
349 ///\r
350 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
351 /// limit of 6 core active.\r
352 ///\r
353 UINT32 Maximum6C:8;\r
354 ///\r
355 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
356 /// limit of 7 core active.\r
357 ///\r
358 UINT32 Maximum7C:8;\r
359 ///\r
360 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
361 /// limit of 8 core active.\r
362 ///\r
363 UINT32 Maximum8C:8;\r
364 } Bits;\r
365 ///\r
366 /// All bit fields as a 64-bit value\r
367 ///\r
368 UINT64 Uint64;\r
369} MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;\r
370\r
371\r
372/**\r
373 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
374 RW if MSR_PLATFORM_INFO.[28] = 1.\r
375\r
376 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)\r
377 @param EAX Lower 32-bits of MSR value.\r
378 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.\r
379 @param EDX Upper 32-bits of MSR value.\r
380 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.\r
381\r
382 <b>Example usage</b>\r
383 @code\r
384 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
385\r
386 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);\r
387 @endcode\r
a73ab083 388 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
c67b579c
MK		 389**/\r
390#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE\r
391\r
392/**\r
393 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1\r
394**/\r
395typedef union {\r
396 ///\r
397 /// Individual bit fields\r
398 ///\r
399 struct {\r
400 ///\r
401 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r
402 /// limit of 9 core active.\r
403 ///\r
404 UINT32 Maximum9C:8;\r
405 ///\r
406 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r
407 /// limit of 10 core active.\r
408 ///\r
409 UINT32 Maximum10C:8;\r
410 ///\r
411 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r
412 /// limit of 11 core active.\r
413 ///\r
414 UINT32 Maximum11C:8;\r
415 ///\r
416 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r
417 /// limit of 12 core active.\r
418 ///\r
419 UINT32 Maximum12C:8;\r
420 ///\r
421 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r
422 /// limit of 13 core active.\r
423 ///\r
424 UINT32 Maximum13C:8;\r
425 ///\r
426 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r
427 /// limit of 14 core active.\r
428 ///\r
429 UINT32 Maximum14C:8;\r
430 ///\r
431 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r
432 /// limit of 15 core active.\r
433 ///\r
434 UINT32 Maximum15C:8;\r
435 ///\r
436 /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio\r
437 /// limit of 16 core active.\r
438 ///\r
439 UINT32 Maximum16C:8;\r
440 } Bits;\r
441 ///\r
442 /// All bit fields as a 64-bit value\r
443 ///\r
444 UINT64 Uint64;\r
445} MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;\r
446\r
447\r
448/**\r
449 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
450 RW if MSR_PLATFORM_INFO.[28] = 1.\r
451\r
452 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)\r
453 @param EAX Lower 32-bits of MSR value.\r
454 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.\r
455 @param EDX Upper 32-bits of MSR value.\r
456 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.\r
457\r
458 <b>Example usage</b>\r
459 @code\r
460 MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr;\r
461\r
462 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);\r
463 @endcode\r
a73ab083 464 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.\r
c67b579c
MK		 465**/\r
466#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF\r
467\r
468/**\r
469 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2\r
470**/\r
471typedef union {\r
472 ///\r
473 /// Individual bit fields\r
474 ///\r
475 struct {\r
476 ///\r
477 /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio\r
478 /// limit of 17 core active.\r
479 ///\r
480 UINT32 Maximum17C:8;\r
481 ///\r
482 /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio\r
483 /// limit of 18 core active.\r
484 ///\r
485 UINT32 Maximum18C:8;\r
486 UINT32 Reserved1:16;\r
487 UINT32 Reserved2:31;\r
488 ///\r
489 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
490 /// the processor uses override configuration specified in\r
491 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and\r
492 /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set\r
493 /// configuration (Default).\r
494 ///\r
495 UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
496 } Bits;\r
497 ///\r
498 /// All bit fields as a 64-bit value\r
499 ///\r
500 UINT64 Uint64;\r
501} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;\r
502\r
503\r
504/**\r
505 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
506 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
507\r
508 * Bank MC5 reports MC error from the Intel QPI 0 module.\r
509 * Bank MC6 reports MC error from the integrated I/O module.\r
510 * Bank MC7 reports MC error from the home agent HA 0.\r
511 * Bank MC8 reports MC error from the home agent HA 1.\r
512 * Banks MC9 through MC16 report MC error from each channel of the integrated\r
513 memory controllers.\r
514 * Bank MC17 reports MC error from the following pair of CBo/L3 Slices\r
515 (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.\r
516 * Bank MC18 reports MC error from the following pair of CBo/L3 Slices\r
517 (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.\r
518 * Bank MC19 reports MC error from the following pair of CBo/L3 Slices\r
519 (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.\r
520 * Bank MC20 reports MC error from the Intel QPI 1 module.\r
521 * Bank MC21 reports MC error from the Intel QPI 2 module.\r
522\r
523 @param ECX MSR_HASWELL_E_MCi_CTL\r
524 @param EAX Lower 32-bits of MSR value.\r
525 @param EDX Upper 32-bits of MSR value.\r
526\r
527 <b>Example usage</b>\r
528 @code\r
529 UINT64 Msr;\r
530\r
531 Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_CTL);\r
532 AsmWriteMsr64 (MSR_HASWELL_E_MC5_CTL, Msr);\r
533 @endcode\r
a73ab083
JF		 534 @note MSR_HASWELL_E_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
535 MSR_HASWELL_E_MC6_CTL is defined as MSR_MC6_CTL in SDM.\r
536 MSR_HASWELL_E_MC7_CTL is defined as MSR_MC7_CTL in SDM.\r
537 MSR_HASWELL_E_MC8_CTL is defined as MSR_MC8_CTL in SDM.\r
538 MSR_HASWELL_E_MC9_CTL is defined as MSR_MC9_CTL in SDM.\r
539 MSR_HASWELL_E_MC10_CTL is defined as MSR_MC10_CTL in SDM.\r
540 MSR_HASWELL_E_MC11_CTL is defined as MSR_MC11_CTL in SDM.\r
541 MSR_HASWELL_E_MC12_CTL is defined as MSR_MC12_CTL in SDM.\r
542 MSR_HASWELL_E_MC13_CTL is defined as MSR_MC13_CTL in SDM.\r
543 MSR_HASWELL_E_MC14_CTL is defined as MSR_MC14_CTL in SDM.\r
544 MSR_HASWELL_E_MC15_CTL is defined as MSR_MC15_CTL in SDM.\r
545 MSR_HASWELL_E_MC16_CTL is defined as MSR_MC16_CTL in SDM.\r
546 MSR_HASWELL_E_MC17_CTL is defined as MSR_MC17_CTL in SDM.\r
547 MSR_HASWELL_E_MC18_CTL is defined as MSR_MC18_CTL in SDM.\r
548 MSR_HASWELL_E_MC19_CTL is defined as MSR_MC19_CTL in SDM.\r
549 MSR_HASWELL_E_MC20_CTL is defined as MSR_MC20_CTL in SDM.\r
550 MSR_HASWELL_E_MC21_CTL is defined as MSR_MC21_CTL in SDM.\r
c67b579c
MK		 551 @{\r
552**/\r
553#define MSR_HASWELL_E_MC5_CTL 0x00000414\r
554#define MSR_HASWELL_E_MC6_CTL 0x00000418\r
555#define MSR_HASWELL_E_MC7_CTL 0x0000041C\r
556#define MSR_HASWELL_E_MC8_CTL 0x00000420\r
557#define MSR_HASWELL_E_MC9_CTL 0x00000424\r
558#define MSR_HASWELL_E_MC10_CTL 0x00000428\r
559#define MSR_HASWELL_E_MC11_CTL 0x0000042C\r
560#define MSR_HASWELL_E_MC12_CTL 0x00000430\r
561#define MSR_HASWELL_E_MC13_CTL 0x00000434\r
562#define MSR_HASWELL_E_MC14_CTL 0x00000438\r
563#define MSR_HASWELL_E_MC15_CTL 0x0000043C\r
564#define MSR_HASWELL_E_MC16_CTL 0x00000440\r
565#define MSR_HASWELL_E_MC17_CTL 0x00000444\r
566#define MSR_HASWELL_E_MC18_CTL 0x00000448\r
567#define MSR_HASWELL_E_MC19_CTL 0x0000044C\r
568#define MSR_HASWELL_E_MC20_CTL 0x00000450\r
569#define MSR_HASWELL_E_MC21_CTL 0x00000454\r
570/// @}\r
571\r
572\r
573/**\r
574 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
575 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
576\r
577 @param ECX MSR_HASWELL_E_MCi_STATUS\r
578 @param EAX Lower 32-bits of MSR value.\r
579 @param EDX Upper 32-bits of MSR value.\r
580\r
581 <b>Example usage</b>\r
582 @code\r
583 UINT64 Msr;\r
584\r
585 Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_STATUS);\r
586 AsmWriteMsr64 (MSR_HASWELL_E_MC5_STATUS, Msr);\r
587 @endcode\r
a73ab083
JF		 588 @note MSR_HASWELL_E_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
589 MSR_HASWELL_E_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
590 MSR_HASWELL_E_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.\r
591 MSR_HASWELL_E_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.\r
592 MSR_HASWELL_E_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.\r
593 MSR_HASWELL_E_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.\r
594 MSR_HASWELL_E_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.\r
595 MSR_HASWELL_E_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.\r
596 MSR_HASWELL_E_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.\r
597 MSR_HASWELL_E_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.\r
598 MSR_HASWELL_E_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.\r
599 MSR_HASWELL_E_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.\r
600 MSR_HASWELL_E_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.\r
601 MSR_HASWELL_E_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.\r
602 MSR_HASWELL_E_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.\r
603 MSR_HASWELL_E_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.\r
604 MSR_HASWELL_E_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.\r
c67b579c
MK		 605 @{\r
606**/\r
607#define MSR_HASWELL_E_MC5_STATUS 0x00000415\r
608#define MSR_HASWELL_E_MC6_STATUS 0x00000419\r
609#define MSR_HASWELL_E_MC7_STATUS 0x0000041D\r
610#define MSR_HASWELL_E_MC8_STATUS 0x00000421\r
611#define MSR_HASWELL_E_MC9_STATUS 0x00000425\r
612#define MSR_HASWELL_E_MC10_STATUS 0x00000429\r
613#define MSR_HASWELL_E_MC11_STATUS 0x0000042D\r
614#define MSR_HASWELL_E_MC12_STATUS 0x00000431\r
615#define MSR_HASWELL_E_MC13_STATUS 0x00000435\r
616#define MSR_HASWELL_E_MC14_STATUS 0x00000439\r
617#define MSR_HASWELL_E_MC15_STATUS 0x0000043D\r
618#define MSR_HASWELL_E_MC16_STATUS 0x00000441\r
619#define MSR_HASWELL_E_MC17_STATUS 0x00000445\r
620#define MSR_HASWELL_E_MC18_STATUS 0x00000449\r
621#define MSR_HASWELL_E_MC19_STATUS 0x0000044D\r
622#define MSR_HASWELL_E_MC20_STATUS 0x00000451\r
623#define MSR_HASWELL_E_MC21_STATUS 0x00000455\r
624/// @}\r
625\r
626/**\r
627 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
628 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
629\r
630 @param ECX MSR_HASWELL_E_MCi_ADDR\r
631 @param EAX Lower 32-bits of MSR value.\r
632 @param EDX Upper 32-bits of MSR value.\r
633\r
634 <b>Example usage</b>\r
635 @code\r
636 UINT64 Msr;\r
637\r
638 Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_ADDR);\r
639 AsmWriteMsr64 (MSR_HASWELL_E_MC5_ADDR, Msr);\r
640 @endcode\r
a73ab083
JF		 641 @note MSR_HASWELL_E_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
642 MSR_HASWELL_E_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.\r
643 MSR_HASWELL_E_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.\r
644 MSR_HASWELL_E_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.\r
645 MSR_HASWELL_E_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.\r
646 MSR_HASWELL_E_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.\r
647 MSR_HASWELL_E_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.\r
648 MSR_HASWELL_E_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.\r
649 MSR_HASWELL_E_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.\r
650 MSR_HASWELL_E_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.\r
651 MSR_HASWELL_E_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.\r
652 MSR_HASWELL_E_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.\r
653 MSR_HASWELL_E_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.\r
654 MSR_HASWELL_E_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.\r
655 MSR_HASWELL_E_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.\r
656 MSR_HASWELL_E_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.\r
657 MSR_HASWELL_E_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.\r
c67b579c
MK		 658 @{\r
659**/\r
660#define MSR_HASWELL_E_MC5_ADDR 0x00000416\r
661#define MSR_HASWELL_E_MC6_ADDR 0x0000041A\r
662#define MSR_HASWELL_E_MC7_ADDR 0x0000041E\r
663#define MSR_HASWELL_E_MC8_ADDR 0x00000422\r
664#define MSR_HASWELL_E_MC9_ADDR 0x00000426\r
665#define MSR_HASWELL_E_MC10_ADDR 0x0000042A\r
666#define MSR_HASWELL_E_MC11_ADDR 0x0000042E\r
667#define MSR_HASWELL_E_MC12_ADDR 0x00000432\r
668#define MSR_HASWELL_E_MC13_ADDR 0x00000436\r
669#define MSR_HASWELL_E_MC14_ADDR 0x0000043A\r
670#define MSR_HASWELL_E_MC15_ADDR 0x0000043E\r
671#define MSR_HASWELL_E_MC16_ADDR 0x00000442\r
672#define MSR_HASWELL_E_MC17_ADDR 0x00000446\r
673#define MSR_HASWELL_E_MC18_ADDR 0x0000044A\r
674#define MSR_HASWELL_E_MC19_ADDR 0x0000044E\r
675#define MSR_HASWELL_E_MC20_ADDR 0x00000452\r
676#define MSR_HASWELL_E_MC21_ADDR 0x00000456\r
677/// @}\r
678\r
679\r
680/**\r
681 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
682 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
683\r
684 @param ECX MSR_HASWELL_E_MCi_MISC\r
685 @param EAX Lower 32-bits of MSR value.\r
686 @param EDX Upper 32-bits of MSR value.\r
687\r
688 <b>Example usage</b>\r
689 @code\r
690 UINT64 Msr;\r
691\r
692 Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_MISC);\r
693 AsmWriteMsr64 (MSR_HASWELL_E_MC5_MISC, Msr);\r
694 @endcode\r
a73ab083
JF		 695 @note MSR_HASWELL_E_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
696 MSR_HASWELL_E_MC6_MISC is defined as MSR_MC6_MISC in SDM.\r
697 MSR_HASWELL_E_MC7_MISC is defined as MSR_MC7_MISC in SDM.\r
698 MSR_HASWELL_E_MC8_MISC is defined as MSR_MC8_MISC in SDM.\r
699 MSR_HASWELL_E_MC9_MISC is defined as MSR_MC9_MISC in SDM.\r
700 MSR_HASWELL_E_MC10_MISC is defined as MSR_MC10_MISC in SDM.\r
701 MSR_HASWELL_E_MC11_MISC is defined as MSR_MC11_MISC in SDM.\r
702 MSR_HASWELL_E_MC12_MISC is defined as MSR_MC12_MISC in SDM.\r
703 MSR_HASWELL_E_MC13_MISC is defined as MSR_MC13_MISC in SDM.\r
704 MSR_HASWELL_E_MC14_MISC is defined as MSR_MC14_MISC in SDM.\r
705 MSR_HASWELL_E_MC15_MISC is defined as MSR_MC15_MISC in SDM.\r
706 MSR_HASWELL_E_MC16_MISC is defined as MSR_MC16_MISC in SDM.\r
707 MSR_HASWELL_E_MC17_MISC is defined as MSR_MC17_MISC in SDM.\r
708 MSR_HASWELL_E_MC18_MISC is defined as MSR_MC18_MISC in SDM.\r
709 MSR_HASWELL_E_MC19_MISC is defined as MSR_MC19_MISC in SDM.\r
710 MSR_HASWELL_E_MC20_MISC is defined as MSR_MC20_MISC in SDM.\r
711 MSR_HASWELL_E_MC21_MISC is defined as MSR_MC21_MISC in SDM.\r
c67b579c
MK		 712 @{\r
713**/\r
714#define MSR_HASWELL_E_MC5_MISC 0x00000417\r
715#define MSR_HASWELL_E_MC6_MISC 0x0000041B\r
716#define MSR_HASWELL_E_MC7_MISC 0x0000041F\r
717#define MSR_HASWELL_E_MC8_MISC 0x00000423\r
718#define MSR_HASWELL_E_MC9_MISC 0x00000427\r
719#define MSR_HASWELL_E_MC10_MISC 0x0000042B\r
720#define MSR_HASWELL_E_MC11_MISC 0x0000042F\r
721#define MSR_HASWELL_E_MC12_MISC 0x00000433\r
722#define MSR_HASWELL_E_MC13_MISC 0x00000437\r
723#define MSR_HASWELL_E_MC14_MISC 0x0000043B\r
724#define MSR_HASWELL_E_MC15_MISC 0x0000043F\r
725#define MSR_HASWELL_E_MC16_MISC 0x00000443\r
726#define MSR_HASWELL_E_MC17_MISC 0x00000447\r
727#define MSR_HASWELL_E_MC18_MISC 0x0000044B\r
728#define MSR_HASWELL_E_MC19_MISC 0x0000044F\r
729#define MSR_HASWELL_E_MC20_MISC 0x00000453\r
730#define MSR_HASWELL_E_MC21_MISC 0x00000457\r
731/// @}\r
732\r
733\r
734/**\r
735 Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
736\r
737 @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)\r
738 @param EAX Lower 32-bits of MSR value.\r
739 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.\r
740 @param EDX Upper 32-bits of MSR value.\r
741 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.\r
742\r
743 <b>Example usage</b>\r
744 @code\r
745 MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr;\r
746\r
747 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);\r
748 @endcode\r
a73ab083 749 @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
c67b579c
MK		 750**/\r
751#define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606\r
752\r
753/**\r
754 MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT\r
755**/\r
756typedef union {\r
757 ///\r
758 /// Individual bit fields\r
759 ///\r
760 struct {\r
761 ///\r
762 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
763 ///\r
764 UINT32 PowerUnits:4;\r
765 UINT32 Reserved1:4;\r
766 ///\r
767 /// [Bits 12:8] Package. Energy Status Units Energy related information\r
768 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
769 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
770 /// micro-joules).\r
771 ///\r
772 UINT32 EnergyStatusUnits:5;\r
773 UINT32 Reserved2:3;\r
774 ///\r
775 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
776 /// Interfaces.".\r
777 ///\r
778 UINT32 TimeUnits:4;\r
779 UINT32 Reserved3:12;\r
780 UINT32 Reserved4:32;\r
781 } Bits;\r
782 ///\r
783 /// All bit fields as a 32-bit value\r
784 ///\r
785 UINT32 Uint32;\r
786 ///\r
787 /// All bit fields as a 64-bit value\r
788 ///\r
789 UINT64 Uint64;\r
790} MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;\r
791\r
792\r
793/**\r
794 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
795 Domain.".\r
796\r
797 @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)\r
798 @param EAX Lower 32-bits of MSR value.\r
799 @param EDX Upper 32-bits of MSR value.\r
800\r
801 <b>Example usage</b>\r
802 @code\r
803 UINT64 Msr;\r
804\r
805 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);\r
806 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);\r
807 @endcode\r
a73ab083 808 @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
c67b579c
MK		 809**/\r
810#define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618\r
811\r
812\r
813/**\r
814 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
815\r
816 @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)\r
817 @param EAX Lower 32-bits of MSR value.\r
818 @param EDX Upper 32-bits of MSR value.\r
819\r
820 <b>Example usage</b>\r
821 @code\r
822 UINT64 Msr;\r
823\r
824 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);\r
825 @endcode\r
a73ab083 826 @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
c67b579c
MK		 827**/\r
828#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619\r
829\r
830\r
831/**\r
832 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
833 RAPL Domain.".\r
834\r
835 @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)\r
836 @param EAX Lower 32-bits of MSR value.\r
837 @param EDX Upper 32-bits of MSR value.\r
838\r
839 <b>Example usage</b>\r
840 @code\r
841 UINT64 Msr;\r
842\r
843 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);\r
844 @endcode\r
a73ab083 845 @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
c67b579c
MK		 846**/\r
847#define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B\r
848\r
849\r
850/**\r
851 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
852\r
853 @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)\r
854 @param EAX Lower 32-bits of MSR value.\r
855 @param EDX Upper 32-bits of MSR value.\r
856\r
857 <b>Example usage</b>\r
858 @code\r
859 UINT64 Msr;\r
860\r
861 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);\r
862 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);\r
863 @endcode\r
a73ab083 864 @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
c67b579c
MK		 865**/\r
866#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C\r
867\r
868\r
869/**\r
870 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
871 refers to processor core frequency).\r
872\r
873 @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)\r
874 @param EAX Lower 32-bits of MSR value.\r
875 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.\r
876 @param EDX Upper 32-bits of MSR value.\r
877 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.\r
878\r
879 <b>Example usage</b>\r
880 @code\r
881 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
882\r
883 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);\r
884 AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
885 @endcode\r
a73ab083 886 @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
c67b579c
MK		 887**/\r
888#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690\r
889\r
890/**\r
891 MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS\r
892**/\r
893typedef union {\r
894 ///\r
895 /// Individual bit fields\r
896 ///\r
897 struct {\r
898 ///\r
899 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
900 /// reduced below the operating system request due to assertion of\r
901 /// external PROCHOT.\r
902 ///\r
903 UINT32 PROCHOT_Status:1;\r
904 ///\r
905 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
906 /// operating system request due to a thermal event.\r
907 ///\r
908 UINT32 ThermalStatus:1;\r
909 ///\r
910 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
911 /// reduced below the operating system request due to PBM limit.\r
912 ///\r
913 UINT32 PowerBudgetManagementStatus:1;\r
914 ///\r
915 /// [Bit 3] Platform Configuration Services Status (R0) When set,\r
916 /// frequency is reduced below the operating system request due to PCS\r
917 /// limit.\r
918 ///\r
919 UINT32 PlatformConfigurationServicesStatus:1;\r
920 UINT32 Reserved1:1;\r
921 ///\r
922 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
923 /// When set, frequency is reduced below the operating system request\r
924 /// because the processor has detected that utilization is low.\r
925 ///\r
926 UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
927 ///\r
928 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
929 /// below the operating system request due to a thermal alert from the\r
930 /// Voltage Regulator.\r
931 ///\r
932 UINT32 VRThermAlertStatus:1;\r
933 UINT32 Reserved2:1;\r
934 ///\r
935 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
936 /// reduced below the operating system request due to electrical design\r
937 /// point constraints (e.g. maximum electrical current consumption).\r
938 ///\r
939 UINT32 ElectricalDesignPointStatus:1;\r
940 UINT32 Reserved3:1;\r
941 ///\r
942 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
943 /// below the operating system request due to Multi-Core Turbo limits.\r
944 ///\r
945 UINT32 MultiCoreTurboStatus:1;\r
946 UINT32 Reserved4:2;\r
947 ///\r
948 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
949 /// below max non-turbo P1.\r
950 ///\r
951 UINT32 FrequencyP1Status:1;\r
952 ///\r
953 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
954 /// set, frequency is reduced below max n-core turbo frequency.\r
955 ///\r
956 UINT32 TurboFrequencyLimitingStatus:1;\r
957 ///\r
958 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
959 /// reduced below the operating system request.\r
960 ///\r
961 UINT32 FrequencyLimitingStatus:1;\r
962 ///\r
963 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
964 /// has asserted since the log bit was last cleared. This log bit will\r
965 /// remain set until cleared by software writing 0.\r
966 ///\r
967 UINT32 PROCHOT_Log:1;\r
968 ///\r
969 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
970 /// has asserted since the log bit was last cleared. This log bit will\r
971 /// remain set until cleared by software writing 0.\r
972 ///\r
973 UINT32 ThermalLog:1;\r
974 ///\r
975 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
976 /// Status bit has asserted since the log bit was last cleared. This log\r
977 /// bit will remain set until cleared by software writing 0.\r
978 ///\r
979 UINT32 PowerBudgetManagementLog:1;\r
980 ///\r
981 /// [Bit 19] Platform Configuration Services Log When set, indicates that\r
982 /// the PCS Status bit has asserted since the log bit was last cleared.\r
983 /// This log bit will remain set until cleared by software writing 0.\r
984 ///\r
985 UINT32 PlatformConfigurationServicesLog:1;\r
986 UINT32 Reserved5:1;\r
987 ///\r
988 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
989 /// indicates that the AUBFC Status bit has asserted since the log bit was\r
990 /// last cleared. This log bit will remain set until cleared by software\r
991 /// writing 0.\r
992 ///\r
993 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
994 ///\r
995 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
996 /// Alert Status bit has asserted since the log bit was last cleared. This\r
997 /// log bit will remain set until cleared by software writing 0.\r
998 ///\r
999 UINT32 VRThermAlertLog:1;\r
1000 UINT32 Reserved6:1;\r
1001 ///\r
1002 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
1003 /// Status bit has asserted since the log bit was last cleared. This log\r
1004 /// bit will remain set until cleared by software writing 0.\r
1005 ///\r
1006 UINT32 ElectricalDesignPointLog:1;\r
1007 UINT32 Reserved7:1;\r
1008 ///\r
1009 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
1010 /// Turbo Status bit has asserted since the log bit was last cleared. This\r
1011 /// log bit will remain set until cleared by software writing 0.\r
1012 ///\r
1013 UINT32 MultiCoreTurboLog:1;\r
1014 UINT32 Reserved8:2;\r
1015 ///\r
1016 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
1017 /// Frequency P1 Status bit has asserted since the log bit was last\r
1018 /// cleared. This log bit will remain set until cleared by software\r
1019 /// writing 0.\r
1020 ///\r
1021 UINT32 CoreFrequencyP1Log:1;\r
1022 ///\r
1023 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
1024 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
1025 /// has asserted since the log bit was last cleared. This log bit will\r
1026 /// remain set until cleared by software writing 0.\r
1027 ///\r
1028 UINT32 TurboFrequencyLimitingLog:1;\r
1029 ///\r
1030 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
1031 /// Frequency Limiting Status bit has asserted since the log bit was last\r
1032 /// cleared. This log bit will remain set until cleared by software\r
1033 /// writing 0.\r
1034 ///\r
1035 UINT32 CoreFrequencyLimitingLog:1;\r
1036 UINT32 Reserved9:32;\r
1037 } Bits;\r
1038 ///\r
1039 /// All bit fields as a 32-bit value\r
1040 ///\r
1041 UINT32 Uint32;\r
1042 ///\r
1043 /// All bit fields as a 64-bit value\r
1044 ///\r
1045 UINT64 Uint64;\r
1046} MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;\r
1047\r
1048\r
1049/**\r
1050 THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,\r
1051 ECX=0):EBX.PQM[bit 12] = 1.\r
1052\r
1053 @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)\r
1054 @param EAX Lower 32-bits of MSR value.\r
1055 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.\r
1056 @param EDX Upper 32-bits of MSR value.\r
1057 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.\r
1058\r
1059 <b>Example usage</b>\r
1060 @code\r
1061 MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr;\r
1062\r
1063 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);\r
1064 AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);\r
1065 @endcode\r
a73ab083 1066 @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
c67b579c
MK		 1067**/\r
1068#define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D\r
1069\r
1070/**\r
1071 MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL\r
1072**/\r
1073typedef union {\r
1074 ///\r
1075 /// Individual bit fields\r
1076 ///\r
1077 struct {\r
1078 ///\r
1079 /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3\r
1080 /// occupancy monitoring all other encoding reserved..\r
1081 ///\r
1082 UINT32 EventID:8;\r
1083 UINT32 Reserved1:24;\r
1084 ///\r
1085 /// [Bits 41:32] RMID (RW).\r
1086 ///\r
1087 UINT32 RMID:10;\r
1088 UINT32 Reserved2:22;\r
1089 } Bits;\r
1090 ///\r
1091 /// All bit fields as a 64-bit value\r
1092 ///\r
1093 UINT64 Uint64;\r
1094} MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;\r
1095\r
1096\r
1097/**\r
1098 THREAD. Resource Association Register (R/W)..\r
1099\r
1100 @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)\r
1101 @param EAX Lower 32-bits of MSR value.\r
1102 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.\r
1103 @param EDX Upper 32-bits of MSR value.\r
1104 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.\r
1105\r
1106 <b>Example usage</b>\r
1107 @code\r
1108 MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr;\r
1109\r
1110 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);\r
1111 AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);\r
1112 @endcode\r
a73ab083 1113 @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
c67b579c
MK		 1114**/\r
1115#define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F\r
1116\r
1117/**\r
1118 MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC\r
1119**/\r
1120typedef union {\r
1121 ///\r
1122 /// Individual bit fields\r
1123 ///\r
1124 struct {\r
1125 ///\r
1126 /// [Bits 9:0] RMID.\r
1127 ///\r
1128 UINT32 RMID:10;\r
1129 UINT32 Reserved1:22;\r
1130 UINT32 Reserved2:32;\r
1131 } Bits;\r
1132 ///\r
1133 /// All bit fields as a 32-bit value\r
1134 ///\r
1135 UINT32 Uint32;\r
1136 ///\r
1137 /// All bit fields as a 64-bit value\r
1138 ///\r
1139 UINT64 Uint64;\r
1140} MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;\r
1141\r
1142\r
1143/**\r
1144 Package. Uncore perfmon per-socket global control.\r
1145\r
1146 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)\r
1147 @param EAX Lower 32-bits of MSR value.\r
1148 @param EDX Upper 32-bits of MSR value.\r
1149\r
1150 <b>Example usage</b>\r
1151 @code\r
1152 UINT64 Msr;\r
1153\r
1154 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);\r
1155 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);\r
1156 @endcode\r
a73ab083 1157 @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r
c67b579c
MK		 1158**/\r
1159#define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700\r
1160\r
1161\r
1162/**\r
1163 Package. Uncore perfmon per-socket global status.\r
1164\r
1165 @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)\r
1166 @param EAX Lower 32-bits of MSR value.\r
1167 @param EDX Upper 32-bits of MSR value.\r
1168\r
1169 <b>Example usage</b>\r
1170 @code\r
1171 UINT64 Msr;\r
1172\r
1173 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);\r
1174 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);\r
1175 @endcode\r
a73ab083 1176 @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r
c67b579c
MK		 1177**/\r
1178#define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701\r
1179\r
1180\r
1181/**\r
1182 Package. Uncore perfmon per-socket global configuration.\r
1183\r
1184 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)\r
1185 @param EAX Lower 32-bits of MSR value.\r
1186 @param EDX Upper 32-bits of MSR value.\r
1187\r
1188 <b>Example usage</b>\r
1189 @code\r
1190 UINT64 Msr;\r
1191\r
1192 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);\r
1193 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);\r
1194 @endcode\r
a73ab083 1195 @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r
c67b579c
MK		 1196**/\r
1197#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702\r
1198\r
1199\r
1200/**\r
1201 Package. Uncore U-box UCLK fixed counter control.\r
1202\r
1203 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)\r
1204 @param EAX Lower 32-bits of MSR value.\r
1205 @param EDX Upper 32-bits of MSR value.\r
1206\r
1207 <b>Example usage</b>\r
1208 @code\r
1209 UINT64 Msr;\r
1210\r
1211 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);\r
1212 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);\r
1213 @endcode\r
a73ab083 1214 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r
c67b579c
MK		 1215**/\r
1216#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703\r
1217\r
1218\r
1219/**\r
1220 Package. Uncore U-box UCLK fixed counter.\r
1221\r
1222 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)\r
1223 @param EAX Lower 32-bits of MSR value.\r
1224 @param EDX Upper 32-bits of MSR value.\r
1225\r
1226 <b>Example usage</b>\r
1227 @code\r
1228 UINT64 Msr;\r
1229\r
1230 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);\r
1231 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);\r
1232 @endcode\r
a73ab083 1233 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r
c67b579c
MK		 1234**/\r
1235#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704\r
1236\r
1237\r
1238/**\r
1239 Package. Uncore U-box perfmon event select for U-box counter 0.\r
1240\r
1241 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)\r
1242 @param EAX Lower 32-bits of MSR value.\r
1243 @param EDX Upper 32-bits of MSR value.\r
1244\r
1245 <b>Example usage</b>\r
1246 @code\r
1247 UINT64 Msr;\r
1248\r
1249 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);\r
1250 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);\r
1251 @endcode\r
a73ab083 1252 @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 1253**/\r
1254#define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705\r
1255\r
1256\r
1257/**\r
1258 Package. Uncore U-box perfmon event select for U-box counter 1.\r
1259\r
1260 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)\r
1261 @param EAX Lower 32-bits of MSR value.\r
1262 @param EDX Upper 32-bits of MSR value.\r
1263\r
1264 <b>Example usage</b>\r
1265 @code\r
1266 UINT64 Msr;\r
1267\r
1268 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);\r
1269 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);\r
1270 @endcode\r
a73ab083 1271 @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 1272**/\r
1273#define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706\r
1274\r
1275\r
1276/**\r
1277 Package. Uncore U-box perfmon U-box wide status.\r
1278\r
1279 @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)\r
1280 @param EAX Lower 32-bits of MSR value.\r
1281 @param EDX Upper 32-bits of MSR value.\r
1282\r
1283 <b>Example usage</b>\r
1284 @code\r
1285 UINT64 Msr;\r
1286\r
1287 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);\r
1288 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);\r
1289 @endcode\r
a73ab083 1290 @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 1291**/\r
1292#define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708\r
1293\r
1294\r
1295/**\r
1296 Package. Uncore U-box perfmon counter 0.\r
1297\r
1298 @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)\r
1299 @param EAX Lower 32-bits of MSR value.\r
1300 @param EDX Upper 32-bits of MSR value.\r
1301\r
1302 <b>Example usage</b>\r
1303 @code\r
1304 UINT64 Msr;\r
1305\r
1306 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);\r
1307 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);\r
1308 @endcode\r
a73ab083 1309 @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r
c67b579c
MK		 1310**/\r
1311#define MSR_HASWELL_E_U_PMON_CTR0 0x00000709\r
1312\r
1313\r
1314/**\r
1315 Package. Uncore U-box perfmon counter 1.\r
1316\r
1317 @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)\r
1318 @param EAX Lower 32-bits of MSR value.\r
1319 @param EDX Upper 32-bits of MSR value.\r
1320\r
1321 <b>Example usage</b>\r
1322 @code\r
1323 UINT64 Msr;\r
1324\r
1325 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);\r
1326 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);\r
1327 @endcode\r
a73ab083 1328 @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r
c67b579c
MK		 1329**/\r
1330#define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A\r
1331\r
1332\r
1333/**\r
1334 Package. Uncore PCU perfmon for PCU-box-wide control.\r
1335\r
1336 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)\r
1337 @param EAX Lower 32-bits of MSR value.\r
1338 @param EDX Upper 32-bits of MSR value.\r
1339\r
1340 <b>Example usage</b>\r
1341 @code\r
1342 UINT64 Msr;\r
1343\r
1344 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);\r
1345 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);\r
1346 @endcode\r
a73ab083 1347 @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 1348**/\r
1349#define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710\r
1350\r
1351\r
1352/**\r
1353 Package. Uncore PCU perfmon event select for PCU counter 0.\r
1354\r
1355 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)\r
1356 @param EAX Lower 32-bits of MSR value.\r
1357 @param EDX Upper 32-bits of MSR value.\r
1358\r
1359 <b>Example usage</b>\r
1360 @code\r
1361 UINT64 Msr;\r
1362\r
1363 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);\r
1364 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);\r
1365 @endcode\r
a73ab083 1366 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 1367**/\r
1368#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711\r
1369\r
1370\r
1371/**\r
1372 Package. Uncore PCU perfmon event select for PCU counter 1.\r
1373\r
1374 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)\r
1375 @param EAX Lower 32-bits of MSR value.\r
1376 @param EDX Upper 32-bits of MSR value.\r
1377\r
1378 <b>Example usage</b>\r
1379 @code\r
1380 UINT64 Msr;\r
1381\r
1382 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);\r
1383 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);\r
1384 @endcode\r
a73ab083 1385 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 1386**/\r
1387#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712\r
1388\r
1389\r
1390/**\r
1391 Package. Uncore PCU perfmon event select for PCU counter 2.\r
1392\r
1393 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)\r
1394 @param EAX Lower 32-bits of MSR value.\r
1395 @param EDX Upper 32-bits of MSR value.\r
1396\r
1397 <b>Example usage</b>\r
1398 @code\r
1399 UINT64 Msr;\r
1400\r
1401 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);\r
1402 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);\r
1403 @endcode\r
a73ab083 1404 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 1405**/\r
1406#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713\r
1407\r
1408\r
1409/**\r
1410 Package. Uncore PCU perfmon event select for PCU counter 3.\r
1411\r
1412 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)\r
1413 @param EAX Lower 32-bits of MSR value.\r
1414 @param EDX Upper 32-bits of MSR value.\r
1415\r
1416 <b>Example usage</b>\r
1417 @code\r
1418 UINT64 Msr;\r
1419\r
1420 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);\r
1421 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);\r
1422 @endcode\r
a73ab083 1423 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 1424**/\r
1425#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714\r
1426\r
1427\r
1428/**\r
1429 Package. Uncore PCU perfmon box-wide filter.\r
1430\r
1431 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)\r
1432 @param EAX Lower 32-bits of MSR value.\r
1433 @param EDX Upper 32-bits of MSR value.\r
1434\r
1435 <b>Example usage</b>\r
1436 @code\r
1437 UINT64 Msr;\r
1438\r
1439 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);\r
1440 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);\r
1441 @endcode\r
a73ab083 1442 @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r
c67b579c
MK		 1443**/\r
1444#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715\r
1445\r
1446\r
1447/**\r
1448 Package. Uncore PCU perfmon box wide status.\r
1449\r
1450 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)\r
1451 @param EAX Lower 32-bits of MSR value.\r
1452 @param EDX Upper 32-bits of MSR value.\r
1453\r
1454 <b>Example usage</b>\r
1455 @code\r
1456 UINT64 Msr;\r
1457\r
1458 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);\r
1459 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);\r
1460 @endcode\r
a73ab083 1461 @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 1462**/\r
1463#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716\r
1464\r
1465\r
1466/**\r
1467 Package. Uncore PCU perfmon counter 0.\r
1468\r
1469 @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)\r
1470 @param EAX Lower 32-bits of MSR value.\r
1471 @param EDX Upper 32-bits of MSR value.\r
1472\r
1473 <b>Example usage</b>\r
1474 @code\r
1475 UINT64 Msr;\r
1476\r
1477 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);\r
1478 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);\r
1479 @endcode\r
a73ab083 1480 @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r
c67b579c
MK		 1481**/\r
1482#define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717\r
1483\r
1484\r
1485/**\r
1486 Package. Uncore PCU perfmon counter 1.\r
1487\r
1488 @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)\r
1489 @param EAX Lower 32-bits of MSR value.\r
1490 @param EDX Upper 32-bits of MSR value.\r
1491\r
1492 <b>Example usage</b>\r
1493 @code\r
1494 UINT64 Msr;\r
1495\r
1496 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);\r
1497 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);\r
1498 @endcode\r
a73ab083 1499 @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r
c67b579c
MK		 1500**/\r
1501#define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718\r
1502\r
1503\r
1504/**\r
1505 Package. Uncore PCU perfmon counter 2.\r
1506\r
1507 @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)\r
1508 @param EAX Lower 32-bits of MSR value.\r
1509 @param EDX Upper 32-bits of MSR value.\r
1510\r
1511 <b>Example usage</b>\r
1512 @code\r
1513 UINT64 Msr;\r
1514\r
1515 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);\r
1516 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);\r
1517 @endcode\r
a73ab083 1518 @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r
c67b579c
MK		 1519**/\r
1520#define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719\r
1521\r
1522\r
1523/**\r
1524 Package. Uncore PCU perfmon counter 3.\r
1525\r
1526 @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)\r
1527 @param EAX Lower 32-bits of MSR value.\r
1528 @param EDX Upper 32-bits of MSR value.\r
1529\r
1530 <b>Example usage</b>\r
1531 @code\r
1532 UINT64 Msr;\r
1533\r
1534 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);\r
1535 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);\r
1536 @endcode\r
a73ab083 1537 @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r
c67b579c
MK		 1538**/\r
1539#define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A\r
1540\r
1541\r
1542/**\r
1543 Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.\r
1544\r
1545 @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)\r
1546 @param EAX Lower 32-bits of MSR value.\r
1547 @param EDX Upper 32-bits of MSR value.\r
1548\r
1549 <b>Example usage</b>\r
1550 @code\r
1551 UINT64 Msr;\r
1552\r
1553 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);\r
1554 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);\r
1555 @endcode\r
a73ab083 1556 @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 1557**/\r
1558#define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720\r
1559\r
1560\r
1561/**\r
1562 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.\r
1563\r
1564 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)\r
1565 @param EAX Lower 32-bits of MSR value.\r
1566 @param EDX Upper 32-bits of MSR value.\r
1567\r
1568 <b>Example usage</b>\r
1569 @code\r
1570 UINT64 Msr;\r
1571\r
1572 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);\r
1573 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);\r
1574 @endcode\r
a73ab083 1575 @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 1576**/\r
1577#define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721\r
1578\r
1579\r
1580/**\r
1581 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.\r
1582\r
1583 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)\r
1584 @param EAX Lower 32-bits of MSR value.\r
1585 @param EDX Upper 32-bits of MSR value.\r
1586\r
1587 <b>Example usage</b>\r
1588 @code\r
1589 UINT64 Msr;\r
1590\r
1591 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);\r
1592 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);\r
1593 @endcode\r
a73ab083 1594 @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 1595**/\r
1596#define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722\r
1597\r
1598\r
1599/**\r
1600 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.\r
1601\r
1602 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)\r
1603 @param EAX Lower 32-bits of MSR value.\r
1604 @param EDX Upper 32-bits of MSR value.\r
1605\r
1606 <b>Example usage</b>\r
1607 @code\r
1608 UINT64 Msr;\r
1609\r
1610 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);\r
1611 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);\r
1612 @endcode\r
a73ab083 1613 @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 1614**/\r
1615#define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723\r
1616\r
1617\r
1618/**\r
1619 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.\r
1620\r
1621 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)\r
1622 @param EAX Lower 32-bits of MSR value.\r
1623 @param EDX Upper 32-bits of MSR value.\r
1624\r
1625 <b>Example usage</b>\r
1626 @code\r
1627 UINT64 Msr;\r
1628\r
1629 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);\r
1630 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);\r
1631 @endcode\r
a73ab083 1632 @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 1633**/\r
1634#define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724\r
1635\r
1636\r
1637/**\r
1638 Package. Uncore SBo 0 perfmon box-wide filter.\r
1639\r
1640 @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)\r
1641 @param EAX Lower 32-bits of MSR value.\r
1642 @param EDX Upper 32-bits of MSR value.\r
1643\r
1644 <b>Example usage</b>\r
1645 @code\r
1646 UINT64 Msr;\r
1647\r
1648 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);\r
1649 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);\r
1650 @endcode\r
a73ab083 1651 @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.\r
c67b579c
MK		 1652**/\r
1653#define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725\r
1654\r
1655\r
1656/**\r
1657 Package. Uncore SBo 0 perfmon counter 0.\r
1658\r
1659 @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)\r
1660 @param EAX Lower 32-bits of MSR value.\r
1661 @param EDX Upper 32-bits of MSR value.\r
1662\r
1663 <b>Example usage</b>\r
1664 @code\r
1665 UINT64 Msr;\r
1666\r
1667 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);\r
1668 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);\r
1669 @endcode\r
a73ab083 1670 @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r
c67b579c
MK		 1671**/\r
1672#define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726\r
1673\r
1674\r
1675/**\r
1676 Package. Uncore SBo 0 perfmon counter 1.\r
1677\r
1678 @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)\r
1679 @param EAX Lower 32-bits of MSR value.\r
1680 @param EDX Upper 32-bits of MSR value.\r
1681\r
1682 <b>Example usage</b>\r
1683 @code\r
1684 UINT64 Msr;\r
1685\r
1686 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);\r
1687 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);\r
1688 @endcode\r
a73ab083 1689 @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r
c67b579c
MK		 1690**/\r
1691#define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727\r
1692\r
1693\r
1694/**\r
1695 Package. Uncore SBo 0 perfmon counter 2.\r
1696\r
1697 @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)\r
1698 @param EAX Lower 32-bits of MSR value.\r
1699 @param EDX Upper 32-bits of MSR value.\r
1700\r
1701 <b>Example usage</b>\r
1702 @code\r
1703 UINT64 Msr;\r
1704\r
1705 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);\r
1706 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);\r
1707 @endcode\r
a73ab083 1708 @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r
c67b579c
MK		 1709**/\r
1710#define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728\r
1711\r
1712\r
1713/**\r
1714 Package. Uncore SBo 0 perfmon counter 3.\r
1715\r
1716 @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)\r
1717 @param EAX Lower 32-bits of MSR value.\r
1718 @param EDX Upper 32-bits of MSR value.\r
1719\r
1720 <b>Example usage</b>\r
1721 @code\r
1722 UINT64 Msr;\r
1723\r
1724 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);\r
1725 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);\r
1726 @endcode\r
a73ab083 1727 @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r
c67b579c
MK		 1728**/\r
1729#define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729\r
1730\r
1731\r
1732/**\r
1733 Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.\r
1734\r
1735 @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)\r
1736 @param EAX Lower 32-bits of MSR value.\r
1737 @param EDX Upper 32-bits of MSR value.\r
1738\r
1739 <b>Example usage</b>\r
1740 @code\r
1741 UINT64 Msr;\r
1742\r
1743 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);\r
1744 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);\r
1745 @endcode\r
a73ab083 1746 @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 1747**/\r
1748#define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A\r
1749\r
1750\r
1751/**\r
1752 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.\r
1753\r
1754 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)\r
1755 @param EAX Lower 32-bits of MSR value.\r
1756 @param EDX Upper 32-bits of MSR value.\r
1757\r
1758 <b>Example usage</b>\r
1759 @code\r
1760 UINT64 Msr;\r
1761\r
1762 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);\r
1763 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);\r
1764 @endcode\r
a73ab083 1765 @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 1766**/\r
1767#define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B\r
1768\r
1769\r
1770/**\r
1771 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.\r
1772\r
1773 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)\r
1774 @param EAX Lower 32-bits of MSR value.\r
1775 @param EDX Upper 32-bits of MSR value.\r
1776\r
1777 <b>Example usage</b>\r
1778 @code\r
1779 UINT64 Msr;\r
1780\r
1781 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);\r
1782 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);\r
1783 @endcode\r
a73ab083 1784 @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 1785**/\r
1786#define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C\r
1787\r
1788\r
1789/**\r
1790 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.\r
1791\r
1792 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)\r
1793 @param EAX Lower 32-bits of MSR value.\r
1794 @param EDX Upper 32-bits of MSR value.\r
1795\r
1796 <b>Example usage</b>\r
1797 @code\r
1798 UINT64 Msr;\r
1799\r
1800 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);\r
1801 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);\r
1802 @endcode\r
a73ab083 1803 @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 1804**/\r
1805#define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D\r
1806\r
1807\r
1808/**\r
1809 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.\r
1810\r
1811 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)\r
1812 @param EAX Lower 32-bits of MSR value.\r
1813 @param EDX Upper 32-bits of MSR value.\r
1814\r
1815 <b>Example usage</b>\r
1816 @code\r
1817 UINT64 Msr;\r
1818\r
1819 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);\r
1820 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);\r
1821 @endcode\r
a73ab083 1822 @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 1823**/\r
1824#define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E\r
1825\r
1826\r
1827/**\r
1828 Package. Uncore SBo 1 perfmon box-wide filter.\r
1829\r
1830 @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)\r
1831 @param EAX Lower 32-bits of MSR value.\r
1832 @param EDX Upper 32-bits of MSR value.\r
1833\r
1834 <b>Example usage</b>\r
1835 @code\r
1836 UINT64 Msr;\r
1837\r
1838 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);\r
1839 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);\r
1840 @endcode\r
a73ab083 1841 @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.\r
c67b579c
MK		 1842**/\r
1843#define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F\r
1844\r
1845\r
1846/**\r
1847 Package. Uncore SBo 1 perfmon counter 0.\r
1848\r
1849 @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)\r
1850 @param EAX Lower 32-bits of MSR value.\r
1851 @param EDX Upper 32-bits of MSR value.\r
1852\r
1853 <b>Example usage</b>\r
1854 @code\r
1855 UINT64 Msr;\r
1856\r
1857 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);\r
1858 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);\r
1859 @endcode\r
a73ab083 1860 @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r
c67b579c
MK		 1861**/\r
1862#define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730\r
1863\r
1864\r
1865/**\r
1866 Package. Uncore SBo 1 perfmon counter 1.\r
1867\r
1868 @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)\r
1869 @param EAX Lower 32-bits of MSR value.\r
1870 @param EDX Upper 32-bits of MSR value.\r
1871\r
1872 <b>Example usage</b>\r
1873 @code\r
1874 UINT64 Msr;\r
1875\r
1876 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);\r
1877 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);\r
1878 @endcode\r
a73ab083 1879 @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r
c67b579c
MK		 1880**/\r
1881#define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731\r
1882\r
1883\r
1884/**\r
1885 Package. Uncore SBo 1 perfmon counter 2.\r
1886\r
1887 @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)\r
1888 @param EAX Lower 32-bits of MSR value.\r
1889 @param EDX Upper 32-bits of MSR value.\r
1890\r
1891 <b>Example usage</b>\r
1892 @code\r
1893 UINT64 Msr;\r
1894\r
1895 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);\r
1896 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);\r
1897 @endcode\r
a73ab083 1898 @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r
c67b579c
MK		 1899**/\r
1900#define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732\r
1901\r
1902\r
1903/**\r
1904 Package. Uncore SBo 1 perfmon counter 3.\r
1905\r
1906 @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)\r
1907 @param EAX Lower 32-bits of MSR value.\r
1908 @param EDX Upper 32-bits of MSR value.\r
1909\r
1910 <b>Example usage</b>\r
1911 @code\r
1912 UINT64 Msr;\r
1913\r
1914 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);\r
1915 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);\r
1916 @endcode\r
a73ab083 1917 @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r
c67b579c
MK		 1918**/\r
1919#define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733\r
1920\r
1921\r
1922/**\r
1923 Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.\r
1924\r
1925 @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)\r
1926 @param EAX Lower 32-bits of MSR value.\r
1927 @param EDX Upper 32-bits of MSR value.\r
1928\r
1929 <b>Example usage</b>\r
1930 @code\r
1931 UINT64 Msr;\r
1932\r
1933 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);\r
1934 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);\r
1935 @endcode\r
a73ab083 1936 @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 1937**/\r
1938#define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734\r
1939\r
1940\r
1941/**\r
1942 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.\r
1943\r
1944 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)\r
1945 @param EAX Lower 32-bits of MSR value.\r
1946 @param EDX Upper 32-bits of MSR value.\r
1947\r
1948 <b>Example usage</b>\r
1949 @code\r
1950 UINT64 Msr;\r
1951\r
1952 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);\r
1953 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);\r
1954 @endcode\r
a73ab083 1955 @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 1956**/\r
1957#define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735\r
1958\r
1959\r
1960/**\r
1961 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.\r
1962\r
1963 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)\r
1964 @param EAX Lower 32-bits of MSR value.\r
1965 @param EDX Upper 32-bits of MSR value.\r
1966\r
1967 <b>Example usage</b>\r
1968 @code\r
1969 UINT64 Msr;\r
1970\r
1971 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);\r
1972 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);\r
1973 @endcode\r
a73ab083 1974 @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 1975**/\r
1976#define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736\r
1977\r
1978\r
1979/**\r
1980 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.\r
1981\r
1982 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)\r
1983 @param EAX Lower 32-bits of MSR value.\r
1984 @param EDX Upper 32-bits of MSR value.\r
1985\r
1986 <b>Example usage</b>\r
1987 @code\r
1988 UINT64 Msr;\r
1989\r
1990 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);\r
1991 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);\r
1992 @endcode\r
a73ab083 1993 @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 1994**/\r
1995#define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737\r
1996\r
1997\r
1998/**\r
1999 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.\r
2000\r
2001 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)\r
2002 @param EAX Lower 32-bits of MSR value.\r
2003 @param EDX Upper 32-bits of MSR value.\r
2004\r
2005 <b>Example usage</b>\r
2006 @code\r
2007 UINT64 Msr;\r
2008\r
2009 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);\r
2010 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);\r
2011 @endcode\r
a73ab083 2012 @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 2013**/\r
2014#define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738\r
2015\r
2016\r
2017/**\r
2018 Package. Uncore SBo 2 perfmon box-wide filter.\r
2019\r
2020 @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)\r
2021 @param EAX Lower 32-bits of MSR value.\r
2022 @param EDX Upper 32-bits of MSR value.\r
2023\r
2024 <b>Example usage</b>\r
2025 @code\r
2026 UINT64 Msr;\r
2027\r
2028 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);\r
2029 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);\r
2030 @endcode\r
a73ab083 2031 @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.\r
c67b579c
MK		 2032**/\r
2033#define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739\r
2034\r
2035\r
2036/**\r
2037 Package. Uncore SBo 2 perfmon counter 0.\r
2038\r
2039 @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)\r
2040 @param EAX Lower 32-bits of MSR value.\r
2041 @param EDX Upper 32-bits of MSR value.\r
2042\r
2043 <b>Example usage</b>\r
2044 @code\r
2045 UINT64 Msr;\r
2046\r
2047 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);\r
2048 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);\r
2049 @endcode\r
a73ab083 2050 @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.\r
c67b579c
MK		 2051**/\r
2052#define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A\r
2053\r
2054\r
2055/**\r
2056 Package. Uncore SBo 2 perfmon counter 1.\r
2057\r
2058 @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)\r
2059 @param EAX Lower 32-bits of MSR value.\r
2060 @param EDX Upper 32-bits of MSR value.\r
2061\r
2062 <b>Example usage</b>\r
2063 @code\r
2064 UINT64 Msr;\r
2065\r
2066 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);\r
2067 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);\r
2068 @endcode\r
a73ab083 2069 @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.\r
c67b579c
MK		 2070**/\r
2071#define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B\r
2072\r
2073\r
2074/**\r
2075 Package. Uncore SBo 2 perfmon counter 2.\r
2076\r
2077 @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)\r
2078 @param EAX Lower 32-bits of MSR value.\r
2079 @param EDX Upper 32-bits of MSR value.\r
2080\r
2081 <b>Example usage</b>\r
2082 @code\r
2083 UINT64 Msr;\r
2084\r
2085 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);\r
2086 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);\r
2087 @endcode\r
a73ab083 2088 @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.\r
c67b579c
MK		 2089**/\r
2090#define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C\r
2091\r
2092\r
2093/**\r
2094 Package. Uncore SBo 2 perfmon counter 3.\r
2095\r
2096 @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)\r
2097 @param EAX Lower 32-bits of MSR value.\r
2098 @param EDX Upper 32-bits of MSR value.\r
2099\r
2100 <b>Example usage</b>\r
2101 @code\r
2102 UINT64 Msr;\r
2103\r
2104 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);\r
2105 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);\r
2106 @endcode\r
a73ab083 2107 @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.\r
c67b579c
MK		 2108**/\r
2109#define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D\r
2110\r
2111\r
2112/**\r
2113 Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.\r
2114\r
2115 @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)\r
2116 @param EAX Lower 32-bits of MSR value.\r
2117 @param EDX Upper 32-bits of MSR value.\r
2118\r
2119 <b>Example usage</b>\r
2120 @code\r
2121 UINT64 Msr;\r
2122\r
2123 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);\r
2124 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);\r
2125 @endcode\r
a73ab083 2126 @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 2127**/\r
2128#define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E\r
2129\r
2130\r
2131/**\r
2132 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.\r
2133\r
2134 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)\r
2135 @param EAX Lower 32-bits of MSR value.\r
2136 @param EDX Upper 32-bits of MSR value.\r
2137\r
2138 <b>Example usage</b>\r
2139 @code\r
2140 UINT64 Msr;\r
2141\r
2142 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);\r
2143 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);\r
2144 @endcode\r
a73ab083 2145 @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 2146**/\r
2147#define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F\r
2148\r
2149\r
2150/**\r
2151 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.\r
2152\r
2153 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)\r
2154 @param EAX Lower 32-bits of MSR value.\r
2155 @param EDX Upper 32-bits of MSR value.\r
2156\r
2157 <b>Example usage</b>\r
2158 @code\r
2159 UINT64 Msr;\r
2160\r
2161 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);\r
2162 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);\r
2163 @endcode\r
a73ab083 2164 @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 2165**/\r
2166#define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740\r
2167\r
2168\r
2169/**\r
2170 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.\r
2171\r
2172 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)\r
2173 @param EAX Lower 32-bits of MSR value.\r
2174 @param EDX Upper 32-bits of MSR value.\r
2175\r
2176 <b>Example usage</b>\r
2177 @code\r
2178 UINT64 Msr;\r
2179\r
2180 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);\r
2181 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);\r
2182 @endcode\r
a73ab083 2183 @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 2184**/\r
2185#define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741\r
2186\r
2187\r
2188/**\r
2189 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.\r
2190\r
2191 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)\r
2192 @param EAX Lower 32-bits of MSR value.\r
2193 @param EDX Upper 32-bits of MSR value.\r
2194\r
2195 <b>Example usage</b>\r
2196 @code\r
2197 UINT64 Msr;\r
2198\r
2199 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);\r
2200 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);\r
2201 @endcode\r
a73ab083 2202 @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 2203**/\r
2204#define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742\r
2205\r
2206\r
2207/**\r
2208 Package. Uncore SBo 3 perfmon box-wide filter.\r
2209\r
2210 @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)\r
2211 @param EAX Lower 32-bits of MSR value.\r
2212 @param EDX Upper 32-bits of MSR value.\r
2213\r
2214 <b>Example usage</b>\r
2215 @code\r
2216 UINT64 Msr;\r
2217\r
2218 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);\r
2219 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);\r
2220 @endcode\r
a73ab083 2221 @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.\r
c67b579c
MK		 2222**/\r
2223#define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743\r
2224\r
2225\r
2226/**\r
2227 Package. Uncore SBo 3 perfmon counter 0.\r
2228\r
2229 @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)\r
2230 @param EAX Lower 32-bits of MSR value.\r
2231 @param EDX Upper 32-bits of MSR value.\r
2232\r
2233 <b>Example usage</b>\r
2234 @code\r
2235 UINT64 Msr;\r
2236\r
2237 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);\r
2238 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);\r
2239 @endcode\r
a73ab083 2240 @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.\r
c67b579c
MK		 2241**/\r
2242#define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744\r
2243\r
2244\r
2245/**\r
2246 Package. Uncore SBo 3 perfmon counter 1.\r
2247\r
2248 @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)\r
2249 @param EAX Lower 32-bits of MSR value.\r
2250 @param EDX Upper 32-bits of MSR value.\r
2251\r
2252 <b>Example usage</b>\r
2253 @code\r
2254 UINT64 Msr;\r
2255\r
2256 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);\r
2257 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);\r
2258 @endcode\r
a73ab083 2259 @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.\r
c67b579c
MK		 2260**/\r
2261#define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745\r
2262\r
2263\r
2264/**\r
2265 Package. Uncore SBo 3 perfmon counter 2.\r
2266\r
2267 @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)\r
2268 @param EAX Lower 32-bits of MSR value.\r
2269 @param EDX Upper 32-bits of MSR value.\r
2270\r
2271 <b>Example usage</b>\r
2272 @code\r
2273 UINT64 Msr;\r
2274\r
2275 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);\r
2276 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);\r
2277 @endcode\r
a73ab083 2278 @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.\r
c67b579c
MK		 2279**/\r
2280#define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746\r
2281\r
2282\r
2283/**\r
2284 Package. Uncore SBo 3 perfmon counter 3.\r
2285\r
2286 @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)\r
2287 @param EAX Lower 32-bits of MSR value.\r
2288 @param EDX Upper 32-bits of MSR value.\r
2289\r
2290 <b>Example usage</b>\r
2291 @code\r
2292 UINT64 Msr;\r
2293\r
2294 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);\r
2295 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);\r
2296 @endcode\r
a73ab083 2297 @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.\r
c67b579c
MK		 2298**/\r
2299#define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747\r
2300\r
2301\r
2302/**\r
2303 Package. Uncore C-box 0 perfmon for box-wide control.\r
2304\r
2305 @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)\r
2306 @param EAX Lower 32-bits of MSR value.\r
2307 @param EDX Upper 32-bits of MSR value.\r
2308\r
2309 <b>Example usage</b>\r
2310 @code\r
2311 UINT64 Msr;\r
2312\r
2313 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);\r
2314 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);\r
2315 @endcode\r
a73ab083 2316 @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 2317**/\r
2318#define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00\r
2319\r
2320\r
2321/**\r
2322 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r
2323\r
2324 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)\r
2325 @param EAX Lower 32-bits of MSR value.\r
2326 @param EDX Upper 32-bits of MSR value.\r
2327\r
2328 <b>Example usage</b>\r
2329 @code\r
2330 UINT64 Msr;\r
2331\r
2332 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);\r
2333 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);\r
2334 @endcode\r
a73ab083 2335 @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 2336**/\r
2337#define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01\r
2338\r
2339\r
2340/**\r
2341 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r
2342\r
2343 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)\r
2344 @param EAX Lower 32-bits of MSR value.\r
2345 @param EDX Upper 32-bits of MSR value.\r
2346\r
2347 <b>Example usage</b>\r
2348 @code\r
2349 UINT64 Msr;\r
2350\r
2351 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);\r
2352 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);\r
2353 @endcode\r
a73ab083 2354 @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 2355**/\r
2356#define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02\r
2357\r
2358\r
2359/**\r
2360 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r
2361\r
2362 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)\r
2363 @param EAX Lower 32-bits of MSR value.\r
2364 @param EDX Upper 32-bits of MSR value.\r
2365\r
2366 <b>Example usage</b>\r
2367 @code\r
2368 UINT64 Msr;\r
2369\r
2370 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);\r
2371 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);\r
2372 @endcode\r
a73ab083 2373 @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 2374**/\r
2375#define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03\r
2376\r
2377\r
2378/**\r
2379 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r
2380\r
2381 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)\r
2382 @param EAX Lower 32-bits of MSR value.\r
2383 @param EDX Upper 32-bits of MSR value.\r
2384\r
2385 <b>Example usage</b>\r
2386 @code\r
2387 UINT64 Msr;\r
2388\r
2389 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);\r
2390 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);\r
2391 @endcode\r
a73ab083 2392 @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 2393**/\r
2394#define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04\r
2395\r
2396\r
2397/**\r
2398 Package. Uncore C-box 0 perfmon box wide filter 0.\r
2399\r
2400 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)\r
2401 @param EAX Lower 32-bits of MSR value.\r
2402 @param EDX Upper 32-bits of MSR value.\r
2403\r
2404 <b>Example usage</b>\r
2405 @code\r
2406 UINT64 Msr;\r
2407\r
2408 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);\r
2409 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);\r
2410 @endcode\r
a73ab083 2411 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 2412**/\r
2413#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05\r
2414\r
2415\r
2416/**\r
2417 Package. Uncore C-box 0 perfmon box wide filter 1.\r
2418\r
2419 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)\r
2420 @param EAX Lower 32-bits of MSR value.\r
2421 @param EDX Upper 32-bits of MSR value.\r
2422\r
2423 <b>Example usage</b>\r
2424 @code\r
2425 UINT64 Msr;\r
2426\r
2427 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);\r
2428 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);\r
2429 @endcode\r
a73ab083 2430 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 2431**/\r
2432#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06\r
2433\r
2434\r
2435/**\r
2436 Package. Uncore C-box 0 perfmon box wide status.\r
2437\r
2438 @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)\r
2439 @param EAX Lower 32-bits of MSR value.\r
2440 @param EDX Upper 32-bits of MSR value.\r
2441\r
2442 <b>Example usage</b>\r
2443 @code\r
2444 UINT64 Msr;\r
2445\r
2446 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);\r
2447 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);\r
2448 @endcode\r
a73ab083 2449 @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 2450**/\r
2451#define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07\r
2452\r
2453\r
2454/**\r
2455 Package. Uncore C-box 0 perfmon counter 0.\r
2456\r
2457 @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)\r
2458 @param EAX Lower 32-bits of MSR value.\r
2459 @param EDX Upper 32-bits of MSR value.\r
2460\r
2461 <b>Example usage</b>\r
2462 @code\r
2463 UINT64 Msr;\r
2464\r
2465 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);\r
2466 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);\r
2467 @endcode\r
a73ab083 2468 @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
c67b579c
MK		 2469**/\r
2470#define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08\r
2471\r
2472\r
2473/**\r
2474 Package. Uncore C-box 0 perfmon counter 1.\r
2475\r
2476 @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)\r
2477 @param EAX Lower 32-bits of MSR value.\r
2478 @param EDX Upper 32-bits of MSR value.\r
2479\r
2480 <b>Example usage</b>\r
2481 @code\r
2482 UINT64 Msr;\r
2483\r
2484 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);\r
2485 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);\r
2486 @endcode\r
a73ab083 2487 @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
c67b579c
MK		 2488**/\r
2489#define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09\r
2490\r
2491\r
2492/**\r
2493 Package. Uncore C-box 0 perfmon counter 2.\r
2494\r
2495 @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)\r
2496 @param EAX Lower 32-bits of MSR value.\r
2497 @param EDX Upper 32-bits of MSR value.\r
2498\r
2499 <b>Example usage</b>\r
2500 @code\r
2501 UINT64 Msr;\r
2502\r
2503 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);\r
2504 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);\r
2505 @endcode\r
a73ab083 2506 @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
c67b579c
MK		 2507**/\r
2508#define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A\r
2509\r
2510\r
2511/**\r
2512 Package. Uncore C-box 0 perfmon counter 3.\r
2513\r
2514 @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)\r
2515 @param EAX Lower 32-bits of MSR value.\r
2516 @param EDX Upper 32-bits of MSR value.\r
2517\r
2518 <b>Example usage</b>\r
2519 @code\r
2520 UINT64 Msr;\r
2521\r
2522 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);\r
2523 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);\r
2524 @endcode\r
a73ab083 2525 @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
c67b579c
MK		 2526**/\r
2527#define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B\r
2528\r
2529\r
2530/**\r
2531 Package. Uncore C-box 1 perfmon for box-wide control.\r
2532\r
2533 @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)\r
2534 @param EAX Lower 32-bits of MSR value.\r
2535 @param EDX Upper 32-bits of MSR value.\r
2536\r
2537 <b>Example usage</b>\r
2538 @code\r
2539 UINT64 Msr;\r
2540\r
2541 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);\r
2542 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);\r
2543 @endcode\r
a73ab083 2544 @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 2545**/\r
2546#define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10\r
2547\r
2548\r
2549/**\r
2550 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r
2551\r
2552 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)\r
2553 @param EAX Lower 32-bits of MSR value.\r
2554 @param EDX Upper 32-bits of MSR value.\r
2555\r
2556 <b>Example usage</b>\r
2557 @code\r
2558 UINT64 Msr;\r
2559\r
2560 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);\r
2561 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);\r
2562 @endcode\r
a73ab083 2563 @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 2564**/\r
2565#define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11\r
2566\r
2567\r
2568/**\r
2569 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r
2570\r
2571 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)\r
2572 @param EAX Lower 32-bits of MSR value.\r
2573 @param EDX Upper 32-bits of MSR value.\r
2574\r
2575 <b>Example usage</b>\r
2576 @code\r
2577 UINT64 Msr;\r
2578\r
2579 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);\r
2580 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);\r
2581 @endcode\r
a73ab083 2582 @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 2583**/\r
2584#define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12\r
2585\r
2586\r
2587/**\r
2588 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r
2589\r
2590 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)\r
2591 @param EAX Lower 32-bits of MSR value.\r
2592 @param EDX Upper 32-bits of MSR value.\r
2593\r
2594 <b>Example usage</b>\r
2595 @code\r
2596 UINT64 Msr;\r
2597\r
2598 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);\r
2599 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);\r
2600 @endcode\r
a73ab083 2601 @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 2602**/\r
2603#define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13\r
2604\r
2605\r
2606/**\r
2607 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r
2608\r
2609 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)\r
2610 @param EAX Lower 32-bits of MSR value.\r
2611 @param EDX Upper 32-bits of MSR value.\r
2612\r
2613 <b>Example usage</b>\r
2614 @code\r
2615 UINT64 Msr;\r
2616\r
2617 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);\r
2618 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);\r
2619 @endcode\r
a73ab083 2620 @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 2621**/\r
2622#define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14\r
2623\r
2624\r
2625/**\r
2626 Package. Uncore C-box 1 perfmon box wide filter 0.\r
2627\r
2628 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)\r
2629 @param EAX Lower 32-bits of MSR value.\r
2630 @param EDX Upper 32-bits of MSR value.\r
2631\r
2632 <b>Example usage</b>\r
2633 @code\r
2634 UINT64 Msr;\r
2635\r
2636 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);\r
2637 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);\r
2638 @endcode\r
a73ab083 2639 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 2640**/\r
2641#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15\r
2642\r
2643\r
2644/**\r
2645 Package. Uncore C-box 1 perfmon box wide filter1.\r
2646\r
2647 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)\r
2648 @param EAX Lower 32-bits of MSR value.\r
2649 @param EDX Upper 32-bits of MSR value.\r
2650\r
2651 <b>Example usage</b>\r
2652 @code\r
2653 UINT64 Msr;\r
2654\r
2655 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);\r
2656 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);\r
2657 @endcode\r
a73ab083 2658 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 2659**/\r
2660#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16\r
2661\r
2662\r
2663/**\r
2664 Package. Uncore C-box 1 perfmon box wide status.\r
2665\r
2666 @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)\r
2667 @param EAX Lower 32-bits of MSR value.\r
2668 @param EDX Upper 32-bits of MSR value.\r
2669\r
2670 <b>Example usage</b>\r
2671 @code\r
2672 UINT64 Msr;\r
2673\r
2674 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);\r
2675 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);\r
2676 @endcode\r
a73ab083 2677 @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 2678**/\r
2679#define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17\r
2680\r
2681\r
2682/**\r
2683 Package. Uncore C-box 1 perfmon counter 0.\r
2684\r
2685 @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)\r
2686 @param EAX Lower 32-bits of MSR value.\r
2687 @param EDX Upper 32-bits of MSR value.\r
2688\r
2689 <b>Example usage</b>\r
2690 @code\r
2691 UINT64 Msr;\r
2692\r
2693 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);\r
2694 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);\r
2695 @endcode\r
a73ab083 2696 @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
c67b579c
MK		 2697**/\r
2698#define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18\r
2699\r
2700\r
2701/**\r
2702 Package. Uncore C-box 1 perfmon counter 1.\r
2703\r
2704 @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)\r
2705 @param EAX Lower 32-bits of MSR value.\r
2706 @param EDX Upper 32-bits of MSR value.\r
2707\r
2708 <b>Example usage</b>\r
2709 @code\r
2710 UINT64 Msr;\r
2711\r
2712 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);\r
2713 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);\r
2714 @endcode\r
a73ab083 2715 @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
c67b579c
MK		 2716**/\r
2717#define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19\r
2718\r
2719\r
2720/**\r
2721 Package. Uncore C-box 1 perfmon counter 2.\r
2722\r
2723 @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)\r
2724 @param EAX Lower 32-bits of MSR value.\r
2725 @param EDX Upper 32-bits of MSR value.\r
2726\r
2727 <b>Example usage</b>\r
2728 @code\r
2729 UINT64 Msr;\r
2730\r
2731 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);\r
2732 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);\r
2733 @endcode\r
a73ab083 2734 @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
c67b579c
MK		 2735**/\r
2736#define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A\r
2737\r
2738\r
2739/**\r
2740 Package. Uncore C-box 1 perfmon counter 3.\r
2741\r
2742 @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)\r
2743 @param EAX Lower 32-bits of MSR value.\r
2744 @param EDX Upper 32-bits of MSR value.\r
2745\r
2746 <b>Example usage</b>\r
2747 @code\r
2748 UINT64 Msr;\r
2749\r
2750 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);\r
2751 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);\r
2752 @endcode\r
a73ab083 2753 @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
c67b579c
MK		 2754**/\r
2755#define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B\r
2756\r
2757\r
2758/**\r
2759 Package. Uncore C-box 2 perfmon for box-wide control.\r
2760\r
2761 @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)\r
2762 @param EAX Lower 32-bits of MSR value.\r
2763 @param EDX Upper 32-bits of MSR value.\r
2764\r
2765 <b>Example usage</b>\r
2766 @code\r
2767 UINT64 Msr;\r
2768\r
2769 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);\r
2770 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);\r
2771 @endcode\r
a73ab083 2772 @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 2773**/\r
2774#define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20\r
2775\r
2776\r
2777/**\r
2778 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r
2779\r
2780 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)\r
2781 @param EAX Lower 32-bits of MSR value.\r
2782 @param EDX Upper 32-bits of MSR value.\r
2783\r
2784 <b>Example usage</b>\r
2785 @code\r
2786 UINT64 Msr;\r
2787\r
2788 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);\r
2789 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);\r
2790 @endcode\r
a73ab083 2791 @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 2792**/\r
2793#define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21\r
2794\r
2795\r
2796/**\r
2797 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r
2798\r
2799 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)\r
2800 @param EAX Lower 32-bits of MSR value.\r
2801 @param EDX Upper 32-bits of MSR value.\r
2802\r
2803 <b>Example usage</b>\r
2804 @code\r
2805 UINT64 Msr;\r
2806\r
2807 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);\r
2808 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);\r
2809 @endcode\r
a73ab083 2810 @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 2811**/\r
2812#define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22\r
2813\r
2814\r
2815/**\r
2816 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r
2817\r
2818 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)\r
2819 @param EAX Lower 32-bits of MSR value.\r
2820 @param EDX Upper 32-bits of MSR value.\r
2821\r
2822 <b>Example usage</b>\r
2823 @code\r
2824 UINT64 Msr;\r
2825\r
2826 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);\r
2827 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);\r
2828 @endcode\r
a73ab083 2829 @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 2830**/\r
2831#define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23\r
2832\r
2833\r
2834/**\r
2835 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r
2836\r
2837 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)\r
2838 @param EAX Lower 32-bits of MSR value.\r
2839 @param EDX Upper 32-bits of MSR value.\r
2840\r
2841 <b>Example usage</b>\r
2842 @code\r
2843 UINT64 Msr;\r
2844\r
2845 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);\r
2846 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);\r
2847 @endcode\r
a73ab083 2848 @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 2849**/\r
2850#define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24\r
2851\r
2852\r
2853/**\r
2854 Package. Uncore C-box 2 perfmon box wide filter 0.\r
2855\r
2856 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)\r
2857 @param EAX Lower 32-bits of MSR value.\r
2858 @param EDX Upper 32-bits of MSR value.\r
2859\r
2860 <b>Example usage</b>\r
2861 @code\r
2862 UINT64 Msr;\r
2863\r
2864 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);\r
2865 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);\r
2866 @endcode\r
a73ab083 2867 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 2868**/\r
2869#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25\r
2870\r
2871\r
2872/**\r
2873 Package. Uncore C-box 2 perfmon box wide filter1.\r
2874\r
2875 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)\r
2876 @param EAX Lower 32-bits of MSR value.\r
2877 @param EDX Upper 32-bits of MSR value.\r
2878\r
2879 <b>Example usage</b>\r
2880 @code\r
2881 UINT64 Msr;\r
2882\r
2883 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);\r
2884 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);\r
2885 @endcode\r
a73ab083 2886 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 2887**/\r
2888#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26\r
2889\r
2890\r
2891/**\r
2892 Package. Uncore C-box 2 perfmon box wide status.\r
2893\r
2894 @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)\r
2895 @param EAX Lower 32-bits of MSR value.\r
2896 @param EDX Upper 32-bits of MSR value.\r
2897\r
2898 <b>Example usage</b>\r
2899 @code\r
2900 UINT64 Msr;\r
2901\r
2902 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);\r
2903 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);\r
2904 @endcode\r
a73ab083 2905 @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 2906**/\r
2907#define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27\r
2908\r
2909\r
2910/**\r
2911 Package. Uncore C-box 2 perfmon counter 0.\r
2912\r
2913 @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)\r
2914 @param EAX Lower 32-bits of MSR value.\r
2915 @param EDX Upper 32-bits of MSR value.\r
2916\r
2917 <b>Example usage</b>\r
2918 @code\r
2919 UINT64 Msr;\r
2920\r
2921 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);\r
2922 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);\r
2923 @endcode\r
a73ab083 2924 @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
c67b579c
MK		 2925**/\r
2926#define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28\r
2927\r
2928\r
2929/**\r
2930 Package. Uncore C-box 2 perfmon counter 1.\r
2931\r
2932 @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)\r
2933 @param EAX Lower 32-bits of MSR value.\r
2934 @param EDX Upper 32-bits of MSR value.\r
2935\r
2936 <b>Example usage</b>\r
2937 @code\r
2938 UINT64 Msr;\r
2939\r
2940 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);\r
2941 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);\r
2942 @endcode\r
a73ab083 2943 @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
c67b579c
MK		 2944**/\r
2945#define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29\r
2946\r
2947\r
2948/**\r
2949 Package. Uncore C-box 2 perfmon counter 2.\r
2950\r
2951 @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)\r
2952 @param EAX Lower 32-bits of MSR value.\r
2953 @param EDX Upper 32-bits of MSR value.\r
2954\r
2955 <b>Example usage</b>\r
2956 @code\r
2957 UINT64 Msr;\r
2958\r
2959 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);\r
2960 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);\r
2961 @endcode\r
a73ab083 2962 @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
c67b579c
MK		 2963**/\r
2964#define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A\r
2965\r
2966\r
2967/**\r
2968 Package. Uncore C-box 2 perfmon counter 3.\r
2969\r
2970 @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)\r
2971 @param EAX Lower 32-bits of MSR value.\r
2972 @param EDX Upper 32-bits of MSR value.\r
2973\r
2974 <b>Example usage</b>\r
2975 @code\r
2976 UINT64 Msr;\r
2977\r
2978 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);\r
2979 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);\r
2980 @endcode\r
a73ab083 2981 @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
c67b579c
MK		 2982**/\r
2983#define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B\r
2984\r
2985\r
2986/**\r
2987 Package. Uncore C-box 3 perfmon for box-wide control.\r
2988\r
2989 @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)\r
2990 @param EAX Lower 32-bits of MSR value.\r
2991 @param EDX Upper 32-bits of MSR value.\r
2992\r
2993 <b>Example usage</b>\r
2994 @code\r
2995 UINT64 Msr;\r
2996\r
2997 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);\r
2998 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);\r
2999 @endcode\r
a73ab083 3000 @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 3001**/\r
3002#define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30\r
3003\r
3004\r
3005/**\r
3006 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r
3007\r
3008 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)\r
3009 @param EAX Lower 32-bits of MSR value.\r
3010 @param EDX Upper 32-bits of MSR value.\r
3011\r
3012 <b>Example usage</b>\r
3013 @code\r
3014 UINT64 Msr;\r
3015\r
3016 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);\r
3017 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);\r
3018 @endcode\r
a73ab083 3019 @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 3020**/\r
3021#define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31\r
3022\r
3023\r
3024/**\r
3025 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r
3026\r
3027 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)\r
3028 @param EAX Lower 32-bits of MSR value.\r
3029 @param EDX Upper 32-bits of MSR value.\r
3030\r
3031 <b>Example usage</b>\r
3032 @code\r
3033 UINT64 Msr;\r
3034\r
3035 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);\r
3036 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);\r
3037 @endcode\r
a73ab083 3038 @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 3039**/\r
3040#define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32\r
3041\r
3042\r
3043/**\r
3044 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r
3045\r
3046 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)\r
3047 @param EAX Lower 32-bits of MSR value.\r
3048 @param EDX Upper 32-bits of MSR value.\r
3049\r
3050 <b>Example usage</b>\r
3051 @code\r
3052 UINT64 Msr;\r
3053\r
3054 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);\r
3055 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);\r
3056 @endcode\r
a73ab083 3057 @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 3058**/\r
3059#define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33\r
3060\r
3061\r
3062/**\r
3063 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r
3064\r
3065 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)\r
3066 @param EAX Lower 32-bits of MSR value.\r
3067 @param EDX Upper 32-bits of MSR value.\r
3068\r
3069 <b>Example usage</b>\r
3070 @code\r
3071 UINT64 Msr;\r
3072\r
3073 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);\r
3074 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);\r
3075 @endcode\r
a73ab083 3076 @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 3077**/\r
3078#define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34\r
3079\r
3080\r
3081/**\r
3082 Package. Uncore C-box 3 perfmon box wide filter 0.\r
3083\r
3084 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)\r
3085 @param EAX Lower 32-bits of MSR value.\r
3086 @param EDX Upper 32-bits of MSR value.\r
3087\r
3088 <b>Example usage</b>\r
3089 @code\r
3090 UINT64 Msr;\r
3091\r
3092 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);\r
3093 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);\r
3094 @endcode\r
a73ab083 3095 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 3096**/\r
3097#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35\r
3098\r
3099\r
3100/**\r
3101 Package. Uncore C-box 3 perfmon box wide filter1.\r
3102\r
3103 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)\r
3104 @param EAX Lower 32-bits of MSR value.\r
3105 @param EDX Upper 32-bits of MSR value.\r
3106\r
3107 <b>Example usage</b>\r
3108 @code\r
3109 UINT64 Msr;\r
3110\r
3111 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);\r
3112 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);\r
3113 @endcode\r
a73ab083 3114 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 3115**/\r
3116#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36\r
3117\r
3118\r
3119/**\r
3120 Package. Uncore C-box 3 perfmon box wide status.\r
3121\r
3122 @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)\r
3123 @param EAX Lower 32-bits of MSR value.\r
3124 @param EDX Upper 32-bits of MSR value.\r
3125\r
3126 <b>Example usage</b>\r
3127 @code\r
3128 UINT64 Msr;\r
3129\r
3130 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);\r
3131 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);\r
3132 @endcode\r
a73ab083 3133 @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 3134**/\r
3135#define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37\r
3136\r
3137\r
3138/**\r
3139 Package. Uncore C-box 3 perfmon counter 0.\r
3140\r
3141 @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)\r
3142 @param EAX Lower 32-bits of MSR value.\r
3143 @param EDX Upper 32-bits of MSR value.\r
3144\r
3145 <b>Example usage</b>\r
3146 @code\r
3147 UINT64 Msr;\r
3148\r
3149 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);\r
3150 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);\r
3151 @endcode\r
a73ab083 3152 @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
c67b579c
MK		 3153**/\r
3154#define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38\r
3155\r
3156\r
3157/**\r
3158 Package. Uncore C-box 3 perfmon counter 1.\r
3159\r
3160 @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)\r
3161 @param EAX Lower 32-bits of MSR value.\r
3162 @param EDX Upper 32-bits of MSR value.\r
3163\r
3164 <b>Example usage</b>\r
3165 @code\r
3166 UINT64 Msr;\r
3167\r
3168 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);\r
3169 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);\r
3170 @endcode\r
a73ab083 3171 @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
c67b579c
MK		 3172**/\r
3173#define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39\r
3174\r
3175\r
3176/**\r
3177 Package. Uncore C-box 3 perfmon counter 2.\r
3178\r
3179 @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)\r
3180 @param EAX Lower 32-bits of MSR value.\r
3181 @param EDX Upper 32-bits of MSR value.\r
3182\r
3183 <b>Example usage</b>\r
3184 @code\r
3185 UINT64 Msr;\r
3186\r
3187 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);\r
3188 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);\r
3189 @endcode\r
a73ab083 3190 @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
c67b579c
MK		 3191**/\r
3192#define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A\r
3193\r
3194\r
3195/**\r
3196 Package. Uncore C-box 3 perfmon counter 3.\r
3197\r
3198 @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)\r
3199 @param EAX Lower 32-bits of MSR value.\r
3200 @param EDX Upper 32-bits of MSR value.\r
3201\r
3202 <b>Example usage</b>\r
3203 @code\r
3204 UINT64 Msr;\r
3205\r
3206 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);\r
3207 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);\r
3208 @endcode\r
a73ab083 3209 @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
c67b579c
MK		 3210**/\r
3211#define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B\r
3212\r
3213\r
3214/**\r
3215 Package. Uncore C-box 4 perfmon for box-wide control.\r
3216\r
3217 @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)\r
3218 @param EAX Lower 32-bits of MSR value.\r
3219 @param EDX Upper 32-bits of MSR value.\r
3220\r
3221 <b>Example usage</b>\r
3222 @code\r
3223 UINT64 Msr;\r
3224\r
3225 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);\r
3226 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);\r
3227 @endcode\r
a73ab083 3228 @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 3229**/\r
3230#define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40\r
3231\r
3232\r
3233/**\r
3234 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r
3235\r
3236 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)\r
3237 @param EAX Lower 32-bits of MSR value.\r
3238 @param EDX Upper 32-bits of MSR value.\r
3239\r
3240 <b>Example usage</b>\r
3241 @code\r
3242 UINT64 Msr;\r
3243\r
3244 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);\r
3245 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);\r
3246 @endcode\r
a73ab083 3247 @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 3248**/\r
3249#define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41\r
3250\r
3251\r
3252/**\r
3253 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r
3254\r
3255 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)\r
3256 @param EAX Lower 32-bits of MSR value.\r
3257 @param EDX Upper 32-bits of MSR value.\r
3258\r
3259 <b>Example usage</b>\r
3260 @code\r
3261 UINT64 Msr;\r
3262\r
3263 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);\r
3264 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);\r
3265 @endcode\r
a73ab083 3266 @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 3267**/\r
3268#define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42\r
3269\r
3270\r
3271/**\r
3272 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r
3273\r
3274 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)\r
3275 @param EAX Lower 32-bits of MSR value.\r
3276 @param EDX Upper 32-bits of MSR value.\r
3277\r
3278 <b>Example usage</b>\r
3279 @code\r
3280 UINT64 Msr;\r
3281\r
3282 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);\r
3283 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);\r
3284 @endcode\r
a73ab083 3285 @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 3286**/\r
3287#define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43\r
3288\r
3289\r
3290/**\r
3291 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r
3292\r
3293 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)\r
3294 @param EAX Lower 32-bits of MSR value.\r
3295 @param EDX Upper 32-bits of MSR value.\r
3296\r
3297 <b>Example usage</b>\r
3298 @code\r
3299 UINT64 Msr;\r
3300\r
3301 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);\r
3302 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);\r
3303 @endcode\r
a73ab083 3304 @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 3305**/\r
3306#define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44\r
3307\r
3308\r
3309/**\r
3310 Package. Uncore C-box 4 perfmon box wide filter 0.\r
3311\r
3312 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)\r
3313 @param EAX Lower 32-bits of MSR value.\r
3314 @param EDX Upper 32-bits of MSR value.\r
3315\r
3316 <b>Example usage</b>\r
3317 @code\r
3318 UINT64 Msr;\r
3319\r
3320 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);\r
3321 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);\r
3322 @endcode\r
a73ab083 3323 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 3324**/\r
3325#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45\r
3326\r
3327\r
3328/**\r
3329 Package. Uncore C-box 4 perfmon box wide filter1.\r
3330\r
3331 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)\r
3332 @param EAX Lower 32-bits of MSR value.\r
3333 @param EDX Upper 32-bits of MSR value.\r
3334\r
3335 <b>Example usage</b>\r
3336 @code\r
3337 UINT64 Msr;\r
3338\r
3339 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);\r
3340 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);\r
3341 @endcode\r
a73ab083 3342 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 3343**/\r
3344#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46\r
3345\r
3346\r
3347/**\r
3348 Package. Uncore C-box 4 perfmon box wide status.\r
3349\r
3350 @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)\r
3351 @param EAX Lower 32-bits of MSR value.\r
3352 @param EDX Upper 32-bits of MSR value.\r
3353\r
3354 <b>Example usage</b>\r
3355 @code\r
3356 UINT64 Msr;\r
3357\r
3358 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);\r
3359 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);\r
3360 @endcode\r
a73ab083 3361 @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 3362**/\r
3363#define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47\r
3364\r
3365\r
3366/**\r
3367 Package. Uncore C-box 4 perfmon counter 0.\r
3368\r
3369 @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)\r
3370 @param EAX Lower 32-bits of MSR value.\r
3371 @param EDX Upper 32-bits of MSR value.\r
3372\r
3373 <b>Example usage</b>\r
3374 @code\r
3375 UINT64 Msr;\r
3376\r
3377 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);\r
3378 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);\r
3379 @endcode\r
a73ab083 3380 @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
c67b579c
MK		 3381**/\r
3382#define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48\r
3383\r
3384\r
3385/**\r
3386 Package. Uncore C-box 4 perfmon counter 1.\r
3387\r
3388 @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)\r
3389 @param EAX Lower 32-bits of MSR value.\r
3390 @param EDX Upper 32-bits of MSR value.\r
3391\r
3392 <b>Example usage</b>\r
3393 @code\r
3394 UINT64 Msr;\r
3395\r
3396 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);\r
3397 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);\r
3398 @endcode\r
a73ab083 3399 @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
c67b579c
MK		 3400**/\r
3401#define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49\r
3402\r
3403\r
3404/**\r
3405 Package. Uncore C-box 4 perfmon counter 2.\r
3406\r
3407 @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)\r
3408 @param EAX Lower 32-bits of MSR value.\r
3409 @param EDX Upper 32-bits of MSR value.\r
3410\r
3411 <b>Example usage</b>\r
3412 @code\r
3413 UINT64 Msr;\r
3414\r
3415 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);\r
3416 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);\r
3417 @endcode\r
a73ab083 3418 @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
c67b579c
MK		 3419**/\r
3420#define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A\r
3421\r
3422\r
3423/**\r
3424 Package. Uncore C-box 4 perfmon counter 3.\r
3425\r
3426 @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)\r
3427 @param EAX Lower 32-bits of MSR value.\r
3428 @param EDX Upper 32-bits of MSR value.\r
3429\r
3430 <b>Example usage</b>\r
3431 @code\r
3432 UINT64 Msr;\r
3433\r
3434 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);\r
3435 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);\r
3436 @endcode\r
a73ab083 3437 @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
c67b579c
MK		 3438**/\r
3439#define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B\r
3440\r
3441\r
3442/**\r
3443 Package. Uncore C-box 5 perfmon for box-wide control.\r
3444\r
3445 @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)\r
3446 @param EAX Lower 32-bits of MSR value.\r
3447 @param EDX Upper 32-bits of MSR value.\r
3448\r
3449 <b>Example usage</b>\r
3450 @code\r
3451 UINT64 Msr;\r
3452\r
3453 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);\r
3454 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);\r
3455 @endcode\r
a73ab083 3456 @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 3457**/\r
3458#define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50\r
3459\r
3460\r
3461/**\r
3462 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r
3463\r
3464 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)\r
3465 @param EAX Lower 32-bits of MSR value.\r
3466 @param EDX Upper 32-bits of MSR value.\r
3467\r
3468 <b>Example usage</b>\r
3469 @code\r
3470 UINT64 Msr;\r
3471\r
3472 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);\r
3473 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);\r
3474 @endcode\r
a73ab083 3475 @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 3476**/\r
3477#define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51\r
3478\r
3479\r
3480/**\r
3481 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r
3482\r
3483 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)\r
3484 @param EAX Lower 32-bits of MSR value.\r
3485 @param EDX Upper 32-bits of MSR value.\r
3486\r
3487 <b>Example usage</b>\r
3488 @code\r
3489 UINT64 Msr;\r
3490\r
3491 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);\r
3492 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);\r
3493 @endcode\r
a73ab083 3494 @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 3495**/\r
3496#define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52\r
3497\r
3498\r
3499/**\r
3500 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r
3501\r
3502 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)\r
3503 @param EAX Lower 32-bits of MSR value.\r
3504 @param EDX Upper 32-bits of MSR value.\r
3505\r
3506 <b>Example usage</b>\r
3507 @code\r
3508 UINT64 Msr;\r
3509\r
3510 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);\r
3511 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);\r
3512 @endcode\r
a73ab083 3513 @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 3514**/\r
3515#define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53\r
3516\r
3517\r
3518/**\r
3519 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r
3520\r
3521 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)\r
3522 @param EAX Lower 32-bits of MSR value.\r
3523 @param EDX Upper 32-bits of MSR value.\r
3524\r
3525 <b>Example usage</b>\r
3526 @code\r
3527 UINT64 Msr;\r
3528\r
3529 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);\r
3530 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);\r
3531 @endcode\r
a73ab083 3532 @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 3533**/\r
3534#define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54\r
3535\r
3536\r
3537/**\r
3538 Package. Uncore C-box 5 perfmon box wide filter 0.\r
3539\r
3540 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)\r
3541 @param EAX Lower 32-bits of MSR value.\r
3542 @param EDX Upper 32-bits of MSR value.\r
3543\r
3544 <b>Example usage</b>\r
3545 @code\r
3546 UINT64 Msr;\r
3547\r
3548 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);\r
3549 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);\r
3550 @endcode\r
a73ab083 3551 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 3552**/\r
3553#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55\r
3554\r
3555\r
3556/**\r
3557 Package. Uncore C-box 5 perfmon box wide filter1.\r
3558\r
3559 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)\r
3560 @param EAX Lower 32-bits of MSR value.\r
3561 @param EDX Upper 32-bits of MSR value.\r
3562\r
3563 <b>Example usage</b>\r
3564 @code\r
3565 UINT64 Msr;\r
3566\r
3567 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);\r
3568 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);\r
3569 @endcode\r
a73ab083 3570 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 3571**/\r
3572#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56\r
3573\r
3574\r
3575/**\r
3576 Package. Uncore C-box 5 perfmon box wide status.\r
3577\r
3578 @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)\r
3579 @param EAX Lower 32-bits of MSR value.\r
3580 @param EDX Upper 32-bits of MSR value.\r
3581\r
3582 <b>Example usage</b>\r
3583 @code\r
3584 UINT64 Msr;\r
3585\r
3586 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);\r
3587 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);\r
3588 @endcode\r
a73ab083 3589 @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 3590**/\r
3591#define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57\r
3592\r
3593\r
3594/**\r
3595 Package. Uncore C-box 5 perfmon counter 0.\r
3596\r
3597 @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)\r
3598 @param EAX Lower 32-bits of MSR value.\r
3599 @param EDX Upper 32-bits of MSR value.\r
3600\r
3601 <b>Example usage</b>\r
3602 @code\r
3603 UINT64 Msr;\r
3604\r
3605 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);\r
3606 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);\r
3607 @endcode\r
a73ab083 3608 @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
c67b579c
MK		 3609**/\r
3610#define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58\r
3611\r
3612\r
3613/**\r
3614 Package. Uncore C-box 5 perfmon counter 1.\r
3615\r
3616 @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)\r
3617 @param EAX Lower 32-bits of MSR value.\r
3618 @param EDX Upper 32-bits of MSR value.\r
3619\r
3620 <b>Example usage</b>\r
3621 @code\r
3622 UINT64 Msr;\r
3623\r
3624 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);\r
3625 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);\r
3626 @endcode\r
a73ab083 3627 @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
c67b579c
MK		 3628**/\r
3629#define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59\r
3630\r
3631\r
3632/**\r
3633 Package. Uncore C-box 5 perfmon counter 2.\r
3634\r
3635 @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)\r
3636 @param EAX Lower 32-bits of MSR value.\r
3637 @param EDX Upper 32-bits of MSR value.\r
3638\r
3639 <b>Example usage</b>\r
3640 @code\r
3641 UINT64 Msr;\r
3642\r
3643 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);\r
3644 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);\r
3645 @endcode\r
a73ab083 3646 @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
c67b579c
MK		 3647**/\r
3648#define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A\r
3649\r
3650\r
3651/**\r
3652 Package. Uncore C-box 5 perfmon counter 3.\r
3653\r
3654 @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)\r
3655 @param EAX Lower 32-bits of MSR value.\r
3656 @param EDX Upper 32-bits of MSR value.\r
3657\r
3658 <b>Example usage</b>\r
3659 @code\r
3660 UINT64 Msr;\r
3661\r
3662 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);\r
3663 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);\r
3664 @endcode\r
a73ab083 3665 @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
c67b579c
MK		 3666**/\r
3667#define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B\r
3668\r
3669\r
3670/**\r
3671 Package. Uncore C-box 6 perfmon for box-wide control.\r
3672\r
3673 @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)\r
3674 @param EAX Lower 32-bits of MSR value.\r
3675 @param EDX Upper 32-bits of MSR value.\r
3676\r
3677 <b>Example usage</b>\r
3678 @code\r
3679 UINT64 Msr;\r
3680\r
3681 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);\r
3682 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);\r
3683 @endcode\r
a73ab083 3684 @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 3685**/\r
3686#define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60\r
3687\r
3688\r
3689/**\r
3690 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r
3691\r
3692 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)\r
3693 @param EAX Lower 32-bits of MSR value.\r
3694 @param EDX Upper 32-bits of MSR value.\r
3695\r
3696 <b>Example usage</b>\r
3697 @code\r
3698 UINT64 Msr;\r
3699\r
3700 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);\r
3701 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);\r
3702 @endcode\r
a73ab083 3703 @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 3704**/\r
3705#define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61\r
3706\r
3707\r
3708/**\r
3709 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r
3710\r
3711 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)\r
3712 @param EAX Lower 32-bits of MSR value.\r
3713 @param EDX Upper 32-bits of MSR value.\r
3714\r
3715 <b>Example usage</b>\r
3716 @code\r
3717 UINT64 Msr;\r
3718\r
3719 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);\r
3720 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);\r
3721 @endcode\r
a73ab083 3722 @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 3723**/\r
3724#define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62\r
3725\r
3726\r
3727/**\r
3728 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r
3729\r
3730 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)\r
3731 @param EAX Lower 32-bits of MSR value.\r
3732 @param EDX Upper 32-bits of MSR value.\r
3733\r
3734 <b>Example usage</b>\r
3735 @code\r
3736 UINT64 Msr;\r
3737\r
3738 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);\r
3739 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);\r
3740 @endcode\r
a73ab083 3741 @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 3742**/\r
3743#define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63\r
3744\r
3745\r
3746/**\r
3747 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r
3748\r
3749 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)\r
3750 @param EAX Lower 32-bits of MSR value.\r
3751 @param EDX Upper 32-bits of MSR value.\r
3752\r
3753 <b>Example usage</b>\r
3754 @code\r
3755 UINT64 Msr;\r
3756\r
3757 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);\r
3758 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);\r
3759 @endcode\r
a73ab083 3760 @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 3761**/\r
3762#define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64\r
3763\r
3764\r
3765/**\r
3766 Package. Uncore C-box 6 perfmon box wide filter 0.\r
3767\r
3768 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)\r
3769 @param EAX Lower 32-bits of MSR value.\r
3770 @param EDX Upper 32-bits of MSR value.\r
3771\r
3772 <b>Example usage</b>\r
3773 @code\r
3774 UINT64 Msr;\r
3775\r
3776 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);\r
3777 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);\r
3778 @endcode\r
a73ab083 3779 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 3780**/\r
3781#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65\r
3782\r
3783\r
3784/**\r
3785 Package. Uncore C-box 6 perfmon box wide filter1.\r
3786\r
3787 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)\r
3788 @param EAX Lower 32-bits of MSR value.\r
3789 @param EDX Upper 32-bits of MSR value.\r
3790\r
3791 <b>Example usage</b>\r
3792 @code\r
3793 UINT64 Msr;\r
3794\r
3795 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);\r
3796 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);\r
3797 @endcode\r
a73ab083 3798 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 3799**/\r
3800#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66\r
3801\r
3802\r
3803/**\r
3804 Package. Uncore C-box 6 perfmon box wide status.\r
3805\r
3806 @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)\r
3807 @param EAX Lower 32-bits of MSR value.\r
3808 @param EDX Upper 32-bits of MSR value.\r
3809\r
3810 <b>Example usage</b>\r
3811 @code\r
3812 UINT64 Msr;\r
3813\r
3814 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);\r
3815 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);\r
3816 @endcode\r
a73ab083 3817 @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 3818**/\r
3819#define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67\r
3820\r
3821\r
3822/**\r
3823 Package. Uncore C-box 6 perfmon counter 0.\r
3824\r
3825 @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)\r
3826 @param EAX Lower 32-bits of MSR value.\r
3827 @param EDX Upper 32-bits of MSR value.\r
3828\r
3829 <b>Example usage</b>\r
3830 @code\r
3831 UINT64 Msr;\r
3832\r
3833 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);\r
3834 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);\r
3835 @endcode\r
a73ab083 3836 @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
c67b579c
MK		 3837**/\r
3838#define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68\r
3839\r
3840\r
3841/**\r
3842 Package. Uncore C-box 6 perfmon counter 1.\r
3843\r
3844 @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)\r
3845 @param EAX Lower 32-bits of MSR value.\r
3846 @param EDX Upper 32-bits of MSR value.\r
3847\r
3848 <b>Example usage</b>\r
3849 @code\r
3850 UINT64 Msr;\r
3851\r
3852 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);\r
3853 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);\r
3854 @endcode\r
a73ab083 3855 @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
c67b579c
MK		 3856**/\r
3857#define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69\r
3858\r
3859\r
3860/**\r
3861 Package. Uncore C-box 6 perfmon counter 2.\r
3862\r
3863 @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)\r
3864 @param EAX Lower 32-bits of MSR value.\r
3865 @param EDX Upper 32-bits of MSR value.\r
3866\r
3867 <b>Example usage</b>\r
3868 @code\r
3869 UINT64 Msr;\r
3870\r
3871 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);\r
3872 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);\r
3873 @endcode\r
a73ab083 3874 @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
c67b579c
MK		 3875**/\r
3876#define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A\r
3877\r
3878\r
3879/**\r
3880 Package. Uncore C-box 6 perfmon counter 3.\r
3881\r
3882 @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)\r
3883 @param EAX Lower 32-bits of MSR value.\r
3884 @param EDX Upper 32-bits of MSR value.\r
3885\r
3886 <b>Example usage</b>\r
3887 @code\r
3888 UINT64 Msr;\r
3889\r
3890 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);\r
3891 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);\r
3892 @endcode\r
a73ab083 3893 @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
c67b579c
MK		 3894**/\r
3895#define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B\r
3896\r
3897\r
3898/**\r
3899 Package. Uncore C-box 7 perfmon for box-wide control.\r
3900\r
3901 @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)\r
3902 @param EAX Lower 32-bits of MSR value.\r
3903 @param EDX Upper 32-bits of MSR value.\r
3904\r
3905 <b>Example usage</b>\r
3906 @code\r
3907 UINT64 Msr;\r
3908\r
3909 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);\r
3910 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);\r
3911 @endcode\r
a73ab083 3912 @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 3913**/\r
3914#define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70\r
3915\r
3916\r
3917/**\r
3918 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r
3919\r
3920 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)\r
3921 @param EAX Lower 32-bits of MSR value.\r
3922 @param EDX Upper 32-bits of MSR value.\r
3923\r
3924 <b>Example usage</b>\r
3925 @code\r
3926 UINT64 Msr;\r
3927\r
3928 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);\r
3929 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);\r
3930 @endcode\r
a73ab083 3931 @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 3932**/\r
3933#define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71\r
3934\r
3935\r
3936/**\r
3937 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r
3938\r
3939 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)\r
3940 @param EAX Lower 32-bits of MSR value.\r
3941 @param EDX Upper 32-bits of MSR value.\r
3942\r
3943 <b>Example usage</b>\r
3944 @code\r
3945 UINT64 Msr;\r
3946\r
3947 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);\r
3948 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);\r
3949 @endcode\r
a73ab083 3950 @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 3951**/\r
3952#define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72\r
3953\r
3954\r
3955/**\r
3956 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r
3957\r
3958 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)\r
3959 @param EAX Lower 32-bits of MSR value.\r
3960 @param EDX Upper 32-bits of MSR value.\r
3961\r
3962 <b>Example usage</b>\r
3963 @code\r
3964 UINT64 Msr;\r
3965\r
3966 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);\r
3967 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);\r
3968 @endcode\r
a73ab083 3969 @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 3970**/\r
3971#define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73\r
3972\r
3973\r
3974/**\r
3975 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r
3976\r
3977 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)\r
3978 @param EAX Lower 32-bits of MSR value.\r
3979 @param EDX Upper 32-bits of MSR value.\r
3980\r
3981 <b>Example usage</b>\r
3982 @code\r
3983 UINT64 Msr;\r
3984\r
3985 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);\r
3986 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);\r
3987 @endcode\r
a73ab083 3988 @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 3989**/\r
3990#define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74\r
3991\r
3992\r
3993/**\r
3994 Package. Uncore C-box 7 perfmon box wide filter 0.\r
3995\r
3996 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)\r
3997 @param EAX Lower 32-bits of MSR value.\r
3998 @param EDX Upper 32-bits of MSR value.\r
3999\r
4000 <b>Example usage</b>\r
4001 @code\r
4002 UINT64 Msr;\r
4003\r
4004 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);\r
4005 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);\r
4006 @endcode\r
a73ab083 4007 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 4008**/\r
4009#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75\r
4010\r
4011\r
4012/**\r
4013 Package. Uncore C-box 7 perfmon box wide filter1.\r
4014\r
4015 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)\r
4016 @param EAX Lower 32-bits of MSR value.\r
4017 @param EDX Upper 32-bits of MSR value.\r
4018\r
4019 <b>Example usage</b>\r
4020 @code\r
4021 UINT64 Msr;\r
4022\r
4023 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);\r
4024 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);\r
4025 @endcode\r
a73ab083 4026 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 4027**/\r
4028#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76\r
4029\r
4030\r
4031/**\r
4032 Package. Uncore C-box 7 perfmon box wide status.\r
4033\r
4034 @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)\r
4035 @param EAX Lower 32-bits of MSR value.\r
4036 @param EDX Upper 32-bits of MSR value.\r
4037\r
4038 <b>Example usage</b>\r
4039 @code\r
4040 UINT64 Msr;\r
4041\r
4042 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);\r
4043 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);\r
4044 @endcode\r
a73ab083 4045 @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 4046**/\r
4047#define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77\r
4048\r
4049\r
4050/**\r
4051 Package. Uncore C-box 7 perfmon counter 0.\r
4052\r
4053 @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)\r
4054 @param EAX Lower 32-bits of MSR value.\r
4055 @param EDX Upper 32-bits of MSR value.\r
4056\r
4057 <b>Example usage</b>\r
4058 @code\r
4059 UINT64 Msr;\r
4060\r
4061 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);\r
4062 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);\r
4063 @endcode\r
a73ab083 4064 @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
c67b579c
MK		 4065**/\r
4066#define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78\r
4067\r
4068\r
4069/**\r
4070 Package. Uncore C-box 7 perfmon counter 1.\r
4071\r
4072 @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)\r
4073 @param EAX Lower 32-bits of MSR value.\r
4074 @param EDX Upper 32-bits of MSR value.\r
4075\r
4076 <b>Example usage</b>\r
4077 @code\r
4078 UINT64 Msr;\r
4079\r
4080 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);\r
4081 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);\r
4082 @endcode\r
a73ab083 4083 @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
c67b579c
MK		 4084**/\r
4085#define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79\r
4086\r
4087\r
4088/**\r
4089 Package. Uncore C-box 7 perfmon counter 2.\r
4090\r
4091 @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)\r
4092 @param EAX Lower 32-bits of MSR value.\r
4093 @param EDX Upper 32-bits of MSR value.\r
4094\r
4095 <b>Example usage</b>\r
4096 @code\r
4097 UINT64 Msr;\r
4098\r
4099 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);\r
4100 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);\r
4101 @endcode\r
a73ab083 4102 @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
c67b579c
MK		 4103**/\r
4104#define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A\r
4105\r
4106\r
4107/**\r
4108 Package. Uncore C-box 7 perfmon counter 3.\r
4109\r
4110 @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)\r
4111 @param EAX Lower 32-bits of MSR value.\r
4112 @param EDX Upper 32-bits of MSR value.\r
4113\r
4114 <b>Example usage</b>\r
4115 @code\r
4116 UINT64 Msr;\r
4117\r
4118 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);\r
4119 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);\r
4120 @endcode\r
a73ab083 4121 @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
c67b579c
MK		 4122**/\r
4123#define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B\r
4124\r
4125\r
4126/**\r
4127 Package. Uncore C-box 8 perfmon local box wide control.\r
4128\r
4129 @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)\r
4130 @param EAX Lower 32-bits of MSR value.\r
4131 @param EDX Upper 32-bits of MSR value.\r
4132\r
4133 <b>Example usage</b>\r
4134 @code\r
4135 UINT64 Msr;\r
4136\r
4137 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);\r
4138 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);\r
4139 @endcode\r
a73ab083 4140 @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 4141**/\r
4142#define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80\r
4143\r
4144\r
4145/**\r
4146 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r
4147\r
4148 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)\r
4149 @param EAX Lower 32-bits of MSR value.\r
4150 @param EDX Upper 32-bits of MSR value.\r
4151\r
4152 <b>Example usage</b>\r
4153 @code\r
4154 UINT64 Msr;\r
4155\r
4156 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);\r
4157 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);\r
4158 @endcode\r
a73ab083 4159 @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 4160**/\r
4161#define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81\r
4162\r
4163\r
4164/**\r
4165 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r
4166\r
4167 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)\r
4168 @param EAX Lower 32-bits of MSR value.\r
4169 @param EDX Upper 32-bits of MSR value.\r
4170\r
4171 <b>Example usage</b>\r
4172 @code\r
4173 UINT64 Msr;\r
4174\r
4175 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);\r
4176 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);\r
4177 @endcode\r
a73ab083 4178 @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 4179**/\r
4180#define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82\r
4181\r
4182\r
4183/**\r
4184 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r
4185\r
4186 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)\r
4187 @param EAX Lower 32-bits of MSR value.\r
4188 @param EDX Upper 32-bits of MSR value.\r
4189\r
4190 <b>Example usage</b>\r
4191 @code\r
4192 UINT64 Msr;\r
4193\r
4194 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);\r
4195 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);\r
4196 @endcode\r
a73ab083 4197 @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 4198**/\r
4199#define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83\r
4200\r
4201\r
4202/**\r
4203 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r
4204\r
4205 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)\r
4206 @param EAX Lower 32-bits of MSR value.\r
4207 @param EDX Upper 32-bits of MSR value.\r
4208\r
4209 <b>Example usage</b>\r
4210 @code\r
4211 UINT64 Msr;\r
4212\r
4213 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);\r
4214 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);\r
4215 @endcode\r
a73ab083 4216 @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 4217**/\r
4218#define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84\r
4219\r
4220\r
4221/**\r
4222 Package. Uncore C-box 8 perfmon box wide filter0.\r
4223\r
4224 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)\r
4225 @param EAX Lower 32-bits of MSR value.\r
4226 @param EDX Upper 32-bits of MSR value.\r
4227\r
4228 <b>Example usage</b>\r
4229 @code\r
4230 UINT64 Msr;\r
4231\r
4232 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);\r
4233 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);\r
4234 @endcode\r
a73ab083 4235 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 4236**/\r
4237#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85\r
4238\r
4239\r
4240/**\r
4241 Package. Uncore C-box 8 perfmon box wide filter1.\r
4242\r
4243 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)\r
4244 @param EAX Lower 32-bits of MSR value.\r
4245 @param EDX Upper 32-bits of MSR value.\r
4246\r
4247 <b>Example usage</b>\r
4248 @code\r
4249 UINT64 Msr;\r
4250\r
4251 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);\r
4252 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);\r
4253 @endcode\r
a73ab083 4254 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 4255**/\r
4256#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86\r
4257\r
4258\r
4259/**\r
4260 Package. Uncore C-box 8 perfmon box wide status.\r
4261\r
4262 @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)\r
4263 @param EAX Lower 32-bits of MSR value.\r
4264 @param EDX Upper 32-bits of MSR value.\r
4265\r
4266 <b>Example usage</b>\r
4267 @code\r
4268 UINT64 Msr;\r
4269\r
4270 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);\r
4271 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);\r
4272 @endcode\r
a73ab083 4273 @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 4274**/\r
4275#define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87\r
4276\r
4277\r
4278/**\r
4279 Package. Uncore C-box 8 perfmon counter 0.\r
4280\r
4281 @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)\r
4282 @param EAX Lower 32-bits of MSR value.\r
4283 @param EDX Upper 32-bits of MSR value.\r
4284\r
4285 <b>Example usage</b>\r
4286 @code\r
4287 UINT64 Msr;\r
4288\r
4289 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);\r
4290 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);\r
4291 @endcode\r
a73ab083 4292 @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
c67b579c
MK		 4293**/\r
4294#define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88\r
4295\r
4296\r
4297/**\r
4298 Package. Uncore C-box 8 perfmon counter 1.\r
4299\r
4300 @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)\r
4301 @param EAX Lower 32-bits of MSR value.\r
4302 @param EDX Upper 32-bits of MSR value.\r
4303\r
4304 <b>Example usage</b>\r
4305 @code\r
4306 UINT64 Msr;\r
4307\r
4308 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);\r
4309 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);\r
4310 @endcode\r
a73ab083 4311 @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
c67b579c
MK		 4312**/\r
4313#define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89\r
4314\r
4315\r
4316/**\r
4317 Package. Uncore C-box 8 perfmon counter 2.\r
4318\r
4319 @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)\r
4320 @param EAX Lower 32-bits of MSR value.\r
4321 @param EDX Upper 32-bits of MSR value.\r
4322\r
4323 <b>Example usage</b>\r
4324 @code\r
4325 UINT64 Msr;\r
4326\r
4327 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);\r
4328 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);\r
4329 @endcode\r
a73ab083 4330 @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
c67b579c
MK		 4331**/\r
4332#define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A\r
4333\r
4334\r
4335/**\r
4336 Package. Uncore C-box 8 perfmon counter 3.\r
4337\r
4338 @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)\r
4339 @param EAX Lower 32-bits of MSR value.\r
4340 @param EDX Upper 32-bits of MSR value.\r
4341\r
4342 <b>Example usage</b>\r
4343 @code\r
4344 UINT64 Msr;\r
4345\r
4346 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);\r
4347 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);\r
4348 @endcode\r
a73ab083 4349 @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
c67b579c
MK		 4350**/\r
4351#define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B\r
4352\r
4353\r
4354/**\r
4355 Package. Uncore C-box 9 perfmon local box wide control.\r
4356\r
4357 @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)\r
4358 @param EAX Lower 32-bits of MSR value.\r
4359 @param EDX Upper 32-bits of MSR value.\r
4360\r
4361 <b>Example usage</b>\r
4362 @code\r
4363 UINT64 Msr;\r
4364\r
4365 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);\r
4366 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);\r
4367 @endcode\r
a73ab083 4368 @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 4369**/\r
4370#define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90\r
4371\r
4372\r
4373/**\r
4374 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r
4375\r
4376 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)\r
4377 @param EAX Lower 32-bits of MSR value.\r
4378 @param EDX Upper 32-bits of MSR value.\r
4379\r
4380 <b>Example usage</b>\r
4381 @code\r
4382 UINT64 Msr;\r
4383\r
4384 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);\r
4385 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);\r
4386 @endcode\r
a73ab083 4387 @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 4388**/\r
4389#define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91\r
4390\r
4391\r
4392/**\r
4393 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r
4394\r
4395 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)\r
4396 @param EAX Lower 32-bits of MSR value.\r
4397 @param EDX Upper 32-bits of MSR value.\r
4398\r
4399 <b>Example usage</b>\r
4400 @code\r
4401 UINT64 Msr;\r
4402\r
4403 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);\r
4404 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);\r
4405 @endcode\r
a73ab083 4406 @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 4407**/\r
4408#define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92\r
4409\r
4410\r
4411/**\r
4412 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r
4413\r
4414 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)\r
4415 @param EAX Lower 32-bits of MSR value.\r
4416 @param EDX Upper 32-bits of MSR value.\r
4417\r
4418 <b>Example usage</b>\r
4419 @code\r
4420 UINT64 Msr;\r
4421\r
4422 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);\r
4423 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);\r
4424 @endcode\r
a73ab083 4425 @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 4426**/\r
4427#define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93\r
4428\r
4429\r
4430/**\r
4431 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r
4432\r
4433 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)\r
4434 @param EAX Lower 32-bits of MSR value.\r
4435 @param EDX Upper 32-bits of MSR value.\r
4436\r
4437 <b>Example usage</b>\r
4438 @code\r
4439 UINT64 Msr;\r
4440\r
4441 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);\r
4442 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);\r
4443 @endcode\r
a73ab083 4444 @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 4445**/\r
4446#define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94\r
4447\r
4448\r
4449/**\r
4450 Package. Uncore C-box 9 perfmon box wide filter0.\r
4451\r
4452 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)\r
4453 @param EAX Lower 32-bits of MSR value.\r
4454 @param EDX Upper 32-bits of MSR value.\r
4455\r
4456 <b>Example usage</b>\r
4457 @code\r
4458 UINT64 Msr;\r
4459\r
4460 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);\r
4461 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);\r
4462 @endcode\r
a73ab083 4463 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 4464**/\r
4465#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95\r
4466\r
4467\r
4468/**\r
4469 Package. Uncore C-box 9 perfmon box wide filter1.\r
4470\r
4471 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)\r
4472 @param EAX Lower 32-bits of MSR value.\r
4473 @param EDX Upper 32-bits of MSR value.\r
4474\r
4475 <b>Example usage</b>\r
4476 @code\r
4477 UINT64 Msr;\r
4478\r
4479 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);\r
4480 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);\r
4481 @endcode\r
a73ab083 4482 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 4483**/\r
4484#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96\r
4485\r
4486\r
4487/**\r
4488 Package. Uncore C-box 9 perfmon box wide status.\r
4489\r
4490 @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)\r
4491 @param EAX Lower 32-bits of MSR value.\r
4492 @param EDX Upper 32-bits of MSR value.\r
4493\r
4494 <b>Example usage</b>\r
4495 @code\r
4496 UINT64 Msr;\r
4497\r
4498 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);\r
4499 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);\r
4500 @endcode\r
a73ab083 4501 @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 4502**/\r
4503#define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97\r
4504\r
4505\r
4506/**\r
4507 Package. Uncore C-box 9 perfmon counter 0.\r
4508\r
4509 @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)\r
4510 @param EAX Lower 32-bits of MSR value.\r
4511 @param EDX Upper 32-bits of MSR value.\r
4512\r
4513 <b>Example usage</b>\r
4514 @code\r
4515 UINT64 Msr;\r
4516\r
4517 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);\r
4518 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);\r
4519 @endcode\r
a73ab083 4520 @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
c67b579c
MK		 4521**/\r
4522#define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98\r
4523\r
4524\r
4525/**\r
4526 Package. Uncore C-box 9 perfmon counter 1.\r
4527\r
4528 @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)\r
4529 @param EAX Lower 32-bits of MSR value.\r
4530 @param EDX Upper 32-bits of MSR value.\r
4531\r
4532 <b>Example usage</b>\r
4533 @code\r
4534 UINT64 Msr;\r
4535\r
4536 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);\r
4537 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);\r
4538 @endcode\r
a73ab083 4539 @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
c67b579c
MK		 4540**/\r
4541#define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99\r
4542\r
4543\r
4544/**\r
4545 Package. Uncore C-box 9 perfmon counter 2.\r
4546\r
4547 @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)\r
4548 @param EAX Lower 32-bits of MSR value.\r
4549 @param EDX Upper 32-bits of MSR value.\r
4550\r
4551 <b>Example usage</b>\r
4552 @code\r
4553 UINT64 Msr;\r
4554\r
4555 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);\r
4556 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);\r
4557 @endcode\r
a73ab083 4558 @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
c67b579c
MK		 4559**/\r
4560#define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A\r
4561\r
4562\r
4563/**\r
4564 Package. Uncore C-box 9 perfmon counter 3.\r
4565\r
4566 @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)\r
4567 @param EAX Lower 32-bits of MSR value.\r
4568 @param EDX Upper 32-bits of MSR value.\r
4569\r
4570 <b>Example usage</b>\r
4571 @code\r
4572 UINT64 Msr;\r
4573\r
4574 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);\r
4575 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);\r
4576 @endcode\r
a73ab083 4577 @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
c67b579c
MK		 4578**/\r
4579#define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B\r
4580\r
4581\r
4582/**\r
4583 Package. Uncore C-box 10 perfmon local box wide control.\r
4584\r
4585 @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)\r
4586 @param EAX Lower 32-bits of MSR value.\r
4587 @param EDX Upper 32-bits of MSR value.\r
4588\r
4589 <b>Example usage</b>\r
4590 @code\r
4591 UINT64 Msr;\r
4592\r
4593 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);\r
4594 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);\r
4595 @endcode\r
a73ab083 4596 @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 4597**/\r
4598#define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0\r
4599\r
4600\r
4601/**\r
4602 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r
4603\r
4604 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)\r
4605 @param EAX Lower 32-bits of MSR value.\r
4606 @param EDX Upper 32-bits of MSR value.\r
4607\r
4608 <b>Example usage</b>\r
4609 @code\r
4610 UINT64 Msr;\r
4611\r
4612 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);\r
4613 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);\r
4614 @endcode\r
a73ab083 4615 @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 4616**/\r
4617#define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1\r
4618\r
4619\r
4620/**\r
4621 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r
4622\r
4623 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)\r
4624 @param EAX Lower 32-bits of MSR value.\r
4625 @param EDX Upper 32-bits of MSR value.\r
4626\r
4627 <b>Example usage</b>\r
4628 @code\r
4629 UINT64 Msr;\r
4630\r
4631 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);\r
4632 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);\r
4633 @endcode\r
a73ab083 4634 @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 4635**/\r
4636#define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2\r
4637\r
4638\r
4639/**\r
4640 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r
4641\r
4642 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)\r
4643 @param EAX Lower 32-bits of MSR value.\r
4644 @param EDX Upper 32-bits of MSR value.\r
4645\r
4646 <b>Example usage</b>\r
4647 @code\r
4648 UINT64 Msr;\r
4649\r
4650 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);\r
4651 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);\r
4652 @endcode\r
a73ab083 4653 @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 4654**/\r
4655#define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3\r
4656\r
4657\r
4658/**\r
4659 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r
4660\r
4661 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)\r
4662 @param EAX Lower 32-bits of MSR value.\r
4663 @param EDX Upper 32-bits of MSR value.\r
4664\r
4665 <b>Example usage</b>\r
4666 @code\r
4667 UINT64 Msr;\r
4668\r
4669 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);\r
4670 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);\r
4671 @endcode\r
a73ab083 4672 @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 4673**/\r
4674#define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4\r
4675\r
4676\r
4677/**\r
4678 Package. Uncore C-box 10 perfmon box wide filter0.\r
4679\r
4680 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)\r
4681 @param EAX Lower 32-bits of MSR value.\r
4682 @param EDX Upper 32-bits of MSR value.\r
4683\r
4684 <b>Example usage</b>\r
4685 @code\r
4686 UINT64 Msr;\r
4687\r
4688 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);\r
4689 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);\r
4690 @endcode\r
a73ab083 4691 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 4692**/\r
4693#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5\r
4694\r
4695\r
4696/**\r
4697 Package. Uncore C-box 10 perfmon box wide filter1.\r
4698\r
4699 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)\r
4700 @param EAX Lower 32-bits of MSR value.\r
4701 @param EDX Upper 32-bits of MSR value.\r
4702\r
4703 <b>Example usage</b>\r
4704 @code\r
4705 UINT64 Msr;\r
4706\r
4707 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);\r
4708 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);\r
4709 @endcode\r
a73ab083 4710 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 4711**/\r
4712#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6\r
4713\r
4714\r
4715/**\r
4716 Package. Uncore C-box 10 perfmon box wide status.\r
4717\r
4718 @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)\r
4719 @param EAX Lower 32-bits of MSR value.\r
4720 @param EDX Upper 32-bits of MSR value.\r
4721\r
4722 <b>Example usage</b>\r
4723 @code\r
4724 UINT64 Msr;\r
4725\r
4726 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);\r
4727 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);\r
4728 @endcode\r
a73ab083 4729 @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 4730**/\r
4731#define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7\r
4732\r
4733\r
4734/**\r
4735 Package. Uncore C-box 10 perfmon counter 0.\r
4736\r
4737 @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)\r
4738 @param EAX Lower 32-bits of MSR value.\r
4739 @param EDX Upper 32-bits of MSR value.\r
4740\r
4741 <b>Example usage</b>\r
4742 @code\r
4743 UINT64 Msr;\r
4744\r
4745 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);\r
4746 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);\r
4747 @endcode\r
a73ab083 4748 @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r
c67b579c
MK		 4749**/\r
4750#define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8\r
4751\r
4752\r
4753/**\r
4754 Package. Uncore C-box 10 perfmon counter 1.\r
4755\r
4756 @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)\r
4757 @param EAX Lower 32-bits of MSR value.\r
4758 @param EDX Upper 32-bits of MSR value.\r
4759\r
4760 <b>Example usage</b>\r
4761 @code\r
4762 UINT64 Msr;\r
4763\r
4764 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);\r
4765 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);\r
4766 @endcode\r
a73ab083 4767 @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r
c67b579c
MK		 4768**/\r
4769#define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9\r
4770\r
4771\r
4772/**\r
4773 Package. Uncore C-box 10 perfmon counter 2.\r
4774\r
4775 @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)\r
4776 @param EAX Lower 32-bits of MSR value.\r
4777 @param EDX Upper 32-bits of MSR value.\r
4778\r
4779 <b>Example usage</b>\r
4780 @code\r
4781 UINT64 Msr;\r
4782\r
4783 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);\r
4784 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);\r
4785 @endcode\r
a73ab083 4786 @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r
c67b579c
MK		 4787**/\r
4788#define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA\r
4789\r
4790\r
4791/**\r
4792 Package. Uncore C-box 10 perfmon counter 3.\r
4793\r
4794 @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)\r
4795 @param EAX Lower 32-bits of MSR value.\r
4796 @param EDX Upper 32-bits of MSR value.\r
4797\r
4798 <b>Example usage</b>\r
4799 @code\r
4800 UINT64 Msr;\r
4801\r
4802 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);\r
4803 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);\r
4804 @endcode\r
a73ab083 4805 @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r
c67b579c
MK		 4806**/\r
4807#define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB\r
4808\r
4809\r
4810/**\r
4811 Package. Uncore C-box 11 perfmon local box wide control.\r
4812\r
4813 @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)\r
4814 @param EAX Lower 32-bits of MSR value.\r
4815 @param EDX Upper 32-bits of MSR value.\r
4816\r
4817 <b>Example usage</b>\r
4818 @code\r
4819 UINT64 Msr;\r
4820\r
4821 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);\r
4822 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);\r
4823 @endcode\r
a73ab083 4824 @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 4825**/\r
4826#define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0\r
4827\r
4828\r
4829/**\r
4830 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r
4831\r
4832 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)\r
4833 @param EAX Lower 32-bits of MSR value.\r
4834 @param EDX Upper 32-bits of MSR value.\r
4835\r
4836 <b>Example usage</b>\r
4837 @code\r
4838 UINT64 Msr;\r
4839\r
4840 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);\r
4841 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);\r
4842 @endcode\r
a73ab083 4843 @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 4844**/\r
4845#define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1\r
4846\r
4847\r
4848/**\r
4849 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r
4850\r
4851 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)\r
4852 @param EAX Lower 32-bits of MSR value.\r
4853 @param EDX Upper 32-bits of MSR value.\r
4854\r
4855 <b>Example usage</b>\r
4856 @code\r
4857 UINT64 Msr;\r
4858\r
4859 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);\r
4860 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);\r
4861 @endcode\r
a73ab083 4862 @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 4863**/\r
4864#define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2\r
4865\r
4866\r
4867/**\r
4868 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r
4869\r
4870 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)\r
4871 @param EAX Lower 32-bits of MSR value.\r
4872 @param EDX Upper 32-bits of MSR value.\r
4873\r
4874 <b>Example usage</b>\r
4875 @code\r
4876 UINT64 Msr;\r
4877\r
4878 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);\r
4879 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);\r
4880 @endcode\r
a73ab083 4881 @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 4882**/\r
4883#define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3\r
4884\r
4885\r
4886/**\r
4887 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r
4888\r
4889 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)\r
4890 @param EAX Lower 32-bits of MSR value.\r
4891 @param EDX Upper 32-bits of MSR value.\r
4892\r
4893 <b>Example usage</b>\r
4894 @code\r
4895 UINT64 Msr;\r
4896\r
4897 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);\r
4898 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);\r
4899 @endcode\r
a73ab083 4900 @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 4901**/\r
4902#define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4\r
4903\r
4904\r
4905/**\r
4906 Package. Uncore C-box 11 perfmon box wide filter0.\r
4907\r
4908 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)\r
4909 @param EAX Lower 32-bits of MSR value.\r
4910 @param EDX Upper 32-bits of MSR value.\r
4911\r
4912 <b>Example usage</b>\r
4913 @code\r
4914 UINT64 Msr;\r
4915\r
4916 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);\r
4917 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);\r
4918 @endcode\r
a73ab083 4919 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 4920**/\r
4921#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5\r
4922\r
4923\r
4924/**\r
4925 Package. Uncore C-box 11 perfmon box wide filter1.\r
4926\r
4927 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)\r
4928 @param EAX Lower 32-bits of MSR value.\r
4929 @param EDX Upper 32-bits of MSR value.\r
4930\r
4931 <b>Example usage</b>\r
4932 @code\r
4933 UINT64 Msr;\r
4934\r
4935 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);\r
4936 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);\r
4937 @endcode\r
a73ab083 4938 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 4939**/\r
4940#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6\r
4941\r
4942\r
4943/**\r
4944 Package. Uncore C-box 11 perfmon box wide status.\r
4945\r
4946 @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)\r
4947 @param EAX Lower 32-bits of MSR value.\r
4948 @param EDX Upper 32-bits of MSR value.\r
4949\r
4950 <b>Example usage</b>\r
4951 @code\r
4952 UINT64 Msr;\r
4953\r
4954 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);\r
4955 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);\r
4956 @endcode\r
a73ab083 4957 @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 4958**/\r
4959#define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7\r
4960\r
4961\r
4962/**\r
4963 Package. Uncore C-box 11 perfmon counter 0.\r
4964\r
4965 @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)\r
4966 @param EAX Lower 32-bits of MSR value.\r
4967 @param EDX Upper 32-bits of MSR value.\r
4968\r
4969 <b>Example usage</b>\r
4970 @code\r
4971 UINT64 Msr;\r
4972\r
4973 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);\r
4974 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);\r
4975 @endcode\r
a73ab083 4976 @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r
c67b579c
MK		 4977**/\r
4978#define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8\r
4979\r
4980\r
4981/**\r
4982 Package. Uncore C-box 11 perfmon counter 1.\r
4983\r
4984 @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)\r
4985 @param EAX Lower 32-bits of MSR value.\r
4986 @param EDX Upper 32-bits of MSR value.\r
4987\r
4988 <b>Example usage</b>\r
4989 @code\r
4990 UINT64 Msr;\r
4991\r
4992 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);\r
4993 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);\r
4994 @endcode\r
a73ab083 4995 @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r
c67b579c
MK		 4996**/\r
4997#define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9\r
4998\r
4999\r
5000/**\r
5001 Package. Uncore C-box 11 perfmon counter 2.\r
5002\r
5003 @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)\r
5004 @param EAX Lower 32-bits of MSR value.\r
5005 @param EDX Upper 32-bits of MSR value.\r
5006\r
5007 <b>Example usage</b>\r
5008 @code\r
5009 UINT64 Msr;\r
5010\r
5011 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);\r
5012 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);\r
5013 @endcode\r
a73ab083 5014 @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r
c67b579c
MK		 5015**/\r
5016#define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA\r
5017\r
5018\r
5019/**\r
5020 Package. Uncore C-box 11 perfmon counter 3.\r
5021\r
5022 @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)\r
5023 @param EAX Lower 32-bits of MSR value.\r
5024 @param EDX Upper 32-bits of MSR value.\r
5025\r
5026 <b>Example usage</b>\r
5027 @code\r
5028 UINT64 Msr;\r
5029\r
5030 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);\r
5031 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);\r
5032 @endcode\r
a73ab083 5033 @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r
c67b579c
MK		 5034**/\r
5035#define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB\r
5036\r
5037\r
5038/**\r
5039 Package. Uncore C-box 12 perfmon local box wide control.\r
5040\r
5041 @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)\r
5042 @param EAX Lower 32-bits of MSR value.\r
5043 @param EDX Upper 32-bits of MSR value.\r
5044\r
5045 <b>Example usage</b>\r
5046 @code\r
5047 UINT64 Msr;\r
5048\r
5049 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);\r
5050 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);\r
5051 @endcode\r
a73ab083 5052 @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 5053**/\r
5054#define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0\r
5055\r
5056\r
5057/**\r
5058 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r
5059\r
5060 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)\r
5061 @param EAX Lower 32-bits of MSR value.\r
5062 @param EDX Upper 32-bits of MSR value.\r
5063\r
5064 <b>Example usage</b>\r
5065 @code\r
5066 UINT64 Msr;\r
5067\r
5068 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);\r
5069 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);\r
5070 @endcode\r
a73ab083 5071 @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 5072**/\r
5073#define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1\r
5074\r
5075\r
5076/**\r
5077 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r
5078\r
5079 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)\r
5080 @param EAX Lower 32-bits of MSR value.\r
5081 @param EDX Upper 32-bits of MSR value.\r
5082\r
5083 <b>Example usage</b>\r
5084 @code\r
5085 UINT64 Msr;\r
5086\r
5087 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);\r
5088 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);\r
5089 @endcode\r
a73ab083 5090 @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 5091**/\r
5092#define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2\r
5093\r
5094\r
5095/**\r
5096 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r
5097\r
5098 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)\r
5099 @param EAX Lower 32-bits of MSR value.\r
5100 @param EDX Upper 32-bits of MSR value.\r
5101\r
5102 <b>Example usage</b>\r
5103 @code\r
5104 UINT64 Msr;\r
5105\r
5106 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);\r
5107 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);\r
5108 @endcode\r
a73ab083 5109 @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 5110**/\r
5111#define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3\r
5112\r
5113\r
5114/**\r
5115 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r
5116\r
5117 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)\r
5118 @param EAX Lower 32-bits of MSR value.\r
5119 @param EDX Upper 32-bits of MSR value.\r
5120\r
5121 <b>Example usage</b>\r
5122 @code\r
5123 UINT64 Msr;\r
5124\r
5125 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);\r
5126 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);\r
5127 @endcode\r
a73ab083 5128 @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 5129**/\r
5130#define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4\r
5131\r
5132\r
5133/**\r
5134 Package. Uncore C-box 12 perfmon box wide filter0.\r
5135\r
5136 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)\r
5137 @param EAX Lower 32-bits of MSR value.\r
5138 @param EDX Upper 32-bits of MSR value.\r
5139\r
5140 <b>Example usage</b>\r
5141 @code\r
5142 UINT64 Msr;\r
5143\r
5144 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);\r
5145 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);\r
5146 @endcode\r
a73ab083 5147 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 5148**/\r
5149#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5\r
5150\r
5151\r
5152/**\r
5153 Package. Uncore C-box 12 perfmon box wide filter1.\r
5154\r
5155 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)\r
5156 @param EAX Lower 32-bits of MSR value.\r
5157 @param EDX Upper 32-bits of MSR value.\r
5158\r
5159 <b>Example usage</b>\r
5160 @code\r
5161 UINT64 Msr;\r
5162\r
5163 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);\r
5164 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);\r
5165 @endcode\r
a73ab083 5166 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 5167**/\r
5168#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6\r
5169\r
5170\r
5171/**\r
5172 Package. Uncore C-box 12 perfmon box wide status.\r
5173\r
5174 @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)\r
5175 @param EAX Lower 32-bits of MSR value.\r
5176 @param EDX Upper 32-bits of MSR value.\r
5177\r
5178 <b>Example usage</b>\r
5179 @code\r
5180 UINT64 Msr;\r
5181\r
5182 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);\r
5183 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);\r
5184 @endcode\r
a73ab083 5185 @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 5186**/\r
5187#define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7\r
5188\r
5189\r
5190/**\r
5191 Package. Uncore C-box 12 perfmon counter 0.\r
5192\r
5193 @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)\r
5194 @param EAX Lower 32-bits of MSR value.\r
5195 @param EDX Upper 32-bits of MSR value.\r
5196\r
5197 <b>Example usage</b>\r
5198 @code\r
5199 UINT64 Msr;\r
5200\r
5201 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);\r
5202 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);\r
5203 @endcode\r
a73ab083 5204 @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r
c67b579c
MK		 5205**/\r
5206#define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8\r
5207\r
5208\r
5209/**\r
5210 Package. Uncore C-box 12 perfmon counter 1.\r
5211\r
5212 @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)\r
5213 @param EAX Lower 32-bits of MSR value.\r
5214 @param EDX Upper 32-bits of MSR value.\r
5215\r
5216 <b>Example usage</b>\r
5217 @code\r
5218 UINT64 Msr;\r
5219\r
5220 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);\r
5221 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);\r
5222 @endcode\r
a73ab083 5223 @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r
c67b579c
MK		 5224**/\r
5225#define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9\r
5226\r
5227\r
5228/**\r
5229 Package. Uncore C-box 12 perfmon counter 2.\r
5230\r
5231 @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)\r
5232 @param EAX Lower 32-bits of MSR value.\r
5233 @param EDX Upper 32-bits of MSR value.\r
5234\r
5235 <b>Example usage</b>\r
5236 @code\r
5237 UINT64 Msr;\r
5238\r
5239 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);\r
5240 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);\r
5241 @endcode\r
a73ab083 5242 @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r
c67b579c
MK		 5243**/\r
5244#define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA\r
5245\r
5246\r
5247/**\r
5248 Package. Uncore C-box 12 perfmon counter 3.\r
5249\r
5250 @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)\r
5251 @param EAX Lower 32-bits of MSR value.\r
5252 @param EDX Upper 32-bits of MSR value.\r
5253\r
5254 <b>Example usage</b>\r
5255 @code\r
5256 UINT64 Msr;\r
5257\r
5258 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);\r
5259 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);\r
5260 @endcode\r
a73ab083 5261 @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r
c67b579c
MK		 5262**/\r
5263#define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB\r
5264\r
5265\r
5266/**\r
5267 Package. Uncore C-box 13 perfmon local box wide control.\r
5268\r
5269 @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)\r
5270 @param EAX Lower 32-bits of MSR value.\r
5271 @param EDX Upper 32-bits of MSR value.\r
5272\r
5273 <b>Example usage</b>\r
5274 @code\r
5275 UINT64 Msr;\r
5276\r
5277 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);\r
5278 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);\r
5279 @endcode\r
a73ab083 5280 @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 5281**/\r
5282#define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0\r
5283\r
5284\r
5285/**\r
5286 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r
5287\r
5288 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)\r
5289 @param EAX Lower 32-bits of MSR value.\r
5290 @param EDX Upper 32-bits of MSR value.\r
5291\r
5292 <b>Example usage</b>\r
5293 @code\r
5294 UINT64 Msr;\r
5295\r
5296 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);\r
5297 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);\r
5298 @endcode\r
a73ab083 5299 @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 5300**/\r
5301#define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1\r
5302\r
5303\r
5304/**\r
5305 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r
5306\r
5307 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)\r
5308 @param EAX Lower 32-bits of MSR value.\r
5309 @param EDX Upper 32-bits of MSR value.\r
5310\r
5311 <b>Example usage</b>\r
5312 @code\r
5313 UINT64 Msr;\r
5314\r
5315 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);\r
5316 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);\r
5317 @endcode\r
a73ab083 5318 @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 5319**/\r
5320#define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2\r
5321\r
5322\r
5323/**\r
5324 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r
5325\r
5326 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)\r
5327 @param EAX Lower 32-bits of MSR value.\r
5328 @param EDX Upper 32-bits of MSR value.\r
5329\r
5330 <b>Example usage</b>\r
5331 @code\r
5332 UINT64 Msr;\r
5333\r
5334 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);\r
5335 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);\r
5336 @endcode\r
a73ab083 5337 @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 5338**/\r
5339#define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3\r
5340\r
5341\r
5342/**\r
5343 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r
5344\r
5345 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)\r
5346 @param EAX Lower 32-bits of MSR value.\r
5347 @param EDX Upper 32-bits of MSR value.\r
5348\r
5349 <b>Example usage</b>\r
5350 @code\r
5351 UINT64 Msr;\r
5352\r
5353 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);\r
5354 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);\r
5355 @endcode\r
a73ab083 5356 @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 5357**/\r
5358#define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4\r
5359\r
5360\r
5361/**\r
5362 Package. Uncore C-box 13 perfmon box wide filter0.\r
5363\r
5364 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)\r
5365 @param EAX Lower 32-bits of MSR value.\r
5366 @param EDX Upper 32-bits of MSR value.\r
5367\r
5368 <b>Example usage</b>\r
5369 @code\r
5370 UINT64 Msr;\r
5371\r
5372 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);\r
5373 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);\r
5374 @endcode\r
a73ab083 5375 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 5376**/\r
5377#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5\r
5378\r
5379\r
5380/**\r
5381 Package. Uncore C-box 13 perfmon box wide filter1.\r
5382\r
5383 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)\r
5384 @param EAX Lower 32-bits of MSR value.\r
5385 @param EDX Upper 32-bits of MSR value.\r
5386\r
5387 <b>Example usage</b>\r
5388 @code\r
5389 UINT64 Msr;\r
5390\r
5391 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);\r
5392 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);\r
5393 @endcode\r
a73ab083 5394 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 5395**/\r
5396#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6\r
5397\r
5398\r
5399/**\r
5400 Package. Uncore C-box 13 perfmon box wide status.\r
5401\r
5402 @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)\r
5403 @param EAX Lower 32-bits of MSR value.\r
5404 @param EDX Upper 32-bits of MSR value.\r
5405\r
5406 <b>Example usage</b>\r
5407 @code\r
5408 UINT64 Msr;\r
5409\r
5410 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);\r
5411 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);\r
5412 @endcode\r
a73ab083 5413 @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 5414**/\r
5415#define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7\r
5416\r
5417\r
5418/**\r
5419 Package. Uncore C-box 13 perfmon counter 0.\r
5420\r
5421 @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)\r
5422 @param EAX Lower 32-bits of MSR value.\r
5423 @param EDX Upper 32-bits of MSR value.\r
5424\r
5425 <b>Example usage</b>\r
5426 @code\r
5427 UINT64 Msr;\r
5428\r
5429 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);\r
5430 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);\r
5431 @endcode\r
a73ab083 5432 @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r
c67b579c
MK		 5433**/\r
5434#define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8\r
5435\r
5436\r
5437/**\r
5438 Package. Uncore C-box 13 perfmon counter 1.\r
5439\r
5440 @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)\r
5441 @param EAX Lower 32-bits of MSR value.\r
5442 @param EDX Upper 32-bits of MSR value.\r
5443\r
5444 <b>Example usage</b>\r
5445 @code\r
5446 UINT64 Msr;\r
5447\r
5448 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);\r
5449 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);\r
5450 @endcode\r
a73ab083 5451 @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r
c67b579c
MK		 5452**/\r
5453#define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9\r
5454\r
5455\r
5456/**\r
5457 Package. Uncore C-box 13 perfmon counter 2.\r
5458\r
5459 @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)\r
5460 @param EAX Lower 32-bits of MSR value.\r
5461 @param EDX Upper 32-bits of MSR value.\r
5462\r
5463 <b>Example usage</b>\r
5464 @code\r
5465 UINT64 Msr;\r
5466\r
5467 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);\r
5468 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);\r
5469 @endcode\r
a73ab083 5470 @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r
c67b579c
MK		 5471**/\r
5472#define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA\r
5473\r
5474\r
5475/**\r
5476 Package. Uncore C-box 13 perfmon counter 3.\r
5477\r
5478 @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)\r
5479 @param EAX Lower 32-bits of MSR value.\r
5480 @param EDX Upper 32-bits of MSR value.\r
5481\r
5482 <b>Example usage</b>\r
5483 @code\r
5484 UINT64 Msr;\r
5485\r
5486 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);\r
5487 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);\r
5488 @endcode\r
a73ab083 5489 @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r
c67b579c
MK		 5490**/\r
5491#define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB\r
5492\r
5493\r
5494/**\r
5495 Package. Uncore C-box 14 perfmon local box wide control.\r
5496\r
5497 @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)\r
5498 @param EAX Lower 32-bits of MSR value.\r
5499 @param EDX Upper 32-bits of MSR value.\r
5500\r
5501 <b>Example usage</b>\r
5502 @code\r
5503 UINT64 Msr;\r
5504\r
5505 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);\r
5506 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);\r
5507 @endcode\r
a73ab083 5508 @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 5509**/\r
5510#define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0\r
5511\r
5512\r
5513/**\r
5514 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r
5515\r
5516 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)\r
5517 @param EAX Lower 32-bits of MSR value.\r
5518 @param EDX Upper 32-bits of MSR value.\r
5519\r
5520 <b>Example usage</b>\r
5521 @code\r
5522 UINT64 Msr;\r
5523\r
5524 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);\r
5525 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);\r
5526 @endcode\r
a73ab083 5527 @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 5528**/\r
5529#define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1\r
5530\r
5531\r
5532/**\r
5533 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r
5534\r
5535 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)\r
5536 @param EAX Lower 32-bits of MSR value.\r
5537 @param EDX Upper 32-bits of MSR value.\r
5538\r
5539 <b>Example usage</b>\r
5540 @code\r
5541 UINT64 Msr;\r
5542\r
5543 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);\r
5544 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);\r
5545 @endcode\r
a73ab083 5546 @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 5547**/\r
5548#define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2\r
5549\r
5550\r
5551/**\r
5552 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r
5553\r
5554 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)\r
5555 @param EAX Lower 32-bits of MSR value.\r
5556 @param EDX Upper 32-bits of MSR value.\r
5557\r
5558 <b>Example usage</b>\r
5559 @code\r
5560 UINT64 Msr;\r
5561\r
5562 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);\r
5563 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);\r
5564 @endcode\r
a73ab083 5565 @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 5566**/\r
5567#define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3\r
5568\r
5569\r
5570/**\r
5571 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r
5572\r
5573 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)\r
5574 @param EAX Lower 32-bits of MSR value.\r
5575 @param EDX Upper 32-bits of MSR value.\r
5576\r
5577 <b>Example usage</b>\r
5578 @code\r
5579 UINT64 Msr;\r
5580\r
5581 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);\r
5582 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);\r
5583 @endcode\r
a73ab083 5584 @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 5585**/\r
5586#define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4\r
5587\r
5588\r
5589/**\r
5590 Package. Uncore C-box 14 perfmon box wide filter0.\r
5591\r
5592 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)\r
5593 @param EAX Lower 32-bits of MSR value.\r
5594 @param EDX Upper 32-bits of MSR value.\r
5595\r
5596 <b>Example usage</b>\r
5597 @code\r
5598 UINT64 Msr;\r
5599\r
5600 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);\r
5601 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);\r
5602 @endcode\r
a73ab083 5603 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r
c67b579c
MK		 5604**/\r
5605#define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5\r
5606\r
5607\r
5608/**\r
5609 Package. Uncore C-box 14 perfmon box wide filter1.\r
5610\r
5611 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)\r
5612 @param EAX Lower 32-bits of MSR value.\r
5613 @param EDX Upper 32-bits of MSR value.\r
5614\r
5615 <b>Example usage</b>\r
5616 @code\r
5617 UINT64 Msr;\r
5618\r
5619 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);\r
5620 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);\r
5621 @endcode\r
a73ab083 5622 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 5623**/\r
5624#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6\r
5625\r
5626\r
5627/**\r
5628 Package. Uncore C-box 14 perfmon box wide status.\r
5629\r
5630 @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)\r
5631 @param EAX Lower 32-bits of MSR value.\r
5632 @param EDX Upper 32-bits of MSR value.\r
5633\r
5634 <b>Example usage</b>\r
5635 @code\r
5636 UINT64 Msr;\r
5637\r
5638 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);\r
5639 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);\r
5640 @endcode\r
a73ab083 5641 @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 5642**/\r
5643#define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7\r
5644\r
5645\r
5646/**\r
5647 Package. Uncore C-box 14 perfmon counter 0.\r
5648\r
5649 @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)\r
5650 @param EAX Lower 32-bits of MSR value.\r
5651 @param EDX Upper 32-bits of MSR value.\r
5652\r
5653 <b>Example usage</b>\r
5654 @code\r
5655 UINT64 Msr;\r
5656\r
5657 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);\r
5658 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);\r
5659 @endcode\r
a73ab083 5660 @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r
c67b579c
MK		 5661**/\r
5662#define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8\r
5663\r
5664\r
5665/**\r
5666 Package. Uncore C-box 14 perfmon counter 1.\r
5667\r
5668 @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)\r
5669 @param EAX Lower 32-bits of MSR value.\r
5670 @param EDX Upper 32-bits of MSR value.\r
5671\r
5672 <b>Example usage</b>\r
5673 @code\r
5674 UINT64 Msr;\r
5675\r
5676 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);\r
5677 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);\r
5678 @endcode\r
a73ab083 5679 @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r
c67b579c
MK		 5680**/\r
5681#define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9\r
5682\r
5683\r
5684/**\r
5685 Package. Uncore C-box 14 perfmon counter 2.\r
5686\r
5687 @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)\r
5688 @param EAX Lower 32-bits of MSR value.\r
5689 @param EDX Upper 32-bits of MSR value.\r
5690\r
5691 <b>Example usage</b>\r
5692 @code\r
5693 UINT64 Msr;\r
5694\r
5695 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);\r
5696 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);\r
5697 @endcode\r
a73ab083 5698 @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r
c67b579c
MK		 5699**/\r
5700#define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA\r
5701\r
5702\r
5703/**\r
5704 Package. Uncore C-box 14 perfmon counter 3.\r
5705\r
5706 @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)\r
5707 @param EAX Lower 32-bits of MSR value.\r
5708 @param EDX Upper 32-bits of MSR value.\r
5709\r
5710 <b>Example usage</b>\r
5711 @code\r
5712 UINT64 Msr;\r
5713\r
5714 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);\r
5715 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);\r
5716 @endcode\r
a73ab083 5717 @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r
c67b579c
MK		 5718**/\r
5719#define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB\r
5720\r
5721\r
5722/**\r
5723 Package. Uncore C-box 15 perfmon local box wide control.\r
5724\r
5725 @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)\r
5726 @param EAX Lower 32-bits of MSR value.\r
5727 @param EDX Upper 32-bits of MSR value.\r
5728\r
5729 <b>Example usage</b>\r
5730 @code\r
5731 UINT64 Msr;\r
5732\r
5733 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);\r
5734 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);\r
5735 @endcode\r
a73ab083 5736 @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 5737**/\r
5738#define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0\r
5739\r
5740\r
5741/**\r
5742 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.\r
5743\r
5744 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)\r
5745 @param EAX Lower 32-bits of MSR value.\r
5746 @param EDX Upper 32-bits of MSR value.\r
5747\r
5748 <b>Example usage</b>\r
5749 @code\r
5750 UINT64 Msr;\r
5751\r
5752 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);\r
5753 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);\r
5754 @endcode\r
a73ab083 5755 @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 5756**/\r
5757#define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1\r
5758\r
5759\r
5760/**\r
5761 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.\r
5762\r
5763 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)\r
5764 @param EAX Lower 32-bits of MSR value.\r
5765 @param EDX Upper 32-bits of MSR value.\r
5766\r
5767 <b>Example usage</b>\r
5768 @code\r
5769 UINT64 Msr;\r
5770\r
5771 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);\r
5772 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);\r
5773 @endcode\r
a73ab083 5774 @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 5775**/\r
5776#define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2\r
5777\r
5778\r
5779/**\r
5780 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.\r
5781\r
5782 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)\r
5783 @param EAX Lower 32-bits of MSR value.\r
5784 @param EDX Upper 32-bits of MSR value.\r
5785\r
5786 <b>Example usage</b>\r
5787 @code\r
5788 UINT64 Msr;\r
5789\r
5790 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);\r
5791 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);\r
5792 @endcode\r
a73ab083 5793 @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 5794**/\r
5795#define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3\r
5796\r
5797\r
5798/**\r
5799 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.\r
5800\r
5801 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)\r
5802 @param EAX Lower 32-bits of MSR value.\r
5803 @param EDX Upper 32-bits of MSR value.\r
5804\r
5805 <b>Example usage</b>\r
5806 @code\r
5807 UINT64 Msr;\r
5808\r
5809 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);\r
5810 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);\r
5811 @endcode\r
a73ab083 5812 @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 5813**/\r
5814#define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4\r
5815\r
5816\r
5817/**\r
5818 Package. Uncore C-box 15 perfmon box wide filter0.\r
5819\r
5820 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)\r
5821 @param EAX Lower 32-bits of MSR value.\r
5822 @param EDX Upper 32-bits of MSR value.\r
5823\r
5824 <b>Example usage</b>\r
5825 @code\r
5826 UINT64 Msr;\r
5827\r
5828 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);\r
5829 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);\r
5830 @endcode\r
a73ab083 5831 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 5832**/\r
5833#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5\r
5834\r
5835\r
5836/**\r
5837 Package. Uncore C-box 15 perfmon box wide filter1.\r
5838\r
5839 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)\r
5840 @param EAX Lower 32-bits of MSR value.\r
5841 @param EDX Upper 32-bits of MSR value.\r
5842\r
5843 <b>Example usage</b>\r
5844 @code\r
5845 UINT64 Msr;\r
5846\r
5847 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);\r
5848 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);\r
5849 @endcode\r
a73ab083 5850 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 5851**/\r
5852#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6\r
5853\r
5854\r
5855/**\r
5856 Package. Uncore C-box 15 perfmon box wide status.\r
5857\r
5858 @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)\r
5859 @param EAX Lower 32-bits of MSR value.\r
5860 @param EDX Upper 32-bits of MSR value.\r
5861\r
5862 <b>Example usage</b>\r
5863 @code\r
5864 UINT64 Msr;\r
5865\r
5866 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);\r
5867 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);\r
5868 @endcode\r
a73ab083 5869 @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 5870**/\r
5871#define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7\r
5872\r
5873\r
5874/**\r
5875 Package. Uncore C-box 15 perfmon counter 0.\r
5876\r
5877 @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)\r
5878 @param EAX Lower 32-bits of MSR value.\r
5879 @param EDX Upper 32-bits of MSR value.\r
5880\r
5881 <b>Example usage</b>\r
5882 @code\r
5883 UINT64 Msr;\r
5884\r
5885 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);\r
5886 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);\r
5887 @endcode\r
a73ab083 5888 @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.\r
c67b579c
MK		 5889**/\r
5890#define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8\r
5891\r
5892\r
5893/**\r
5894 Package. Uncore C-box 15 perfmon counter 1.\r
5895\r
5896 @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)\r
5897 @param EAX Lower 32-bits of MSR value.\r
5898 @param EDX Upper 32-bits of MSR value.\r
5899\r
5900 <b>Example usage</b>\r
5901 @code\r
5902 UINT64 Msr;\r
5903\r
5904 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);\r
5905 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);\r
5906 @endcode\r
a73ab083 5907 @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.\r
c67b579c
MK		 5908**/\r
5909#define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9\r
5910\r
5911\r
5912/**\r
5913 Package. Uncore C-box 15 perfmon counter 2.\r
5914\r
5915 @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)\r
5916 @param EAX Lower 32-bits of MSR value.\r
5917 @param EDX Upper 32-bits of MSR value.\r
5918\r
5919 <b>Example usage</b>\r
5920 @code\r
5921 UINT64 Msr;\r
5922\r
5923 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);\r
5924 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);\r
5925 @endcode\r
a73ab083 5926 @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.\r
c67b579c
MK		 5927**/\r
5928#define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA\r
5929\r
5930\r
5931/**\r
5932 Package. Uncore C-box 15 perfmon counter 3.\r
5933\r
5934 @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)\r
5935 @param EAX Lower 32-bits of MSR value.\r
5936 @param EDX Upper 32-bits of MSR value.\r
5937\r
5938 <b>Example usage</b>\r
5939 @code\r
5940 UINT64 Msr;\r
5941\r
5942 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);\r
5943 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);\r
5944 @endcode\r
a73ab083 5945 @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.\r
c67b579c
MK		 5946**/\r
5947#define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB\r
5948\r
5949\r
5950/**\r
5951 Package. Uncore C-box 16 perfmon for box-wide control.\r
5952\r
5953 @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)\r
5954 @param EAX Lower 32-bits of MSR value.\r
5955 @param EDX Upper 32-bits of MSR value.\r
5956\r
5957 <b>Example usage</b>\r
5958 @code\r
5959 UINT64 Msr;\r
5960\r
5961 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);\r
5962 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);\r
5963 @endcode\r
a73ab083 5964 @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 5965**/\r
5966#define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00\r
5967\r
5968\r
5969/**\r
5970 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.\r
5971\r
5972 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)\r
5973 @param EAX Lower 32-bits of MSR value.\r
5974 @param EDX Upper 32-bits of MSR value.\r
5975\r
5976 <b>Example usage</b>\r
5977 @code\r
5978 UINT64 Msr;\r
5979\r
5980 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);\r
5981 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);\r
5982 @endcode\r
a73ab083 5983 @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 5984**/\r
5985#define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01\r
5986\r
5987\r
5988/**\r
5989 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.\r
5990\r
5991 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)\r
5992 @param EAX Lower 32-bits of MSR value.\r
5993 @param EDX Upper 32-bits of MSR value.\r
5994\r
5995 <b>Example usage</b>\r
5996 @code\r
5997 UINT64 Msr;\r
5998\r
5999 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);\r
6000 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);\r
6001 @endcode\r
a73ab083 6002 @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 6003**/\r
6004#define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02\r
6005\r
6006\r
6007/**\r
6008 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.\r
6009\r
6010 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)\r
6011 @param EAX Lower 32-bits of MSR value.\r
6012 @param EDX Upper 32-bits of MSR value.\r
6013\r
6014 <b>Example usage</b>\r
6015 @code\r
6016 UINT64 Msr;\r
6017\r
6018 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);\r
6019 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);\r
6020 @endcode\r
a73ab083 6021 @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 6022**/\r
6023#define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03\r
6024\r
6025\r
6026/**\r
6027 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.\r
6028\r
6029 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)\r
6030 @param EAX Lower 32-bits of MSR value.\r
6031 @param EDX Upper 32-bits of MSR value.\r
6032\r
6033 <b>Example usage</b>\r
6034 @code\r
6035 UINT64 Msr;\r
6036\r
6037 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);\r
6038 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);\r
6039 @endcode\r
a73ab083 6040 @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 6041**/\r
6042#define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04\r
6043\r
6044\r
6045/**\r
6046 Package. Uncore C-box 16 perfmon box wide filter 0.\r
6047\r
6048 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)\r
6049 @param EAX Lower 32-bits of MSR value.\r
6050 @param EDX Upper 32-bits of MSR value.\r
6051\r
6052 <b>Example usage</b>\r
6053 @code\r
6054 UINT64 Msr;\r
6055\r
6056 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);\r
6057 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);\r
6058 @endcode\r
a73ab083 6059 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 6060**/\r
6061#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05\r
6062\r
6063\r
6064/**\r
6065 Package. Uncore C-box 16 perfmon box wide filter 1.\r
6066\r
6067 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)\r
6068 @param EAX Lower 32-bits of MSR value.\r
6069 @param EDX Upper 32-bits of MSR value.\r
6070\r
6071 <b>Example usage</b>\r
6072 @code\r
6073 UINT64 Msr;\r
6074\r
6075 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);\r
6076 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);\r
6077 @endcode\r
a73ab083 6078 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 6079**/\r
6080#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06\r
6081\r
6082\r
6083/**\r
6084 Package. Uncore C-box 16 perfmon box wide status.\r
6085\r
6086 @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)\r
6087 @param EAX Lower 32-bits of MSR value.\r
6088 @param EDX Upper 32-bits of MSR value.\r
6089\r
6090 <b>Example usage</b>\r
6091 @code\r
6092 UINT64 Msr;\r
6093\r
6094 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);\r
6095 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);\r
6096 @endcode\r
a73ab083 6097 @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 6098**/\r
6099#define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07\r
6100\r
6101\r
6102/**\r
6103 Package. Uncore C-box 16 perfmon counter 0.\r
6104\r
6105 @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)\r
6106 @param EAX Lower 32-bits of MSR value.\r
6107 @param EDX Upper 32-bits of MSR value.\r
6108\r
6109 <b>Example usage</b>\r
6110 @code\r
6111 UINT64 Msr;\r
6112\r
6113 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);\r
6114 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);\r
6115 @endcode\r
a73ab083 6116 @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.\r
c67b579c
MK		 6117**/\r
6118#define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08\r
6119\r
6120\r
6121/**\r
6122 Package. Uncore C-box 16 perfmon counter 1.\r
6123\r
6124 @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)\r
6125 @param EAX Lower 32-bits of MSR value.\r
6126 @param EDX Upper 32-bits of MSR value.\r
6127\r
6128 <b>Example usage</b>\r
6129 @code\r
6130 UINT64 Msr;\r
6131\r
6132 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);\r
6133 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);\r
6134 @endcode\r
a73ab083 6135 @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.\r
c67b579c
MK		 6136**/\r
6137#define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09\r
6138\r
6139\r
6140/**\r
6141 Package. Uncore C-box 16 perfmon counter 2.\r
6142\r
6143 @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)\r
6144 @param EAX Lower 32-bits of MSR value.\r
6145 @param EDX Upper 32-bits of MSR value.\r
6146\r
6147 <b>Example usage</b>\r
6148 @code\r
6149 UINT64 Msr;\r
6150\r
6151 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);\r
6152 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);\r
6153 @endcode\r
a73ab083 6154 @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.\r
c67b579c
MK		 6155**/\r
6156#define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A\r
6157\r
6158\r
6159/**\r
6160 Package. Uncore C-box 16 perfmon counter 3.\r
6161\r
6162 @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)\r
6163 @param EAX Lower 32-bits of MSR value.\r
6164 @param EDX Upper 32-bits of MSR value.\r
6165\r
6166 <b>Example usage</b>\r
6167 @code\r
6168 UINT64 Msr;\r
6169\r
6170 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);\r
6171 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);\r
6172 @endcode\r
a73ab083 6173 @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.\r
c67b579c
MK		 6174**/\r
6175#define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B\r
6176\r
6177\r
6178/**\r
6179 Package. Uncore C-box 17 perfmon for box-wide control.\r
6180\r
6181 @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)\r
6182 @param EAX Lower 32-bits of MSR value.\r
6183 @param EDX Upper 32-bits of MSR value.\r
6184\r
6185 <b>Example usage</b>\r
6186 @code\r
6187 UINT64 Msr;\r
6188\r
6189 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);\r
6190 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);\r
6191 @endcode\r
a73ab083 6192 @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.\r
c67b579c
MK		 6193**/\r
6194#define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10\r
6195\r
6196\r
6197/**\r
6198 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.\r
6199\r
6200 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)\r
6201 @param EAX Lower 32-bits of MSR value.\r
6202 @param EDX Upper 32-bits of MSR value.\r
6203\r
6204 <b>Example usage</b>\r
6205 @code\r
6206 UINT64 Msr;\r
6207\r
6208 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);\r
6209 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);\r
6210 @endcode\r
a73ab083 6211 @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.\r
c67b579c
MK		 6212**/\r
6213#define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11\r
6214\r
6215\r
6216/**\r
6217 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.\r
6218\r
6219 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)\r
6220 @param EAX Lower 32-bits of MSR value.\r
6221 @param EDX Upper 32-bits of MSR value.\r
6222\r
6223 <b>Example usage</b>\r
6224 @code\r
6225 UINT64 Msr;\r
6226\r
6227 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);\r
6228 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);\r
6229 @endcode\r
a73ab083 6230 @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.\r
c67b579c
MK		 6231**/\r
6232#define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12\r
6233\r
6234\r
6235/**\r
6236 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.\r
6237\r
6238 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)\r
6239 @param EAX Lower 32-bits of MSR value.\r
6240 @param EDX Upper 32-bits of MSR value.\r
6241\r
6242 <b>Example usage</b>\r
6243 @code\r
6244 UINT64 Msr;\r
6245\r
6246 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);\r
6247 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);\r
6248 @endcode\r
a73ab083 6249 @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.\r
c67b579c
MK		 6250**/\r
6251#define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13\r
6252\r
6253\r
6254/**\r
6255 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.\r
6256\r
6257 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)\r
6258 @param EAX Lower 32-bits of MSR value.\r
6259 @param EDX Upper 32-bits of MSR value.\r
6260\r
6261 <b>Example usage</b>\r
6262 @code\r
6263 UINT64 Msr;\r
6264\r
6265 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);\r
6266 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);\r
6267 @endcode\r
a73ab083 6268 @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.\r
c67b579c
MK		 6269**/\r
6270#define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14\r
6271\r
6272\r
6273/**\r
6274 Package. Uncore C-box 17 perfmon box wide filter 0.\r
6275\r
6276 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)\r
6277 @param EAX Lower 32-bits of MSR value.\r
6278 @param EDX Upper 32-bits of MSR value.\r
6279\r
6280 <b>Example usage</b>\r
6281 @code\r
6282 UINT64 Msr;\r
6283\r
6284 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);\r
6285 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);\r
6286 @endcode\r
a73ab083 6287 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.\r
c67b579c
MK		 6288**/\r
6289#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15\r
6290\r
6291\r
6292/**\r
6293 Package. Uncore C-box 17 perfmon box wide filter1.\r
6294\r
6295 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)\r
6296 @param EAX Lower 32-bits of MSR value.\r
6297 @param EDX Upper 32-bits of MSR value.\r
6298\r
6299 <b>Example usage</b>\r
6300 @code\r
6301 UINT64 Msr;\r
6302\r
6303 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);\r
6304 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);\r
6305 @endcode\r
a73ab083 6306 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.\r
c67b579c
MK		 6307**/\r
6308#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16\r
6309\r
6310/**\r
6311 Package. Uncore C-box 17 perfmon box wide status.\r
6312\r
6313 @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)\r
6314 @param EAX Lower 32-bits of MSR value.\r
6315 @param EDX Upper 32-bits of MSR value.\r
6316\r
6317 <b>Example usage</b>\r
6318 @code\r
6319 UINT64 Msr;\r
6320\r
6321 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);\r
6322 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);\r
6323 @endcode\r
a73ab083 6324 @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.\r
c67b579c
MK		 6325**/\r
6326#define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17\r
6327\r
6328\r
6329/**\r
6330 Package. Uncore C-box 17 perfmon counter n.\r
6331\r
6332 @param ECX MSR_HASWELL_E_C17_PMON_CTRn\r
6333 @param EAX Lower 32-bits of MSR value.\r
6334 @param EDX Upper 32-bits of MSR value.\r
6335\r
6336 <b>Example usage</b>\r
6337 @code\r
6338 UINT64 Msr;\r
6339\r
6340 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);\r
6341 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);\r
6342 @endcode\r
a73ab083
JF		 6343 @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.\r
6344 MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.\r
6345 MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.\r
6346 MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.\r
c67b579c
MK		 6347 @{\r
6348**/\r
6349#define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18\r
6350#define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19\r
6351#define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A\r
6352#define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B\r
6353/// @}\r
6354\r
6355#endif\r
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