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UefiCpuPkg/Include: Add Broadwell MSR include file
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / SandyBridgeMsr.h
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MK		 1/** @file\r
2 MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8.\r
21\r
22**/\r
23\r
24#ifndef __SANDY_BRIDGE_MSR_H__\r
25#define __SANDY_BRIDGE_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
29/**\r
30 Thread. SMI Counter (R/O).\r
31\r
32 @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)\r
33 @param EAX Lower 32-bits of MSR value.\r
34 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.\r
35 @param EDX Upper 32-bits of MSR value.\r
36 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.\r
37\r
38 <b>Example usage</b>\r
39 @code\r
40 MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr;\r
41\r
42 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);\r
43 @endcode\r
44**/\r
45#define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034\r
46\r
47/**\r
48 MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT\r
49**/\r
50typedef union {\r
51 ///\r
52 /// Individual bit fields\r
53 ///\r
54 struct {\r
55 ///\r
56 /// [Bits 31:0] SMI Count (R/O) Count SMIs.\r
57 ///\r
58 UINT32 SMICount:32;\r
59 UINT32 Reserved:32;\r
60 } Bits;\r
61 ///\r
62 /// All bit fields as a 32-bit value\r
63 ///\r
64 UINT32 Uint32;\r
65 ///\r
66 /// All bit fields as a 64-bit value\r
67 ///\r
68 UINT64 Uint64;\r
69} MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER;\r
70\r
71\r
72/**\r
73 Package. See http://biosbits.org.\r
74\r
75 @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)\r
76 @param EAX Lower 32-bits of MSR value.\r
77 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.\r
78 @param EDX Upper 32-bits of MSR value.\r
79 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.\r
80\r
81 <b>Example usage</b>\r
82 @code\r
83 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr;\r
84\r
85 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);\r
86 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);\r
87 @endcode\r
88**/\r
89#define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE\r
90\r
91/**\r
92 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO\r
93**/\r
94typedef union {\r
95 ///\r
96 /// Individual bit fields\r
97 ///\r
98 struct {\r
99 UINT32 Reserved1:8;\r
100 ///\r
101 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
102 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
103 /// MHz.\r
104 ///\r
105 UINT32 MaximumNonTurboRatio:8;\r
106 UINT32 Reserved2:12;\r
107 ///\r
108 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
109 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
110 /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
111 /// Turbo mode is disabled.\r
112 ///\r
113 UINT32 RatioLimit:1;\r
114 ///\r
115 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
116 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
117 /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
118 /// programmable.\r
119 ///\r
120 UINT32 TDPLimit:1;\r
121 UINT32 Reserved3:2;\r
122 UINT32 Reserved4:8;\r
123 ///\r
124 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
125 /// minimum ratio (maximum efficiency) that the processor can operates, in\r
126 /// units of 100MHz.\r
127 ///\r
128 UINT32 MaximumEfficiencyRatio:8;\r
129 UINT32 Reserved5:16;\r
130 } Bits;\r
131 ///\r
132 /// All bit fields as a 64-bit value\r
133 ///\r
134 UINT64 Uint64;\r
135} MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER;\r
136\r
137\r
138/**\r
139 Core. C-State Configuration Control (R/W) Note: C-state values are\r
140 processor specific C-state code names, unrelated to MWAIT extension C-state\r
141 parameters or ACPI CStates. See http://biosbits.org.\r
142\r
143 @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
144 @param EAX Lower 32-bits of MSR value.\r
145 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
146 @param EDX Upper 32-bits of MSR value.\r
147 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
148\r
149 <b>Example usage</b>\r
150 @code\r
151 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
152\r
153 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);\r
154 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
155 @endcode\r
156**/\r
157#define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
158\r
159/**\r
160 MSR information returned for MSR index\r
161 #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL\r
162**/\r
163typedef union {\r
164 ///\r
165 /// Individual bit fields\r
166 ///\r
167 struct {\r
168 ///\r
169 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
170 /// processor-specific C-state code name (consuming the least power). for\r
171 /// the package. The default is set as factory-configured package C-state\r
172 /// limit. The following C-state code name encodings are supported: 000b:\r
173 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:\r
174 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r
175 /// This field cannot be used to limit package C-state to C3.\r
176 ///\r
177 UINT32 Limit:3;\r
178 UINT32 Reserved1:7;\r
179 ///\r
180 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
181 /// IO_read instructions sent to IO register specified by\r
182 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
183 ///\r
184 UINT32 IO_MWAIT:1;\r
185 UINT32 Reserved2:4;\r
186 ///\r
187 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
188 /// until next reset.\r
189 ///\r
190 UINT32 CFGLock:1;\r
191 UINT32 Reserved3:9;\r
192 ///\r
193 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
194 /// will conditionally demote C6/C7 requests to C3 based on uncore\r
195 /// auto-demote information.\r
196 ///\r
197 UINT32 C3AutoDemotion:1;\r
198 ///\r
199 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
200 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
201 /// auto-demote information.\r
202 ///\r
203 UINT32 C1AutoDemotion:1;\r
204 ///\r
205 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r
206 /// demoted C3.\r
207 ///\r
208 UINT32 C3Undemotion:1;\r
209 ///\r
210 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r
211 /// demoted C1.\r
212 ///\r
213 UINT32 C1Undemotion:1;\r
214 UINT32 Reserved4:3;\r
215 UINT32 Reserved5:32;\r
216 } Bits;\r
217 ///\r
218 /// All bit fields as a 32-bit value\r
219 ///\r
220 UINT32 Uint32;\r
221 ///\r
222 /// All bit fields as a 64-bit value\r
223 ///\r
224 UINT64 Uint64;\r
225} MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
226\r
227\r
228/**\r
229 Core. Power Management IO Redirection in C-state (R/W) See\r
230 http://biosbits.org.\r
231\r
232 @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)\r
233 @param EAX Lower 32-bits of MSR value.\r
234 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.\r
235 @param EDX Upper 32-bits of MSR value.\r
236 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.\r
237\r
238 <b>Example usage</b>\r
239 @code\r
240 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
241\r
242 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);\r
243 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
244 @endcode\r
245**/\r
246#define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4\r
247\r
248/**\r
249 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE\r
250**/\r
251typedef union {\r
252 ///\r
253 /// Individual bit fields\r
254 ///\r
255 struct {\r
256 ///\r
257 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r
258 /// visible to software for IO redirection. If IO MWAIT Redirection is\r
259 /// enabled, reads to this address will be consumed by the power\r
260 /// management logic and decoded to MWAIT instructions. When IO port\r
261 /// address redirection is enabled, this is the IO port address reported\r
262 /// to the OS/software.\r
263 ///\r
264 UINT32 Lvl2Base:16;\r
265 ///\r
266 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
267 /// maximum C-State code name to be included when IO read to MWAIT\r
268 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3\r
269 /// is the max C-State to include 001b - C6 is the max C-State to include\r
270 /// 010b - C7 is the max C-State to include.\r
271 ///\r
272 UINT32 CStateRange:3;\r
273 UINT32 Reserved1:13;\r
274 UINT32 Reserved2:32;\r
275 } Bits;\r
276 ///\r
277 /// All bit fields as a 32-bit value\r
278 ///\r
279 UINT32 Uint32;\r
280 ///\r
281 /// All bit fields as a 64-bit value\r
282 ///\r
283 UINT64 Uint64;\r
284} MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER;\r
285\r
286\r
287/**\r
288 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
289 handler to handle unsuccessful read of this MSR.\r
290\r
291 @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)\r
292 @param EAX Lower 32-bits of MSR value.\r
293 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.\r
294 @param EDX Upper 32-bits of MSR value.\r
295 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.\r
296\r
297 <b>Example usage</b>\r
298 @code\r
299 MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr;\r
300\r
301 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);\r
302 AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);\r
303 @endcode\r
304**/\r
305#define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C\r
306\r
307/**\r
308 MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG\r
309**/\r
310typedef union {\r
311 ///\r
312 /// Individual bit fields\r
313 ///\r
314 struct {\r
315 ///\r
316 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
317 /// MSR, the configuration of AES instruction set availability is as\r
318 /// follows: 11b: AES instructions are not available until next RESET.\r
319 /// otherwise, AES instructions are available. Note, AES instruction set\r
320 /// is not available if read is unsuccessful. If the configuration is not\r
321 /// 01b, AES instruction can be mis-configured if a privileged agent\r
322 /// unintentionally writes 11b.\r
323 ///\r
324 UINT32 AESConfiguration:2;\r
325 UINT32 Reserved1:30;\r
326 UINT32 Reserved2:32;\r
327 } Bits;\r
328 ///\r
329 /// All bit fields as a 32-bit value\r
330 ///\r
331 UINT32 Uint32;\r
332 ///\r
333 /// All bit fields as a 64-bit value\r
334 ///\r
335 UINT64 Uint64;\r
336} MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER;\r
337\r
338\r
339/**\r
340 Core. See Table 35-2; If CPUID.0AH:EAX[15:8] = 8.\r
341\r
342 @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn\r
343 @param EAX Lower 32-bits of MSR value.\r
344 @param EDX Upper 32-bits of MSR value.\r
345\r
346 <b>Example usage</b>\r
347 @code\r
348 UINT64 Msr;\r
349\r
350 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);\r
351 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);\r
352 @endcode\r
353 @{\r
354**/\r
355#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A\r
356#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B\r
357#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C\r
358#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D\r
359/// @}\r
360\r
361\r
362/**\r
363 Package.\r
364\r
365 @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)\r
366 @param EAX Lower 32-bits of MSR value.\r
367 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.\r
368 @param EDX Upper 32-bits of MSR value.\r
369 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.\r
370\r
371 <b>Example usage</b>\r
372 @code\r
373 MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr;\r
374\r
375 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);\r
376 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);\r
377 @endcode\r
378**/\r
379#define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198\r
380\r
381/**\r
382 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS\r
383**/\r
384typedef union {\r
385 ///\r
386 /// Individual bit fields\r
387 ///\r
388 struct {\r
389 UINT32 Reserved1:32;\r
390 ///\r
391 /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed\r
392 /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).\r
393 ///\r
394 UINT32 CoreVoltage:16;\r
395 UINT32 Reserved2:16;\r
396 } Bits;\r
397 ///\r
398 /// All bit fields as a 64-bit value\r
399 ///\r
400 UINT64 Uint64;\r
401} MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER;\r
402\r
403\r
404/**\r
405 Thread. Clock Modulation (R/W) See Table 35-2 IA32_CLOCK_MODULATION MSR was\r
406 originally named IA32_THERM_CONTROL MSR.\r
407\r
408 @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)\r
409 @param EAX Lower 32-bits of MSR value.\r
410 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.\r
411 @param EDX Upper 32-bits of MSR value.\r
412 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.\r
413\r
414 <b>Example usage</b>\r
415 @code\r
416 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr;\r
417\r
418 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);\r
419 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);\r
420 @endcode\r
421**/\r
422#define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A\r
423\r
424/**\r
425 MSR information returned for MSR index\r
426 #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION\r
427**/\r
428typedef union {\r
429 ///\r
430 /// Individual bit fields\r
431 ///\r
432 struct {\r
433 ///\r
434 /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%\r
435 /// increment.\r
436 ///\r
437 UINT32 OnDemandClockModulationDutyCycle:4;\r
438 ///\r
439 /// [Bit 4] On demand Clock Modulation Enable (R/W).\r
440 ///\r
441 UINT32 OnDemandClockModulationEnable:1;\r
442 UINT32 Reserved1:27;\r
443 UINT32 Reserved2:32;\r
444 } Bits;\r
445 ///\r
446 /// All bit fields as a 32-bit value\r
447 ///\r
448 UINT32 Uint32;\r
449 ///\r
450 /// All bit fields as a 64-bit value\r
451 ///\r
452 UINT64 Uint64;\r
453} MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER;\r
454\r
455\r
456/**\r
457 Enable Misc. Processor Features (R/W) Allows a variety of processor\r
458 functions to be enabled and disabled.\r
459\r
460 @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)\r
461 @param EAX Lower 32-bits of MSR value.\r
462 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.\r
463 @param EDX Upper 32-bits of MSR value.\r
464 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.\r
465\r
466 <b>Example usage</b>\r
467 @code\r
468 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr;\r
469\r
470 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);\r
471 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);\r
472 @endcode\r
473**/\r
474#define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0\r
475\r
476/**\r
477 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE\r
478**/\r
479typedef union {\r
480 ///\r
481 /// Individual bit fields\r
482 ///\r
483 struct {\r
484 ///\r
485 /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.\r
486 ///\r
487 UINT32 FastStrings:1;\r
488 UINT32 Reserved1:6;\r
489 ///\r
490 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.\r
491 ///\r
492 UINT32 PerformanceMonitoring:1;\r
493 UINT32 Reserved2:3;\r
494 ///\r
495 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.\r
496 ///\r
497 UINT32 BTS:1;\r
498 ///\r
499 /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See\r
500 /// Table 35-2.\r
501 ///\r
502 UINT32 PEBS:1;\r
503 UINT32 Reserved3:3;\r
504 ///\r
505 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
506 /// Table 35-2.\r
507 ///\r
508 UINT32 EIST:1;\r
509 UINT32 Reserved4:1;\r
510 ///\r
511 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.\r
512 ///\r
513 UINT32 MONITOR:1;\r
514 UINT32 Reserved5:3;\r
515 ///\r
516 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.\r
517 ///\r
518 UINT32 LimitCpuidMaxval:1;\r
519 ///\r
520 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.\r
521 ///\r
522 UINT32 xTPR_Message_Disable:1;\r
523 UINT32 Reserved6:8;\r
524 UINT32 Reserved7:2;\r
525 ///\r
526 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.\r
527 ///\r
528 UINT32 XD:1;\r
529 UINT32 Reserved8:3;\r
530 ///\r
531 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
532 /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
533 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
534 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
535 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
536 /// the power-on default value is used by BIOS to detect hardware support\r
537 /// of turbo mode. If power-on default value is 1, turbo mode is available\r
538 /// in the processor. If power-on default value is 0, turbo mode is not\r
539 /// available.\r
540 ///\r
541 UINT32 TurboModeDisable:1;\r
542 UINT32 Reserved9:25;\r
543 } Bits;\r
544 ///\r
545 /// All bit fields as a 64-bit value\r
546 ///\r
547 UINT64 Uint64;\r
548} MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER;\r
549\r
550\r
551/**\r
552 Unique.\r
553\r
554 @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)\r
555 @param EAX Lower 32-bits of MSR value.\r
556 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
557 @param EDX Upper 32-bits of MSR value.\r
558 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
559\r
560 <b>Example usage</b>\r
561 @code\r
562 MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;\r
563\r
564 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);\r
565 AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);\r
566 @endcode\r
567**/\r
568#define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
569\r
570/**\r
571 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET\r
572**/\r
573typedef union {\r
574 ///\r
575 /// Individual bit fields\r
576 ///\r
577 struct {\r
578 UINT32 Reserved1:16;\r
579 ///\r
580 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r
581 /// PROCHOT# will be asserted. The value is degree C.\r
582 ///\r
583 UINT32 TemperatureTarget:8;\r
584 UINT32 Reserved2:8;\r
585 UINT32 Reserved3:32;\r
586 } Bits;\r
587 ///\r
588 /// All bit fields as a 32-bit value\r
589 ///\r
590 UINT32 Uint32;\r
591 ///\r
592 /// All bit fields as a 64-bit value\r
593 ///\r
594 UINT64 Uint64;\r
595} MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r
596\r
597\r
598/**\r
599 Miscellaneous Feature Control (R/W).\r
600\r
601 @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)\r
602 @param EAX Lower 32-bits of MSR value.\r
603 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.\r
604 @param EDX Upper 32-bits of MSR value.\r
605 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.\r
606\r
607 <b>Example usage</b>\r
608 @code\r
609 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr;\r
610\r
611 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);\r
612 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);\r
613 @endcode\r
614**/\r
615#define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4\r
616\r
617/**\r
618 MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL\r
619**/\r
620typedef union {\r
621 ///\r
622 /// Individual bit fields\r
623 ///\r
624 struct {\r
625 ///\r
626 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
627 /// L2 hardware prefetcher, which fetches additional lines of code or data\r
628 /// into the L2 cache.\r
629 ///\r
630 UINT32 L2HardwarePrefetcherDisable:1;\r
631 ///\r
632 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r
633 /// disables the adjacent cache line prefetcher, which fetches the cache\r
634 /// line that comprises a cache line pair (128 bytes).\r
635 ///\r
636 UINT32 L2AdjacentCacheLinePrefetcherDisable:1;\r
637 ///\r
638 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
639 /// the L1 data cache prefetcher, which fetches the next cache line into\r
640 /// L1 data cache.\r
641 ///\r
642 UINT32 DCUHardwarePrefetcherDisable:1;\r
643 ///\r
644 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r
645 /// data cache IP prefetcher, which uses sequential load history (based on\r
646 /// instruction Pointer of previous loads) to determine whether to\r
647 /// prefetch additional lines.\r
648 ///\r
649 UINT32 DCUIPPrefetcherDisable:1;\r
650 UINT32 Reserved1:28;\r
651 UINT32 Reserved2:32;\r
652 } Bits;\r
653 ///\r
654 /// All bit fields as a 32-bit value\r
655 ///\r
656 UINT32 Uint32;\r
657 ///\r
658 /// All bit fields as a 64-bit value\r
659 ///\r
660 UINT64 Uint64;\r
661} MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER;\r
662\r
663\r
664/**\r
665 Thread. Offcore Response Event Select Register (R/W).\r
666\r
667 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)\r
668 @param EAX Lower 32-bits of MSR value.\r
669 @param EDX Upper 32-bits of MSR value.\r
670\r
671 <b>Example usage</b>\r
672 @code\r
673 UINT64 Msr;\r
674\r
675 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);\r
676 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);\r
677 @endcode\r
678**/\r
679#define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6\r
680\r
681\r
682/**\r
683 Thread. Offcore Response Event Select Register (R/W).\r
684\r
685 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)\r
686 @param EAX Lower 32-bits of MSR value.\r
687 @param EDX Upper 32-bits of MSR value.\r
688\r
689 <b>Example usage</b>\r
690 @code\r
691 UINT64 Msr;\r
692\r
693 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);\r
694 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);\r
695 @endcode\r
696**/\r
697#define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7\r
698\r
699\r
700/**\r
701 See http://biosbits.org.\r
702\r
703 @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)\r
704 @param EAX Lower 32-bits of MSR value.\r
705 @param EDX Upper 32-bits of MSR value.\r
706\r
707 <b>Example usage</b>\r
708 @code\r
709 UINT64 Msr;\r
710\r
711 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);\r
712 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);\r
713 @endcode\r
714**/\r
715#define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA\r
716\r
717\r
718/**\r
719 Thread. Last Branch Record Filtering Select Register (R/W) See Section\r
720 17.6.2, "Filtering of Last Branch Records.".\r
721\r
722 @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)\r
723 @param EAX Lower 32-bits of MSR value.\r
724 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.\r
725 @param EDX Upper 32-bits of MSR value.\r
726 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.\r
727\r
728 <b>Example usage</b>\r
729 @code\r
730 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr;\r
731\r
732 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);\r
733 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);\r
734 @endcode\r
735**/\r
736#define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8\r
737\r
738/**\r
739 MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT\r
740**/\r
741typedef union {\r
742 ///\r
743 /// Individual bit fields\r
744 ///\r
745 struct {\r
746 ///\r
747 /// [Bit 0] CPL_EQ_0.\r
748 ///\r
749 UINT32 CPL_EQ_0:1;\r
750 ///\r
751 /// [Bit 1] CPL_NEQ_0.\r
752 ///\r
753 UINT32 CPL_NEQ_0:1;\r
754 ///\r
755 /// [Bit 2] JCC.\r
756 ///\r
757 UINT32 JCC:1;\r
758 ///\r
759 /// [Bit 3] NEAR_REL_CALL.\r
760 ///\r
761 UINT32 NEAR_REL_CALL:1;\r
762 ///\r
763 /// [Bit 4] NEAR_IND_CALL.\r
764 ///\r
765 UINT32 NEAR_IND_CALL:1;\r
766 ///\r
767 /// [Bit 5] NEAR_RET.\r
768 ///\r
769 UINT32 NEAR_RET:1;\r
770 ///\r
771 /// [Bit 6] NEAR_IND_JMP.\r
772 ///\r
773 UINT32 NEAR_IND_JMP:1;\r
774 ///\r
775 /// [Bit 7] NEAR_REL_JMP.\r
776 ///\r
777 UINT32 NEAR_REL_JMP:1;\r
778 ///\r
779 /// [Bit 8] FAR_BRANCH.\r
780 ///\r
781 UINT32 FAR_BRANCH:1;\r
782 UINT32 Reserved1:23;\r
783 UINT32 Reserved2:32;\r
784 } Bits;\r
785 ///\r
786 /// All bit fields as a 32-bit value\r
787 ///\r
788 UINT32 Uint32;\r
789 ///\r
790 /// All bit fields as a 64-bit value\r
791 ///\r
792 UINT64 Uint64;\r
793} MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER;\r
794\r
795\r
796/**\r
797 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
798 that points to the MSR containing the most recent branch record. See\r
799 MSR_LASTBRANCH_0_FROM_IP (at 680H).\r
800\r
801 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)\r
802 @param EAX Lower 32-bits of MSR value.\r
803 @param EDX Upper 32-bits of MSR value.\r
804\r
805 <b>Example usage</b>\r
806 @code\r
807 UINT64 Msr;\r
808\r
809 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);\r
810 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);\r
811 @endcode\r
812**/\r
813#define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9\r
814\r
815\r
816/**\r
817 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r
818 last branch instruction that the processor executed prior to the last\r
819 exception that was generated or the last interrupt that was handled.\r
820\r
821 @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)\r
822 @param EAX Lower 32-bits of MSR value.\r
823 @param EDX Upper 32-bits of MSR value.\r
824\r
825 <b>Example usage</b>\r
826 @code\r
827 UINT64 Msr;\r
828\r
829 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);\r
830 @endcode\r
831**/\r
832#define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD\r
833\r
834\r
835/**\r
836 Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r
837 to the target of the last branch instruction that the processor executed\r
838 prior to the last exception that was generated or the last interrupt that\r
839 was handled.\r
840\r
841 @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)\r
842 @param EAX Lower 32-bits of MSR value.\r
843 @param EDX Upper 32-bits of MSR value.\r
844\r
845 <b>Example usage</b>\r
846 @code\r
847 UINT64 Msr;\r
848\r
849 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);\r
850 @endcode\r
851**/\r
852#define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE\r
853\r
854\r
855/**\r
856 Core. See http://biosbits.org.\r
857\r
858 @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)\r
859 @param EAX Lower 32-bits of MSR value.\r
860 @param EDX Upper 32-bits of MSR value.\r
861\r
862 <b>Example usage</b>\r
863 @code\r
864 UINT64 Msr;\r
865\r
866 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);\r
867 AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);\r
868 @endcode\r
869**/\r
870#define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC\r
871\r
872\r
873/**\r
874 Package. Always 0 (CMCI not supported).\r
875\r
876 @param ECX MSR_SANDY_BRIDGE_MC4_CTL2 (0x00000284)\r
877 @param EAX Lower 32-bits of MSR value.\r
878 @param EDX Upper 32-bits of MSR value.\r
879\r
880 <b>Example usage</b>\r
881 @code\r
882 UINT64 Msr;\r
883\r
884 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2);\r
885 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2, Msr);\r
886 @endcode\r
887**/\r
888#define MSR_SANDY_BRIDGE_MC4_CTL2 0x00000284\r
889\r
890\r
891/**\r
892 See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".\r
893\r
894 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
895 @param EAX Lower 32-bits of MSR value.\r
896 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER.\r
897 @param EDX Upper 32-bits of MSR value.\r
898 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER.\r
899\r
900 <b>Example usage</b>\r
901 @code\r
902 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;\r
903\r
904 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS);\r
905 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);\r
906 @endcode\r
907**/\r
908#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
909\r
910/**\r
911 MSR information returned for MSR index\r
912 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS\r
913**/\r
914typedef union {\r
915 ///\r
916 /// Individual bit fields\r
917 ///\r
918 struct {\r
919 ///\r
920 /// [Bit 0] Thread. Ovf_PMC0.\r
921 ///\r
922 UINT32 Ovf_PMC0:1;\r
923 ///\r
924 /// [Bit 1] Thread. Ovf_PMC1.\r
925 ///\r
926 UINT32 Ovf_PMC1:1;\r
927 ///\r
928 /// [Bit 2] Thread. Ovf_PMC2.\r
929 ///\r
930 UINT32 Ovf_PMC2:1;\r
931 ///\r
932 /// [Bit 3] Thread. Ovf_PMC3.\r
933 ///\r
934 UINT32 Ovf_PMC3:1;\r
935 ///\r
936 /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
937 ///\r
938 UINT32 Ovf_PMC4:1;\r
939 ///\r
940 /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
941 ///\r
942 UINT32 Ovf_PMC5:1;\r
943 ///\r
944 /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
945 ///\r
946 UINT32 Ovf_PMC6:1;\r
947 ///\r
948 /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
949 ///\r
950 UINT32 Ovf_PMC7:1;\r
951 UINT32 Reserved1:24;\r
952 ///\r
953 /// [Bit 32] Thread. Ovf_FixedCtr0.\r
954 ///\r
955 UINT32 Ovf_FixedCtr0:1;\r
956 ///\r
957 /// [Bit 33] Thread. Ovf_FixedCtr1.\r
958 ///\r
959 UINT32 Ovf_FixedCtr1:1;\r
960 ///\r
961 /// [Bit 34] Thread. Ovf_FixedCtr2.\r
962 ///\r
963 UINT32 Ovf_FixedCtr2:1;\r
964 UINT32 Reserved2:26;\r
965 ///\r
966 /// [Bit 61] Thread. Ovf_Uncore.\r
967 ///\r
968 UINT32 Ovf_Uncore:1;\r
969 ///\r
970 /// [Bit 62] Thread. Ovf_BufDSSAVE.\r
971 ///\r
972 UINT32 Ovf_BufDSSAVE:1;\r
973 ///\r
974 /// [Bit 63] Thread. CondChgd.\r
975 ///\r
976 UINT32 CondChgd:1;\r
977 } Bits;\r
978 ///\r
979 /// All bit fields as a 64-bit value\r
980 ///\r
981 UINT64 Uint64;\r
982} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER;\r
983\r
984\r
985/**\r
986 Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
987 Facilities.".\r
988\r
989 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r
990 @param EAX Lower 32-bits of MSR value.\r
991 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
992 @param EDX Upper 32-bits of MSR value.\r
993 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
994\r
995 <b>Example usage</b>\r
996 @code\r
997 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r
998\r
999 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);\r
1000 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r
1001 @endcode\r
1002**/\r
1003#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
1004\r
1005/**\r
1006 MSR information returned for MSR index\r
1007 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL\r
1008**/\r
1009typedef union {\r
1010 ///\r
1011 /// Individual bit fields\r
1012 ///\r
1013 struct {\r
1014 ///\r
1015 /// [Bit 0] Thread. Set 1 to enable PMC0 to count.\r
1016 ///\r
1017 UINT32 PCM0_EN:1;\r
1018 ///\r
1019 /// [Bit 1] Thread. Set 1 to enable PMC1 to count.\r
1020 ///\r
1021 UINT32 PCM1_EN:1;\r
1022 ///\r
1023 /// [Bit 2] Thread. Set 1 to enable PMC2 to count.\r
1024 ///\r
1025 UINT32 PCM2_EN:1;\r
1026 ///\r
1027 /// [Bit 3] Thread. Set 1 to enable PMC3 to count.\r
1028 ///\r
1029 UINT32 PCM3_EN:1;\r
1030 ///\r
1031 /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >\r
1032 /// 4).\r
1033 ///\r
1034 UINT32 PCM4_EN:1;\r
1035 ///\r
1036 /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >\r
1037 /// 5).\r
1038 ///\r
1039 UINT32 PCM5_EN:1;\r
1040 ///\r
1041 /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >\r
1042 /// 6).\r
1043 ///\r
1044 UINT32 PCM6_EN:1;\r
1045 ///\r
1046 /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >\r
1047 /// 7).\r
1048 ///\r
1049 UINT32 PCM7_EN:1;\r
1050 UINT32 Reserved1:24;\r
1051 ///\r
1052 /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.\r
1053 ///\r
1054 UINT32 FIXED_CTR0:1;\r
1055 ///\r
1056 /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.\r
1057 ///\r
1058 UINT32 FIXED_CTR1:1;\r
1059 ///\r
1060 /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.\r
1061 ///\r
1062 UINT32 FIXED_CTR2:1;\r
1063 UINT32 Reserved2:29;\r
1064 } Bits;\r
1065 ///\r
1066 /// All bit fields as a 64-bit value\r
1067 ///\r
1068 UINT64 Uint64;\r
1069} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER;\r
1070\r
1071\r
1072/**\r
1073 See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".\r
1074\r
1075 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
1076 @param EAX Lower 32-bits of MSR value.\r
1077 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
1078 @param EDX Upper 32-bits of MSR value.\r
1079 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
1080\r
1081 <b>Example usage</b>\r
1082 @code\r
1083 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r
1084\r
1085 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);\r
1086 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
1087 @endcode\r
1088**/\r
1089#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
1090\r
1091/**\r
1092 MSR information returned for MSR index\r
1093 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL\r
1094**/\r
1095typedef union {\r
1096 ///\r
1097 /// Individual bit fields\r
1098 ///\r
1099 struct {\r
1100 ///\r
1101 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
1102 ///\r
1103 UINT32 Ovf_PMC0:1;\r
1104 ///\r
1105 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
1106 ///\r
1107 UINT32 Ovf_PMC1:1;\r
1108 ///\r
1109 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
1110 ///\r
1111 UINT32 Ovf_PMC2:1;\r
1112 ///\r
1113 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
1114 ///\r
1115 UINT32 Ovf_PMC3:1;\r
1116 ///\r
1117 /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
1118 ///\r
1119 UINT32 Ovf_PMC4:1;\r
1120 ///\r
1121 /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
1122 ///\r
1123 UINT32 Ovf_PMC5:1;\r
1124 ///\r
1125 /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
1126 ///\r
1127 UINT32 Ovf_PMC6:1;\r
1128 ///\r
1129 /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
1130 ///\r
1131 UINT32 Ovf_PMC7:1;\r
1132 UINT32 Reserved1:24;\r
1133 ///\r
1134 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
1135 ///\r
1136 UINT32 Ovf_FixedCtr0:1;\r
1137 ///\r
1138 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
1139 ///\r
1140 UINT32 Ovf_FixedCtr1:1;\r
1141 ///\r
1142 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
1143 ///\r
1144 UINT32 Ovf_FixedCtr2:1;\r
1145 UINT32 Reserved2:26;\r
1146 ///\r
1147 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
1148 ///\r
1149 UINT32 Ovf_Uncore:1;\r
1150 ///\r
1151 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
1152 ///\r
1153 UINT32 Ovf_BufDSSAVE:1;\r
1154 ///\r
1155 /// [Bit 63] Thread. Set 1 to clear CondChgd.\r
1156 ///\r
1157 UINT32 CondChgd:1;\r
1158 } Bits;\r
1159 ///\r
1160 /// All bit fields as a 64-bit value\r
1161 ///\r
1162 UINT64 Uint64;\r
1163} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
1164\r
1165\r
1166/**\r
1167 Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".\r
1168\r
1169 @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)\r
1170 @param EAX Lower 32-bits of MSR value.\r
1171 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.\r
1172 @param EDX Upper 32-bits of MSR value.\r
1173 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.\r
1174\r
1175 <b>Example usage</b>\r
1176 @code\r
1177 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr;\r
1178\r
1179 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);\r
1180 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);\r
1181 @endcode\r
1182**/\r
1183#define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1\r
1184\r
1185/**\r
1186 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE\r
1187**/\r
1188typedef union {\r
1189 ///\r
1190 /// Individual bit fields\r
1191 ///\r
1192 struct {\r
1193 ///\r
1194 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
1195 ///\r
1196 UINT32 PEBS_EN_PMC0:1;\r
1197 ///\r
1198 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
1199 ///\r
1200 UINT32 PEBS_EN_PMC1:1;\r
1201 ///\r
1202 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
1203 ///\r
1204 UINT32 PEBS_EN_PMC2:1;\r
1205 ///\r
1206 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
1207 ///\r
1208 UINT32 PEBS_EN_PMC3:1;\r
1209 UINT32 Reserved1:28;\r
1210 ///\r
1211 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
1212 ///\r
1213 UINT32 LL_EN_PMC0:1;\r
1214 ///\r
1215 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
1216 ///\r
1217 UINT32 LL_EN_PMC1:1;\r
1218 ///\r
1219 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
1220 ///\r
1221 UINT32 LL_EN_PMC2:1;\r
1222 ///\r
1223 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
1224 ///\r
1225 UINT32 LL_EN_PMC3:1;\r
1226 UINT32 Reserved2:27;\r
1227 ///\r
1228 /// [Bit 63] Enable Precise Store. (R/W).\r
1229 ///\r
1230 UINT32 PS_EN:1;\r
1231 } Bits;\r
1232 ///\r
1233 /// All bit fields as a 64-bit value\r
1234 ///\r
1235 UINT64 Uint64;\r
1236} MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER;\r
1237\r
1238\r
1239/**\r
1240 Thread. see See Section 18.7.1.2, "Load Latency Performance Monitoring\r
1241 Facility.".\r
1242\r
1243 @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)\r
1244 @param EAX Lower 32-bits of MSR value.\r
1245 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.\r
1246 @param EDX Upper 32-bits of MSR value.\r
1247 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.\r
1248\r
1249 <b>Example usage</b>\r
1250 @code\r
1251 MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr;\r
1252\r
1253 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);\r
1254 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);\r
1255 @endcode\r
1256**/\r
1257#define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6\r
1258\r
1259/**\r
1260 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT\r
1261**/\r
1262typedef union {\r
1263 ///\r
1264 /// Individual bit fields\r
1265 ///\r
1266 struct {\r
1267 ///\r
1268 /// [Bits 15:0] Minimum threshold latency value of tagged load operation\r
1269 /// that will be counted. (R/W).\r
1270 ///\r
1271 UINT32 MinimumThreshold:16;\r
1272 UINT32 Reserved1:16;\r
1273 UINT32 Reserved2:32;\r
1274 } Bits;\r
1275 ///\r
1276 /// All bit fields as a 32-bit value\r
1277 ///\r
1278 UINT32 Uint32;\r
1279 ///\r
1280 /// All bit fields as a 64-bit value\r
1281 ///\r
1282 UINT64 Uint64;\r
1283} MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER;\r
1284\r
1285\r
1286/**\r
1287 Package. Note: C-state values are processor specific C-state code names,\r
1288 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
1289 Residency Counter. (R/O) Value since last reset that this package is in\r
1290 processor-specific C3 states. Count at the same frequency as the TSC.\r
1291\r
1292 @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)\r
1293 @param EAX Lower 32-bits of MSR value.\r
1294 @param EDX Upper 32-bits of MSR value.\r
1295\r
1296 <b>Example usage</b>\r
1297 @code\r
1298 UINT64 Msr;\r
1299\r
1300 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);\r
1301 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);\r
1302 @endcode\r
1303**/\r
1304#define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8\r
1305\r
1306\r
1307/**\r
1308 Package. Note: C-state values are processor specific C-state code names,\r
1309 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
1310 Residency Counter. (R/O) Value since last reset that this package is in\r
1311 processor-specific C6 states. Count at the same frequency as the TSC.\r
1312\r
1313 @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)\r
1314 @param EAX Lower 32-bits of MSR value.\r
1315 @param EDX Upper 32-bits of MSR value.\r
1316\r
1317 <b>Example usage</b>\r
1318 @code\r
1319 UINT64 Msr;\r
1320\r
1321 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);\r
1322 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);\r
1323 @endcode\r
1324**/\r
1325#define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9\r
1326\r
1327\r
1328/**\r
1329 Package. Note: C-state values are processor specific C-state code names,\r
1330 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7\r
1331 Residency Counter. (R/O) Value since last reset that this package is in\r
1332 processor-specific C7 states. Count at the same frequency as the TSC.\r
1333\r
1334 @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)\r
1335 @param EAX Lower 32-bits of MSR value.\r
1336 @param EDX Upper 32-bits of MSR value.\r
1337\r
1338 <b>Example usage</b>\r
1339 @code\r
1340 UINT64 Msr;\r
1341\r
1342 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);\r
1343 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);\r
1344 @endcode\r
1345**/\r
1346#define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA\r
1347\r
1348\r
1349/**\r
1350 Core. Note: C-state values are processor specific C-state code names,\r
1351 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r
1352 Residency Counter. (R/O) Value since last reset that this core is in\r
1353 processor-specific C3 states. Count at the same frequency as the TSC.\r
1354\r
1355 @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)\r
1356 @param EAX Lower 32-bits of MSR value.\r
1357 @param EDX Upper 32-bits of MSR value.\r
1358\r
1359 <b>Example usage</b>\r
1360 @code\r
1361 UINT64 Msr;\r
1362\r
1363 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);\r
1364 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);\r
1365 @endcode\r
1366**/\r
1367#define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC\r
1368\r
1369\r
1370/**\r
1371 Core. Note: C-state values are processor specific C-state code names,\r
1372 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r
1373 Residency Counter. (R/O) Value since last reset that this core is in\r
1374 processor-specific C6 states. Count at the same frequency as the TSC.\r
1375\r
1376 @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)\r
1377 @param EAX Lower 32-bits of MSR value.\r
1378 @param EDX Upper 32-bits of MSR value.\r
1379\r
1380 <b>Example usage</b>\r
1381 @code\r
1382 UINT64 Msr;\r
1383\r
1384 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);\r
1385 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);\r
1386 @endcode\r
1387**/\r
1388#define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD\r
1389\r
1390\r
1391/**\r
1392 Core. Note: C-state values are processor specific C-state code names,\r
1393 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7\r
1394 Residency Counter. (R/O) Value since last reset that this core is in\r
1395 processor-specific C7 states. Count at the same frequency as the TSC.\r
1396\r
1397 @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)\r
1398 @param EAX Lower 32-bits of MSR value.\r
1399 @param EDX Upper 32-bits of MSR value.\r
1400\r
1401 <b>Example usage</b>\r
1402 @code\r
1403 UINT64 Msr;\r
1404\r
1405 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);\r
1406 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);\r
1407 @endcode\r
1408**/\r
1409#define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE\r
1410\r
1411\r
1412/**\r
1413 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
1414\r
1415 @param ECX MSR_SANDY_BRIDGE_MC4_CTL (0x00000410)\r
1416 @param EAX Lower 32-bits of MSR value.\r
1417 Described by the type MSR_SANDY_BRIDGE_MC4_CTL_REGISTER.\r
1418 @param EDX Upper 32-bits of MSR value.\r
1419 Described by the type MSR_SANDY_BRIDGE_MC4_CTL_REGISTER.\r
1420\r
1421 <b>Example usage</b>\r
1422 @code\r
1423 MSR_SANDY_BRIDGE_MC4_CTL_REGISTER Msr;\r
1424\r
1425 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL);\r
1426 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL, Msr.Uint64);\r
1427 @endcode\r
1428**/\r
1429#define MSR_SANDY_BRIDGE_MC4_CTL 0x00000410\r
1430\r
1431/**\r
1432 MSR information returned for MSR index #MSR_SANDY_BRIDGE_MC4_CTL\r
1433**/\r
1434typedef union {\r
1435 ///\r
1436 /// Individual bit fields\r
1437 ///\r
1438 struct {\r
1439 ///\r
1440 /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU\r
1441 /// hardware detected errors.\r
1442 ///\r
1443 UINT32 PCUHardwareError:1;\r
1444 ///\r
1445 /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU\r
1446 /// controller detected errors.\r
1447 ///\r
1448 UINT32 PCUControllerError:1;\r
1449 ///\r
1450 /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU\r
1451 /// firmware detected errors.\r
1452 ///\r
1453 UINT32 PCUFirmwareError:1;\r
1454 UINT32 Reserved1:29;\r
1455 UINT32 Reserved2:32;\r
1456 } Bits;\r
1457 ///\r
1458 /// All bit fields as a 32-bit value\r
1459 ///\r
1460 UINT32 Uint32;\r
1461 ///\r
1462 /// All bit fields as a 64-bit value\r
1463 ///\r
1464 UINT64 Uint64;\r
1465} MSR_SANDY_BRIDGE_MC4_CTL_REGISTER;\r
1466\r
1467\r
1468/**\r
1469 Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.\r
1470\r
1471 @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
1472 @param EAX Lower 32-bits of MSR value.\r
1473 @param EDX Upper 32-bits of MSR value.\r
1474\r
1475 <b>Example usage</b>\r
1476 @code\r
1477 UINT64 Msr;\r
1478\r
1479 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);\r
1480 @endcode\r
1481**/\r
1482#define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
1483\r
1484\r
1485/**\r
1486 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
1487 "RAPL Interfaces.".\r
1488\r
1489 @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)\r
1490 @param EAX Lower 32-bits of MSR value.\r
1491 @param EDX Upper 32-bits of MSR value.\r
1492\r
1493 <b>Example usage</b>\r
1494 @code\r
1495 UINT64 Msr;\r
1496\r
1497 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);\r
1498 @endcode\r
1499**/\r
1500#define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606\r
1501\r
1502\r
1503/**\r
1504 Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r
1505 processor specific C-state code names, unrelated to MWAIT extension C-state\r
1506 parameters or ACPI CStates.\r
1507\r
1508 @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)\r
1509 @param EAX Lower 32-bits of MSR value.\r
1510 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.\r
1511 @param EDX Upper 32-bits of MSR value.\r
1512 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.\r
1513\r
1514 <b>Example usage</b>\r
1515 @code\r
1516 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr;\r
1517\r
1518 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);\r
1519 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);\r
1520 @endcode\r
1521**/\r
1522#define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A\r
1523\r
1524/**\r
1525 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL\r
1526**/\r
1527typedef union {\r
1528 ///\r
1529 /// Individual bit fields\r
1530 ///\r
1531 struct {\r
1532 ///\r
1533 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
1534 /// that should be used to decide if the package should be put into a\r
1535 /// package C3 state.\r
1536 ///\r
1537 UINT32 TimeLimit:10;\r
1538 ///\r
1539 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
1540 /// unit of the interrupt response time limit. The following time unit\r
1541 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
1542 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
1543 ///\r
1544 UINT32 TimeUnit:3;\r
1545 UINT32 Reserved1:2;\r
1546 ///\r
1547 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
1548 /// valid and can be used by the processor for package C-sate management.\r
1549 ///\r
1550 UINT32 Valid:1;\r
1551 UINT32 Reserved2:16;\r
1552 UINT32 Reserved3:32;\r
1553 } Bits;\r
1554 ///\r
1555 /// All bit fields as a 32-bit value\r
1556 ///\r
1557 UINT32 Uint32;\r
1558 ///\r
1559 /// All bit fields as a 64-bit value\r
1560 ///\r
1561 UINT64 Uint64;\r
1562} MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER;\r
1563\r
1564\r
1565/**\r
1566 Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the\r
1567 budget allocated for the package to exit from C6 to a C0 state, where\r
1568 interrupt request can be delivered to the core and serviced. Additional\r
1569 core-exit latency amy be applicable depending on the actual C-state the core\r
1570 is in. Note: C-state values are processor specific C-state code names,\r
1571 unrelated to MWAIT extension C-state parameters or ACPI CStates.\r
1572\r
1573 @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)\r
1574 @param EAX Lower 32-bits of MSR value.\r
1575 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.\r
1576 @param EDX Upper 32-bits of MSR value.\r
1577 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.\r
1578\r
1579 <b>Example usage</b>\r
1580 @code\r
1581 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr;\r
1582\r
1583 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);\r
1584 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);\r
1585 @endcode\r
1586**/\r
1587#define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B\r
1588\r
1589/**\r
1590 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL\r
1591**/\r
1592typedef union {\r
1593 ///\r
1594 /// Individual bit fields\r
1595 ///\r
1596 struct {\r
1597 ///\r
1598 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
1599 /// that should be used to decide if the package should be put into a\r
1600 /// package C6 state.\r
1601 ///\r
1602 UINT32 TimeLimit:10;\r
1603 ///\r
1604 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
1605 /// unit of the interrupt response time limit. The following time unit\r
1606 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
1607 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
1608 ///\r
1609 UINT32 TimeUnit:3;\r
1610 UINT32 Reserved1:2;\r
1611 ///\r
1612 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
1613 /// valid and can be used by the processor for package C-sate management.\r
1614 ///\r
1615 UINT32 Valid:1;\r
1616 UINT32 Reserved2:16;\r
1617 UINT32 Reserved3:32;\r
1618 } Bits;\r
1619 ///\r
1620 /// All bit fields as a 32-bit value\r
1621 ///\r
1622 UINT32 Uint32;\r
1623 ///\r
1624 /// All bit fields as a 64-bit value\r
1625 ///\r
1626 UINT64 Uint64;\r
1627} MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER;\r
1628\r
1629\r
1630/**\r
1631 Package. Note: C-state values are processor specific C-state code names,\r
1632 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r
1633 Residency Counter. (R/O) Value since last reset that this package is in\r
1634 processor-specific C2 states. Count at the same frequency as the TSC.\r
1635\r
1636 @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)\r
1637 @param EAX Lower 32-bits of MSR value.\r
1638 @param EDX Upper 32-bits of MSR value.\r
1639\r
1640 <b>Example usage</b>\r
1641 @code\r
1642 UINT64 Msr;\r
1643\r
1644 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);\r
1645 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);\r
1646 @endcode\r
1647**/\r
1648#define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D\r
1649\r
1650\r
1651/**\r
1652 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
1653 RAPL Domain.".\r
1654\r
1655 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)\r
1656 @param EAX Lower 32-bits of MSR value.\r
1657 @param EDX Upper 32-bits of MSR value.\r
1658\r
1659 <b>Example usage</b>\r
1660 @code\r
1661 UINT64 Msr;\r
1662\r
1663 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);\r
1664 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);\r
1665 @endcode\r
1666**/\r
1667#define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610\r
1668\r
1669\r
1670/**\r
1671 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
1672\r
1673 @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)\r
1674 @param EAX Lower 32-bits of MSR value.\r
1675 @param EDX Upper 32-bits of MSR value.\r
1676\r
1677 <b>Example usage</b>\r
1678 @code\r
1679 UINT64 Msr;\r
1680\r
1681 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);\r
1682 @endcode\r
1683**/\r
1684#define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611\r
1685\r
1686\r
1687/**\r
1688 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r
1689 Domain.".\r
1690\r
1691 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)\r
1692 @param EAX Lower 32-bits of MSR value.\r
1693 @param EDX Upper 32-bits of MSR value.\r
1694\r
1695 <b>Example usage</b>\r
1696 @code\r
1697 UINT64 Msr;\r
1698\r
1699 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);\r
1700 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);\r
1701 @endcode\r
1702**/\r
1703#define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614\r
1704\r
1705\r
1706/**\r
1707 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
1708 RAPL Domains.".\r
1709\r
1710 @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)\r
1711 @param EAX Lower 32-bits of MSR value.\r
1712 @param EDX Upper 32-bits of MSR value.\r
1713\r
1714 <b>Example usage</b>\r
1715 @code\r
1716 UINT64 Msr;\r
1717\r
1718 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);\r
1719 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);\r
1720 @endcode\r
1721**/\r
1722#define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638\r
1723\r
1724\r
1725/**\r
1726 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
1727 Domains.".\r
1728\r
1729 @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)\r
1730 @param EAX Lower 32-bits of MSR value.\r
1731 @param EDX Upper 32-bits of MSR value.\r
1732\r
1733 <b>Example usage</b>\r
1734 @code\r
1735 UINT64 Msr;\r
1736\r
1737 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);\r
1738 @endcode\r
1739**/\r
1740#define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
1741\r
1742\r
1743/**\r
1744 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
1745 branch record registers on the last branch record stack. This part of the\r
1746 stack contains pointers to the source instruction. See also: - Last Branch\r
1747 Record Stack TOS at 1C9H - Section 17.6.1, "LBR Stack.".\r
1748\r
1749 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP\r
1750 @param EAX Lower 32-bits of MSR value.\r
1751 @param EDX Upper 32-bits of MSR value.\r
1752\r
1753 <b>Example usage</b>\r
1754 @code\r
1755 UINT64 Msr;\r
1756\r
1757 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);\r
1758 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);\r
1759 @endcode\r
1760 @{\r
1761**/\r
1762#define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680\r
1763#define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681\r
1764#define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682\r
1765#define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683\r
1766#define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684\r
1767#define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685\r
1768#define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686\r
1769#define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687\r
1770#define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688\r
1771#define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689\r
1772#define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A\r
1773#define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B\r
1774#define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C\r
1775#define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D\r
1776#define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E\r
1777#define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F\r
1778/// @}\r
1779\r
1780\r
1781/**\r
1782 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
1783 record registers on the last branch record stack. This part of the stack\r
1784 contains pointers to the destination instruction.\r
1785\r
1786 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP\r
1787 @param EAX Lower 32-bits of MSR value.\r
1788 @param EDX Upper 32-bits of MSR value.\r
1789\r
1790 <b>Example usage</b>\r
1791 @code\r
1792 UINT64 Msr;\r
1793\r
1794 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);\r
1795 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);\r
1796 @endcode\r
1797 @{\r
1798**/\r
1799#define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0\r
1800#define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1\r
1801#define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2\r
1802#define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3\r
1803#define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4\r
1804#define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5\r
1805#define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6\r
1806#define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7\r
1807#define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8\r
1808#define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9\r
1809#define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA\r
1810#define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB\r
1811#define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC\r
1812#define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD\r
1813#define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE\r
1814#define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF\r
1815/// @}\r
1816\r
1817\r
1818/**\r
1819 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
1820 RW if MSR_PLATFORM_INFO.[28] = 1.\r
1821\r
1822 @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)\r
1823 @param EAX Lower 32-bits of MSR value.\r
1824 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.\r
1825 @param EDX Upper 32-bits of MSR value.\r
1826 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.\r
1827\r
1828 <b>Example usage</b>\r
1829 @code\r
1830 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr;\r
1831\r
1832 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);\r
1833 @endcode\r
1834**/\r
1835#define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD\r
1836\r
1837/**\r
1838 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT\r
1839**/\r
1840typedef union {\r
1841 ///\r
1842 /// Individual bit fields\r
1843 ///\r
1844 struct {\r
1845 ///\r
1846 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
1847 /// limit of 1 core active.\r
1848 ///\r
1849 UINT32 Maximum1C:8;\r
1850 ///\r
1851 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
1852 /// limit of 2 core active.\r
1853 ///\r
1854 UINT32 Maximum2C:8;\r
1855 ///\r
1856 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
1857 /// limit of 3 core active.\r
1858 ///\r
1859 UINT32 Maximum3C:8;\r
1860 ///\r
1861 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
1862 /// limit of 4 core active.\r
1863 ///\r
1864 UINT32 Maximum4C:8;\r
1865 ///\r
1866 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
1867 /// limit of 5 core active.\r
1868 ///\r
1869 UINT32 Maximum5C:8;\r
1870 ///\r
1871 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
1872 /// limit of 6 core active.\r
1873 ///\r
1874 UINT32 Maximum6C:8;\r
1875 ///\r
1876 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
1877 /// limit of 7 core active.\r
1878 ///\r
1879 UINT32 Maximum7C:8;\r
1880 ///\r
1881 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
1882 /// limit of 8 core active.\r
1883 ///\r
1884 UINT32 Maximum8C:8;\r
1885 } Bits;\r
1886 ///\r
1887 /// All bit fields as a 64-bit value\r
1888 ///\r
1889 UINT64 Uint64;\r
1890} MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER;\r
1891\r
1892\r
1893/**\r
1894 Package. Uncore PMU global control.\r
1895\r
1896 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)\r
1897 @param EAX Lower 32-bits of MSR value.\r
1898 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
1899 @param EDX Upper 32-bits of MSR value.\r
1900 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
1901\r
1902 <b>Example usage</b>\r
1903 @code\r
1904 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r
1905\r
1906 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);\r
1907 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
1908 @endcode\r
1909**/\r
1910#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391\r
1911\r
1912/**\r
1913 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL\r
1914**/\r
1915typedef union {\r
1916 ///\r
1917 /// Individual bit fields\r
1918 ///\r
1919 struct {\r
1920 ///\r
1921 /// [Bit 0] Core 0 select.\r
1922 ///\r
1923 UINT32 PMI_Sel_Core0:1;\r
1924 ///\r
1925 /// [Bit 1] Core 1 select.\r
1926 ///\r
1927 UINT32 PMI_Sel_Core1:1;\r
1928 ///\r
1929 /// [Bit 2] Core 2 select.\r
1930 ///\r
1931 UINT32 PMI_Sel_Core2:1;\r
1932 ///\r
1933 /// [Bit 3] Core 3 select.\r
1934 ///\r
1935 UINT32 PMI_Sel_Core3:1;\r
1936 UINT32 Reserved1:15;\r
1937 UINT32 Reserved2:10;\r
1938 ///\r
1939 /// [Bit 29] Enable all uncore counters.\r
1940 ///\r
1941 UINT32 EN:1;\r
1942 ///\r
1943 /// [Bit 30] Enable wake on PMI.\r
1944 ///\r
1945 UINT32 WakePMI:1;\r
1946 ///\r
1947 /// [Bit 31] Enable Freezing counter when overflow.\r
1948 ///\r
1949 UINT32 FREEZE:1;\r
1950 UINT32 Reserved3:32;\r
1951 } Bits;\r
1952 ///\r
1953 /// All bit fields as a 32-bit value\r
1954 ///\r
1955 UINT32 Uint32;\r
1956 ///\r
1957 /// All bit fields as a 64-bit value\r
1958 ///\r
1959 UINT64 Uint64;\r
1960} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
1961\r
1962\r
1963/**\r
1964 Package. Uncore PMU main status.\r
1965\r
1966 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)\r
1967 @param EAX Lower 32-bits of MSR value.\r
1968 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
1969 @param EDX Upper 32-bits of MSR value.\r
1970 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
1971\r
1972 <b>Example usage</b>\r
1973 @code\r
1974 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r
1975\r
1976 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);\r
1977 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
1978 @endcode\r
1979**/\r
1980#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392\r
1981\r
1982/**\r
1983 MSR information returned for MSR index\r
1984 #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS\r
1985**/\r
1986typedef union {\r
1987 ///\r
1988 /// Individual bit fields\r
1989 ///\r
1990 struct {\r
1991 ///\r
1992 /// [Bit 0] Fixed counter overflowed.\r
1993 ///\r
1994 UINT32 Fixed:1;\r
1995 ///\r
1996 /// [Bit 1] An ARB counter overflowed.\r
1997 ///\r
1998 UINT32 ARB:1;\r
1999 UINT32 Reserved1:1;\r
2000 ///\r
2001 /// [Bit 3] A CBox counter overflowed (on any slice).\r
2002 ///\r
2003 UINT32 CBox:1;\r
2004 UINT32 Reserved2:28;\r
2005 UINT32 Reserved3:32;\r
2006 } Bits;\r
2007 ///\r
2008 /// All bit fields as a 32-bit value\r
2009 ///\r
2010 UINT32 Uint32;\r
2011 ///\r
2012 /// All bit fields as a 64-bit value\r
2013 ///\r
2014 UINT64 Uint64;\r
2015} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
2016\r
2017\r
2018/**\r
2019 Package. Uncore fixed counter control (R/W).\r
2020\r
2021 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)\r
2022 @param EAX Lower 32-bits of MSR value.\r
2023 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.\r
2024 @param EDX Upper 32-bits of MSR value.\r
2025 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.\r
2026\r
2027 <b>Example usage</b>\r
2028 @code\r
2029 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r
2030\r
2031 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);\r
2032 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
2033 @endcode\r
2034**/\r
2035#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394\r
2036\r
2037/**\r
2038 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL\r
2039**/\r
2040typedef union {\r
2041 ///\r
2042 /// Individual bit fields\r
2043 ///\r
2044 struct {\r
2045 UINT32 Reserved1:20;\r
2046 ///\r
2047 /// [Bit 20] Enable overflow propagation.\r
2048 ///\r
2049 UINT32 EnableOverflow:1;\r
2050 UINT32 Reserved2:1;\r
2051 ///\r
2052 /// [Bit 22] Enable counting.\r
2053 ///\r
2054 UINT32 EnableCounting:1;\r
2055 UINT32 Reserved3:9;\r
2056 UINT32 Reserved4:32;\r
2057 } Bits;\r
2058 ///\r
2059 /// All bit fields as a 32-bit value\r
2060 ///\r
2061 UINT32 Uint32;\r
2062 ///\r
2063 /// All bit fields as a 64-bit value\r
2064 ///\r
2065 UINT64 Uint64;\r
2066} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER;\r
2067\r
2068\r
2069/**\r
2070 Package. Uncore fixed counter.\r
2071\r
2072 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)\r
2073 @param EAX Lower 32-bits of MSR value.\r
2074 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.\r
2075 @param EDX Upper 32-bits of MSR value.\r
2076 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.\r
2077\r
2078 <b>Example usage</b>\r
2079 @code\r
2080 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr;\r
2081\r
2082 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);\r
2083 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
2084 @endcode\r
2085**/\r
2086#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395\r
2087\r
2088/**\r
2089 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR\r
2090**/\r
2091typedef union {\r
2092 ///\r
2093 /// Individual bit fields\r
2094 ///\r
2095 struct {\r
2096 ///\r
2097 /// [Bits 31:0] Current count.\r
2098 ///\r
2099 UINT32 CurrentCount:32;\r
2100 ///\r
2101 /// [Bits 47:32] Current count.\r
2102 ///\r
2103 UINT32 CurrentCountHi:16;\r
2104 UINT32 Reserved:16;\r
2105 } Bits;\r
2106 ///\r
2107 /// All bit fields as a 64-bit value\r
2108 ///\r
2109 UINT64 Uint64;\r
2110} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER;\r
2111\r
2112\r
2113/**\r
2114 Package. Uncore C-Box configuration information (R/O).\r
2115\r
2116 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)\r
2117 @param EAX Lower 32-bits of MSR value.\r
2118 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.\r
2119 @param EDX Upper 32-bits of MSR value.\r
2120 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.\r
2121\r
2122 <b>Example usage</b>\r
2123 @code\r
2124 MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr;\r
2125\r
2126 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);\r
2127 @endcode\r
2128**/\r
2129#define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396\r
2130\r
2131/**\r
2132 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG\r
2133**/\r
2134typedef union {\r
2135 ///\r
2136 /// Individual bit fields\r
2137 ///\r
2138 struct {\r
2139 ///\r
2140 /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".\r
2141 ///\r
2142 UINT32 CBox:4;\r
2143 UINT32 Reserved1:28;\r
2144 UINT32 Reserved2:32;\r
2145 } Bits;\r
2146 ///\r
2147 /// All bit fields as a 32-bit value\r
2148 ///\r
2149 UINT32 Uint32;\r
2150 ///\r
2151 /// All bit fields as a 64-bit value\r
2152 ///\r
2153 UINT64 Uint64;\r
2154} MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER;\r
2155\r
2156\r
2157/**\r
2158 Package. Uncore Arb unit, performance counter 0.\r
2159\r
2160 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)\r
2161 @param EAX Lower 32-bits of MSR value.\r
2162 @param EDX Upper 32-bits of MSR value.\r
2163\r
2164 <b>Example usage</b>\r
2165 @code\r
2166 UINT64 Msr;\r
2167\r
2168 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);\r
2169 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);\r
2170 @endcode\r
2171**/\r
2172#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0\r
2173\r
2174\r
2175/**\r
2176 Package. Uncore Arb unit, performance counter 1.\r
2177\r
2178 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)\r
2179 @param EAX Lower 32-bits of MSR value.\r
2180 @param EDX Upper 32-bits of MSR value.\r
2181\r
2182 <b>Example usage</b>\r
2183 @code\r
2184 UINT64 Msr;\r
2185\r
2186 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);\r
2187 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);\r
2188 @endcode\r
2189**/\r
2190#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1\r
2191\r
2192\r
2193/**\r
2194 Package. Uncore Arb unit, counter 0 event select MSR.\r
2195\r
2196 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r
2197 @param EAX Lower 32-bits of MSR value.\r
2198 @param EDX Upper 32-bits of MSR value.\r
2199\r
2200 <b>Example usage</b>\r
2201 @code\r
2202 UINT64 Msr;\r
2203\r
2204 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);\r
2205 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);\r
2206 @endcode\r
2207**/\r
2208#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
2209\r
2210\r
2211/**\r
2212 Package. Uncore Arb unit, counter 1 event select MSR.\r
2213\r
2214 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r
2215 @param EAX Lower 32-bits of MSR value.\r
2216 @param EDX Upper 32-bits of MSR value.\r
2217\r
2218 <b>Example usage</b>\r
2219 @code\r
2220 UINT64 Msr;\r
2221\r
2222 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);\r
2223 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);\r
2224 @endcode\r
2225**/\r
2226#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
2227\r
2228\r
2229/**\r
2230 Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the\r
2231 budget allocated for the package to exit from C7 to a C0 state, where\r
2232 interrupt request can be delivered to the core and serviced. Additional\r
2233 core-exit latency amy be applicable depending on the actual C-state the core\r
2234 is in. Note: C-state values are processor specific C-state code names,\r
2235 unrelated to MWAIT extension C-state parameters or ACPI CStates.\r
2236\r
2237 @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)\r
2238 @param EAX Lower 32-bits of MSR value.\r
2239 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.\r
2240 @param EDX Upper 32-bits of MSR value.\r
2241 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.\r
2242\r
2243 <b>Example usage</b>\r
2244 @code\r
2245 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr;\r
2246\r
2247 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);\r
2248 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);\r
2249 @endcode\r
2250**/\r
2251#define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C\r
2252\r
2253/**\r
2254 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL\r
2255**/\r
2256typedef union {\r
2257 ///\r
2258 /// Individual bit fields\r
2259 ///\r
2260 struct {\r
2261 ///\r
2262 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
2263 /// that should be used to decide if the package should be put into a\r
2264 /// package C7 state.\r
2265 ///\r
2266 UINT32 TimeLimit:10;\r
2267 ///\r
2268 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
2269 /// unit of the interrupt response time limit. The following time unit\r
2270 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
2271 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
2272 ///\r
2273 UINT32 TimeUnit:3;\r
2274 UINT32 Reserved1:2;\r
2275 ///\r
2276 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
2277 /// valid and can be used by the processor for package C-sate management.\r
2278 ///\r
2279 UINT32 Valid:1;\r
2280 UINT32 Reserved2:16;\r
2281 UINT32 Reserved3:32;\r
2282 } Bits;\r
2283 ///\r
2284 /// All bit fields as a 32-bit value\r
2285 ///\r
2286 UINT32 Uint32;\r
2287 ///\r
2288 /// All bit fields as a 64-bit value\r
2289 ///\r
2290 UINT64 Uint64;\r
2291} MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER;\r
2292\r
2293\r
2294/**\r
2295 Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
2296 Domains.".\r
2297\r
2298 @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)\r
2299 @param EAX Lower 32-bits of MSR value.\r
2300 @param EDX Upper 32-bits of MSR value.\r
2301\r
2302 <b>Example usage</b>\r
2303 @code\r
2304 UINT64 Msr;\r
2305\r
2306 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);\r
2307 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);\r
2308 @endcode\r
2309**/\r
2310#define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A\r
2311\r
2312\r
2313/**\r
2314 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
2315 RAPL Domains.".\r
2316\r
2317 @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)\r
2318 @param EAX Lower 32-bits of MSR value.\r
2319 @param EDX Upper 32-bits of MSR value.\r
2320\r
2321 <b>Example usage</b>\r
2322 @code\r
2323 UINT64 Msr;\r
2324\r
2325 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);\r
2326 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);\r
2327 @endcode\r
2328**/\r
2329#define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640\r
2330\r
2331\r
2332/**\r
2333 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
2334 Domains.".\r
2335\r
2336 @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)\r
2337 @param EAX Lower 32-bits of MSR value.\r
2338 @param EDX Upper 32-bits of MSR value.\r
2339\r
2340 <b>Example usage</b>\r
2341 @code\r
2342 UINT64 Msr;\r
2343\r
2344 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);\r
2345 @endcode\r
2346**/\r
2347#define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641\r
2348\r
2349\r
2350/**\r
2351 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
2352 Domains.".\r
2353\r
2354 @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)\r
2355 @param EAX Lower 32-bits of MSR value.\r
2356 @param EDX Upper 32-bits of MSR value.\r
2357\r
2358 <b>Example usage</b>\r
2359 @code\r
2360 UINT64 Msr;\r
2361\r
2362 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);\r
2363 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);\r
2364 @endcode\r
2365**/\r
2366#define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642\r
2367\r
2368\r
2369/**\r
2370 Package. Uncore C-Box 0, counter 0 event select MSR.\r
2371\r
2372 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r
2373 @param EAX Lower 32-bits of MSR value.\r
2374 @param EDX Upper 32-bits of MSR value.\r
2375\r
2376 <b>Example usage</b>\r
2377 @code\r
2378 UINT64 Msr;\r
2379\r
2380 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);\r
2381 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);\r
2382 @endcode\r
2383**/\r
2384#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
2385\r
2386\r
2387/**\r
2388 Package. Uncore C-Box 0, counter 1 event select MSR.\r
2389\r
2390 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r
2391 @param EAX Lower 32-bits of MSR value.\r
2392 @param EDX Upper 32-bits of MSR value.\r
2393\r
2394 <b>Example usage</b>\r
2395 @code\r
2396 UINT64 Msr;\r
2397\r
2398 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1);\r
2399 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1, Msr);\r
2400 @endcode\r
2401**/\r
2402#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
2403\r
2404\r
2405/**\r
2406 Package. Uncore C-Box 0, performance counter 0.\r
2407\r
2408 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 (0x00000706)\r
2409 @param EAX Lower 32-bits of MSR value.\r
2410 @param EDX Upper 32-bits of MSR value.\r
2411\r
2412 <b>Example usage</b>\r
2413 @code\r
2414 UINT64 Msr;\r
2415\r
2416 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);\r
2417 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);\r
2418 @endcode\r
2419**/\r
2420#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706\r
2421\r
2422\r
2423/**\r
2424 Package. Uncore C-Box 0, performance counter 1.\r
2425\r
2426 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 (0x00000707)\r
2427 @param EAX Lower 32-bits of MSR value.\r
2428 @param EDX Upper 32-bits of MSR value.\r
2429\r
2430 <b>Example usage</b>\r
2431 @code\r
2432 UINT64 Msr;\r
2433\r
2434 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1);\r
2435 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1, Msr);\r
2436 @endcode\r
2437**/\r
2438#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707\r
2439\r
2440\r
2441/**\r
2442 Package. Uncore C-Box 1, counter 0 event select MSR.\r
2443\r
2444 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r
2445 @param EAX Lower 32-bits of MSR value.\r
2446 @param EDX Upper 32-bits of MSR value.\r
2447\r
2448 <b>Example usage</b>\r
2449 @code\r
2450 UINT64 Msr;\r
2451\r
2452 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);\r
2453 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);\r
2454 @endcode\r
2455**/\r
2456#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
2457\r
2458\r
2459/**\r
2460 Package. Uncore C-Box 1, counter 1 event select MSR.\r
2461\r
2462 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r
2463 @param EAX Lower 32-bits of MSR value.\r
2464 @param EDX Upper 32-bits of MSR value.\r
2465\r
2466 <b>Example usage</b>\r
2467 @code\r
2468 UINT64 Msr;\r
2469\r
2470 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1);\r
2471 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1, Msr);\r
2472 @endcode\r
2473**/\r
2474#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
2475\r
2476\r
2477/**\r
2478 Package. Uncore C-Box 1, performance counter 0.\r
2479\r
2480 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 (0x00000716)\r
2481 @param EAX Lower 32-bits of MSR value.\r
2482 @param EDX Upper 32-bits of MSR value.\r
2483\r
2484 <b>Example usage</b>\r
2485 @code\r
2486 UINT64 Msr;\r
2487\r
2488 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);\r
2489 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);\r
2490 @endcode\r
2491**/\r
2492#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716\r
2493\r
2494\r
2495/**\r
2496 Package. Uncore C-Box 1, performance counter 1.\r
2497\r
2498 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 (0x00000717)\r
2499 @param EAX Lower 32-bits of MSR value.\r
2500 @param EDX Upper 32-bits of MSR value.\r
2501\r
2502 <b>Example usage</b>\r
2503 @code\r
2504 UINT64 Msr;\r
2505\r
2506 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1);\r
2507 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1, Msr);\r
2508 @endcode\r
2509**/\r
2510#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717\r
2511\r
2512\r
2513/**\r
2514 Package. Uncore C-Box 2, counter 0 event select MSR.\r
2515\r
2516 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r
2517 @param EAX Lower 32-bits of MSR value.\r
2518 @param EDX Upper 32-bits of MSR value.\r
2519\r
2520 <b>Example usage</b>\r
2521 @code\r
2522 UINT64 Msr;\r
2523\r
2524 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);\r
2525 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);\r
2526 @endcode\r
2527**/\r
2528#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
2529\r
2530\r
2531/**\r
2532 Package. Uncore C-Box 2, counter 1 event select MSR.\r
2533\r
2534 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r
2535 @param EAX Lower 32-bits of MSR value.\r
2536 @param EDX Upper 32-bits of MSR value.\r
2537\r
2538 <b>Example usage</b>\r
2539 @code\r
2540 UINT64 Msr;\r
2541\r
2542 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1);\r
2543 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1, Msr);\r
2544 @endcode\r
2545**/\r
2546#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
2547\r
2548\r
2549/**\r
2550 Package. Uncore C-Box 2, performance counter 0.\r
2551\r
2552 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 (0x00000726)\r
2553 @param EAX Lower 32-bits of MSR value.\r
2554 @param EDX Upper 32-bits of MSR value.\r
2555\r
2556 <b>Example usage</b>\r
2557 @code\r
2558 UINT64 Msr;\r
2559\r
2560 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);\r
2561 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);\r
2562 @endcode\r
2563**/\r
2564#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726\r
2565\r
2566\r
2567/**\r
2568 Package. Uncore C-Box 2, performance counter 1.\r
2569\r
2570 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 (0x00000727)\r
2571 @param EAX Lower 32-bits of MSR value.\r
2572 @param EDX Upper 32-bits of MSR value.\r
2573\r
2574 <b>Example usage</b>\r
2575 @code\r
2576 UINT64 Msr;\r
2577\r
2578 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1);\r
2579 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1, Msr);\r
2580 @endcode\r
2581**/\r
2582#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727\r
2583\r
2584\r
2585/**\r
2586 Package. Uncore C-Box 3, counter 0 event select MSR.\r
2587\r
2588 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r
2589 @param EAX Lower 32-bits of MSR value.\r
2590 @param EDX Upper 32-bits of MSR value.\r
2591\r
2592 <b>Example usage</b>\r
2593 @code\r
2594 UINT64 Msr;\r
2595\r
2596 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);\r
2597 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);\r
2598 @endcode\r
2599**/\r
2600#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
2601\r
2602\r
2603/**\r
2604 Package. Uncore C-Box 3, counter 1 event select MSR.\r
2605\r
2606 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r
2607 @param EAX Lower 32-bits of MSR value.\r
2608 @param EDX Upper 32-bits of MSR value.\r
2609\r
2610 <b>Example usage</b>\r
2611 @code\r
2612 UINT64 Msr;\r
2613\r
2614 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1);\r
2615 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1, Msr);\r
2616 @endcode\r
2617**/\r
2618#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
2619\r
2620\r
2621/**\r
2622 Package. Uncore C-Box 3, performance counter 0.\r
2623\r
2624 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 (0x00000736)\r
2625 @param EAX Lower 32-bits of MSR value.\r
2626 @param EDX Upper 32-bits of MSR value.\r
2627\r
2628 <b>Example usage</b>\r
2629 @code\r
2630 UINT64 Msr;\r
2631\r
2632 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);\r
2633 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);\r
2634 @endcode\r
2635**/\r
2636#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736\r
2637\r
2638\r
2639/**\r
2640 Package. Uncore C-Box 3, performance counter 1.\r
2641\r
2642 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 (0x00000737)\r
2643 @param EAX Lower 32-bits of MSR value.\r
2644 @param EDX Upper 32-bits of MSR value.\r
2645\r
2646 <b>Example usage</b>\r
2647 @code\r
2648 UINT64 Msr;\r
2649\r
2650 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1);\r
2651 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1, Msr);\r
2652 @endcode\r
2653**/\r
2654#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737\r
2655\r
2656\r
2657/**\r
2658 Package. MC Bank Error Configuration (R/W).\r
2659\r
2660 @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)\r
2661 @param EAX Lower 32-bits of MSR value.\r
2662 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.\r
2663 @param EDX Upper 32-bits of MSR value.\r
2664 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.\r
2665\r
2666 <b>Example usage</b>\r
2667 @code\r
2668 MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr;\r
2669\r
2670 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);\r
2671 AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);\r
2672 @endcode\r
2673**/\r
2674#define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F\r
2675\r
2676/**\r
2677 MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL\r
2678**/\r
2679typedef union {\r
2680 ///\r
2681 /// Individual bit fields\r
2682 ///\r
2683 struct {\r
2684 UINT32 Reserved1:1;\r
2685 ///\r
2686 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
2687 /// to log additional info in bits 36:32.\r
2688 ///\r
2689 UINT32 MemErrorLogEnable:1;\r
2690 UINT32 Reserved2:30;\r
2691 UINT32 Reserved3:32;\r
2692 } Bits;\r
2693 ///\r
2694 /// All bit fields as a 32-bit value\r
2695 ///\r
2696 UINT32 Uint32;\r
2697 ///\r
2698 /// All bit fields as a 64-bit value\r
2699 ///\r
2700 UINT64 Uint64;\r
2701} MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER;\r
2702\r
2703\r
2704/**\r
2705 Package.\r
2706\r
2707 @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)\r
2708 @param EAX Lower 32-bits of MSR value.\r
2709 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.\r
2710 @param EDX Upper 32-bits of MSR value.\r
2711 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.\r
2712\r
2713 <b>Example usage</b>\r
2714 @code\r
2715 MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr;\r
2716\r
2717 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);\r
2718 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);\r
2719 @endcode\r
2720**/\r
2721#define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C\r
2722\r
2723/**\r
2724 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT\r
2725**/\r
2726typedef union {\r
2727 ///\r
2728 /// Individual bit fields\r
2729 ///\r
2730 struct {\r
2731 ///\r
2732 /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS\r
2733 /// counting logic for specific events requiring additional configuration,\r
2734 /// see Table 19-9.\r
2735 ///\r
2736 UINT32 ENABLE_PEBS_NUM_ALT:1;\r
2737 UINT32 Reserved1:31;\r
2738 UINT32 Reserved2:32;\r
2739 } Bits;\r
2740 ///\r
2741 /// All bit fields as a 32-bit value\r
2742 ///\r
2743 UINT32 Uint32;\r
2744 ///\r
2745 /// All bit fields as a 64-bit value\r
2746 ///\r
2747 UINT64 Uint64;\r
2748} MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER;\r
2749\r
2750\r
2751/**\r
2752 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
2753\r
2754 @param ECX MSR_SANDY_BRIDGE_MCi_CTL\r
2755 @param EAX Lower 32-bits of MSR value.\r
2756 @param EDX Upper 32-bits of MSR value.\r
2757\r
2758 <b>Example usage</b>\r
2759 @code\r
2760 UINT64 Msr;\r
2761\r
2762 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_CTL);\r
2763 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_CTL, Msr);\r
2764 @endcode\r
2765 @{\r
2766**/\r
2767#define MSR_SANDY_BRIDGE_MC5_CTL 0x00000414\r
2768#define MSR_SANDY_BRIDGE_MC6_CTL 0x00000418\r
2769#define MSR_SANDY_BRIDGE_MC7_CTL 0x0000041C\r
2770#define MSR_SANDY_BRIDGE_MC8_CTL 0x00000420\r
2771#define MSR_SANDY_BRIDGE_MC9_CTL 0x00000424\r
2772#define MSR_SANDY_BRIDGE_MC10_CTL 0x00000428\r
2773#define MSR_SANDY_BRIDGE_MC11_CTL 0x0000042C\r
2774#define MSR_SANDY_BRIDGE_MC12_CTL 0x00000430\r
2775#define MSR_SANDY_BRIDGE_MC13_CTL 0x00000434\r
2776#define MSR_SANDY_BRIDGE_MC14_CTL 0x00000438\r
2777#define MSR_SANDY_BRIDGE_MC15_CTL 0x0000043C\r
2778#define MSR_SANDY_BRIDGE_MC16_CTL 0x00000440\r
2779#define MSR_SANDY_BRIDGE_MC17_CTL 0x00000444\r
2780#define MSR_SANDY_BRIDGE_MC18_CTL 0x00000448\r
2781#define MSR_SANDY_BRIDGE_MC19_CTL 0x0000044C\r
2782/// @}\r
2783\r
2784\r
2785/**\r
2786 Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.\r
2787\r
2788 @param ECX MSR_SANDY_BRIDGE_MCi_STATUS\r
2789 @param EAX Lower 32-bits of MSR value.\r
2790 @param EDX Upper 32-bits of MSR value.\r
2791\r
2792 <b>Example usage</b>\r
2793 @code\r
2794 UINT64 Msr;\r
2795\r
2796 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS);\r
2797 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS, Msr);\r
2798 @endcode\r
2799 @{\r
2800**/\r
2801#define MSR_SANDY_BRIDGE_MC5_STATUS 0x00000415\r
2802#define MSR_SANDY_BRIDGE_MC6_STATUS 0x00000419\r
2803#define MSR_SANDY_BRIDGE_MC7_STATUS 0x0000041D\r
2804#define MSR_SANDY_BRIDGE_MC8_STATUS 0x00000421\r
2805#define MSR_SANDY_BRIDGE_MC9_STATUS 0x00000425\r
2806#define MSR_SANDY_BRIDGE_MC10_STATUS 0x00000429\r
2807#define MSR_SANDY_BRIDGE_MC11_STATUS 0x0000042D\r
2808#define MSR_SANDY_BRIDGE_MC12_STATUS 0x00000431\r
2809#define MSR_SANDY_BRIDGE_MC13_STATUS 0x00000435\r
2810#define MSR_SANDY_BRIDGE_MC14_STATUS 0x00000439\r
2811#define MSR_SANDY_BRIDGE_MC15_STATUS 0x0000043D\r
2812#define MSR_SANDY_BRIDGE_MC16_STATUS 0x00000441\r
2813#define MSR_SANDY_BRIDGE_MC17_STATUS 0x00000445\r
2814#define MSR_SANDY_BRIDGE_MC18_STATUS 0x00000449\r
2815#define MSR_SANDY_BRIDGE_MC19_STATUS 0x0000044D\r
2816/// @}\r
2817\r
2818\r
2819/**\r
2820 Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".\r
2821\r
2822 @param ECX MSR_SANDY_BRIDGE_MCi_ADDR\r
2823 @param EAX Lower 32-bits of MSR value.\r
2824 @param EDX Upper 32-bits of MSR value.\r
2825\r
2826 <b>Example usage</b>\r
2827 @code\r
2828 UINT64 Msr;\r
2829\r
2830 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR);\r
2831 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR, Msr);\r
2832 @endcode\r
2833 @{\r
2834**/\r
2835#define MSR_SANDY_BRIDGE_MC5_ADDR 0x00000416\r
2836#define MSR_SANDY_BRIDGE_MC6_ADDR 0x0000041A\r
2837#define MSR_SANDY_BRIDGE_MC7_ADDR 0x0000041E\r
2838#define MSR_SANDY_BRIDGE_MC8_ADDR 0x00000422\r
2839#define MSR_SANDY_BRIDGE_MC9_ADDR 0x00000426\r
2840#define MSR_SANDY_BRIDGE_MC10_ADDR 0x0000042A\r
2841#define MSR_SANDY_BRIDGE_MC11_ADDR 0x0000042E\r
2842#define MSR_SANDY_BRIDGE_MC12_ADDR 0x00000432\r
2843#define MSR_SANDY_BRIDGE_MC13_ADDR 0x00000436\r
2844#define MSR_SANDY_BRIDGE_MC14_ADDR 0x0000043A\r
2845#define MSR_SANDY_BRIDGE_MC15_ADDR 0x0000043E\r
2846#define MSR_SANDY_BRIDGE_MC16_ADDR 0x00000442\r
2847#define MSR_SANDY_BRIDGE_MC17_ADDR 0x00000446\r
2848#define MSR_SANDY_BRIDGE_MC18_ADDR 0x0000044A\r
2849#define MSR_SANDY_BRIDGE_MC19_ADDR 0x0000044E\r
2850/// @}\r
2851\r
2852\r
2853/**\r
2854 Package. See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
2855\r
2856 @param ECX MSR_SANDY_BRIDGE_MCi_MISC\r
2857 @param EAX Lower 32-bits of MSR value.\r
2858 @param EDX Upper 32-bits of MSR value.\r
2859\r
2860 <b>Example usage</b>\r
2861 @code\r
2862 UINT64 Msr;\r
2863\r
2864 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_MISC);\r
2865 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_MISC, Msr);\r
2866 @endcode\r
2867 @{\r
2868**/\r
2869#define MSR_SANDY_BRIDGE_MC5_MISC 0x00000417\r
2870#define MSR_SANDY_BRIDGE_MC6_MISC 0x0000041B\r
2871#define MSR_SANDY_BRIDGE_MC7_MISC 0x0000041F\r
2872#define MSR_SANDY_BRIDGE_MC8_MISC 0x00000423\r
2873#define MSR_SANDY_BRIDGE_MC9_MISC 0x00000427\r
2874#define MSR_SANDY_BRIDGE_MC10_MISC 0x0000042B\r
2875#define MSR_SANDY_BRIDGE_MC11_MISC 0x0000042F\r
2876#define MSR_SANDY_BRIDGE_MC12_MISC 0x00000433\r
2877#define MSR_SANDY_BRIDGE_MC13_MISC 0x00000437\r
2878#define MSR_SANDY_BRIDGE_MC14_MISC 0x0000043B\r
2879#define MSR_SANDY_BRIDGE_MC15_MISC 0x0000043F\r
2880#define MSR_SANDY_BRIDGE_MC16_MISC 0x00000443\r
2881#define MSR_SANDY_BRIDGE_MC17_MISC 0x00000447\r
2882#define MSR_SANDY_BRIDGE_MC18_MISC 0x0000044B\r
2883#define MSR_SANDY_BRIDGE_MC19_MISC 0x0000044F\r
2884/// @}\r
2885\r
2886\r
2887/**\r
2888 Package. Package RAPL Perf Status (R/O).\r
2889\r
2890 @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)\r
2891 @param EAX Lower 32-bits of MSR value.\r
2892 @param EDX Upper 32-bits of MSR value.\r
2893\r
2894 <b>Example usage</b>\r
2895 @code\r
2896 UINT64 Msr;\r
2897\r
2898 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);\r
2899 @endcode\r
2900**/\r
2901#define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
2902\r
2903\r
2904/**\r
2905 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
2906 Domain.".\r
2907\r
2908 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)\r
2909 @param EAX Lower 32-bits of MSR value.\r
2910 @param EDX Upper 32-bits of MSR value.\r
2911\r
2912 <b>Example usage</b>\r
2913 @code\r
2914 UINT64 Msr;\r
2915\r
2916 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);\r
2917 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);\r
2918 @endcode\r
2919**/\r
2920#define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
2921\r
2922\r
2923/**\r
2924 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
2925\r
2926 @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)\r
2927 @param EAX Lower 32-bits of MSR value.\r
2928 @param EDX Upper 32-bits of MSR value.\r
2929\r
2930 <b>Example usage</b>\r
2931 @code\r
2932 UINT64 Msr;\r
2933\r
2934 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);\r
2935 @endcode\r
2936**/\r
2937#define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
2938\r
2939\r
2940/**\r
2941 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
2942 RAPL Domain.".\r
2943\r
2944 @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)\r
2945 @param EAX Lower 32-bits of MSR value.\r
2946 @param EDX Upper 32-bits of MSR value.\r
2947\r
2948 <b>Example usage</b>\r
2949 @code\r
2950 UINT64 Msr;\r
2951\r
2952 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);\r
2953 @endcode\r
2954**/\r
2955#define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
2956\r
2957\r
2958/**\r
2959 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
2960\r
2961 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)\r
2962 @param EAX Lower 32-bits of MSR value.\r
2963 @param EDX Upper 32-bits of MSR value.\r
2964\r
2965 <b>Example usage</b>\r
2966 @code\r
2967 UINT64 Msr;\r
2968\r
2969 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);\r
2970 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);\r
2971 @endcode\r
2972**/\r
2973#define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
2974\r
2975\r
2976/**\r
2977 Package. Uncore U-box UCLK fixed counter control.\r
2978\r
2979 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)\r
2980 @param EAX Lower 32-bits of MSR value.\r
2981 @param EDX Upper 32-bits of MSR value.\r
2982\r
2983 <b>Example usage</b>\r
2984 @code\r
2985 UINT64 Msr;\r
2986\r
2987 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);\r
2988 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);\r
2989 @endcode\r
2990**/\r
2991#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08\r
2992\r
2993\r
2994/**\r
2995 Package. Uncore U-box UCLK fixed counter.\r
2996\r
2997 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)\r
2998 @param EAX Lower 32-bits of MSR value.\r
2999 @param EDX Upper 32-bits of MSR value.\r
3000\r
3001 <b>Example usage</b>\r
3002 @code\r
3003 UINT64 Msr;\r
3004\r
3005 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);\r
3006 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);\r
3007 @endcode\r
3008**/\r
3009#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09\r
3010\r
3011\r
3012/**\r
3013 Package. Uncore U-box perfmon event select for U-box counter 0.\r
3014\r
3015 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)\r
3016 @param EAX Lower 32-bits of MSR value.\r
3017 @param EDX Upper 32-bits of MSR value.\r
3018\r
3019 <b>Example usage</b>\r
3020 @code\r
3021 UINT64 Msr;\r
3022\r
3023 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);\r
3024 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);\r
3025 @endcode\r
3026**/\r
3027#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10\r
3028\r
3029\r
3030/**\r
3031 Package. Uncore U-box perfmon event select for U-box counter 1.\r
3032\r
3033 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)\r
3034 @param EAX Lower 32-bits of MSR value.\r
3035 @param EDX Upper 32-bits of MSR value.\r
3036\r
3037 <b>Example usage</b>\r
3038 @code\r
3039 UINT64 Msr;\r
3040\r
3041 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);\r
3042 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);\r
3043 @endcode\r
3044**/\r
3045#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11\r
3046\r
3047\r
3048/**\r
3049 Package. Uncore U-box perfmon counter 0.\r
3050\r
3051 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)\r
3052 @param EAX Lower 32-bits of MSR value.\r
3053 @param EDX Upper 32-bits of MSR value.\r
3054\r
3055 <b>Example usage</b>\r
3056 @code\r
3057 UINT64 Msr;\r
3058\r
3059 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);\r
3060 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);\r
3061 @endcode\r
3062**/\r
3063#define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16\r
3064\r
3065\r
3066/**\r
3067 Package. Uncore U-box perfmon counter 1.\r
3068\r
3069 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)\r
3070 @param EAX Lower 32-bits of MSR value.\r
3071 @param EDX Upper 32-bits of MSR value.\r
3072\r
3073 <b>Example usage</b>\r
3074 @code\r
3075 UINT64 Msr;\r
3076\r
3077 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);\r
3078 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);\r
3079 @endcode\r
3080**/\r
3081#define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17\r
3082\r
3083\r
3084/**\r
3085 Package. Uncore PCU perfmon for PCU-box-wide control.\r
3086\r
3087 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)\r
3088 @param EAX Lower 32-bits of MSR value.\r
3089 @param EDX Upper 32-bits of MSR value.\r
3090\r
3091 <b>Example usage</b>\r
3092 @code\r
3093 UINT64 Msr;\r
3094\r
3095 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);\r
3096 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);\r
3097 @endcode\r
3098**/\r
3099#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24\r
3100\r
3101\r
3102/**\r
3103 Package. Uncore PCU perfmon event select for PCU counter 0.\r
3104\r
3105 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)\r
3106 @param EAX Lower 32-bits of MSR value.\r
3107 @param EDX Upper 32-bits of MSR value.\r
3108\r
3109 <b>Example usage</b>\r
3110 @code\r
3111 UINT64 Msr;\r
3112\r
3113 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);\r
3114 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);\r
3115 @endcode\r
3116**/\r
3117#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30\r
3118\r
3119\r
3120/**\r
3121 Package. Uncore PCU perfmon event select for PCU counter 1.\r
3122\r
3123 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)\r
3124 @param EAX Lower 32-bits of MSR value.\r
3125 @param EDX Upper 32-bits of MSR value.\r
3126\r
3127 <b>Example usage</b>\r
3128 @code\r
3129 UINT64 Msr;\r
3130\r
3131 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);\r
3132 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);\r
3133 @endcode\r
3134**/\r
3135#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31\r
3136\r
3137\r
3138/**\r
3139 Package. Uncore PCU perfmon event select for PCU counter 2.\r
3140\r
3141 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)\r
3142 @param EAX Lower 32-bits of MSR value.\r
3143 @param EDX Upper 32-bits of MSR value.\r
3144\r
3145 <b>Example usage</b>\r
3146 @code\r
3147 UINT64 Msr;\r
3148\r
3149 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);\r
3150 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);\r
3151 @endcode\r
3152**/\r
3153#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32\r
3154\r
3155\r
3156/**\r
3157 Package. Uncore PCU perfmon event select for PCU counter 3.\r
3158\r
3159 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)\r
3160 @param EAX Lower 32-bits of MSR value.\r
3161 @param EDX Upper 32-bits of MSR value.\r
3162\r
3163 <b>Example usage</b>\r
3164 @code\r
3165 UINT64 Msr;\r
3166\r
3167 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);\r
3168 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);\r
3169 @endcode\r
3170**/\r
3171#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33\r
3172\r
3173\r
3174/**\r
3175 Package. Uncore PCU perfmon box-wide filter.\r
3176\r
3177 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)\r
3178 @param EAX Lower 32-bits of MSR value.\r
3179 @param EDX Upper 32-bits of MSR value.\r
3180\r
3181 <b>Example usage</b>\r
3182 @code\r
3183 UINT64 Msr;\r
3184\r
3185 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);\r
3186 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);\r
3187 @endcode\r
3188**/\r
3189#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34\r
3190\r
3191\r
3192/**\r
3193 Package. Uncore PCU perfmon counter 0.\r
3194\r
3195 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)\r
3196 @param EAX Lower 32-bits of MSR value.\r
3197 @param EDX Upper 32-bits of MSR value.\r
3198\r
3199 <b>Example usage</b>\r
3200 @code\r
3201 UINT64 Msr;\r
3202\r
3203 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);\r
3204 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);\r
3205 @endcode\r
3206**/\r
3207#define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36\r
3208\r
3209\r
3210/**\r
3211 Package. Uncore PCU perfmon counter 1.\r
3212\r
3213 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)\r
3214 @param EAX Lower 32-bits of MSR value.\r
3215 @param EDX Upper 32-bits of MSR value.\r
3216\r
3217 <b>Example usage</b>\r
3218 @code\r
3219 UINT64 Msr;\r
3220\r
3221 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);\r
3222 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);\r
3223 @endcode\r
3224**/\r
3225#define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37\r
3226\r
3227\r
3228/**\r
3229 Package. Uncore PCU perfmon counter 2.\r
3230\r
3231 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)\r
3232 @param EAX Lower 32-bits of MSR value.\r
3233 @param EDX Upper 32-bits of MSR value.\r
3234\r
3235 <b>Example usage</b>\r
3236 @code\r
3237 UINT64 Msr;\r
3238\r
3239 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);\r
3240 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);\r
3241 @endcode\r
3242**/\r
3243#define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38\r
3244\r
3245\r
3246/**\r
3247 Package. Uncore PCU perfmon counter 3.\r
3248\r
3249 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)\r
3250 @param EAX Lower 32-bits of MSR value.\r
3251 @param EDX Upper 32-bits of MSR value.\r
3252\r
3253 <b>Example usage</b>\r
3254 @code\r
3255 UINT64 Msr;\r
3256\r
3257 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);\r
3258 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);\r
3259 @endcode\r
3260**/\r
3261#define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39\r
3262\r
3263\r
3264/**\r
3265 Package. Uncore C-box 0 perfmon local box wide control.\r
3266\r
3267 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)\r
3268 @param EAX Lower 32-bits of MSR value.\r
3269 @param EDX Upper 32-bits of MSR value.\r
3270\r
3271 <b>Example usage</b>\r
3272 @code\r
3273 UINT64 Msr;\r
3274\r
3275 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);\r
3276 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);\r
3277 @endcode\r
3278**/\r
3279#define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04\r
3280\r
3281\r
3282/**\r
3283 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r
3284\r
3285 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)\r
3286 @param EAX Lower 32-bits of MSR value.\r
3287 @param EDX Upper 32-bits of MSR value.\r
3288\r
3289 <b>Example usage</b>\r
3290 @code\r
3291 UINT64 Msr;\r
3292\r
3293 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);\r
3294 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);\r
3295 @endcode\r
3296**/\r
3297#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10\r
3298\r
3299\r
3300/**\r
3301 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r
3302\r
3303 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)\r
3304 @param EAX Lower 32-bits of MSR value.\r
3305 @param EDX Upper 32-bits of MSR value.\r
3306\r
3307 <b>Example usage</b>\r
3308 @code\r
3309 UINT64 Msr;\r
3310\r
3311 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);\r
3312 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);\r
3313 @endcode\r
3314**/\r
3315#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11\r
3316\r
3317\r
3318/**\r
3319 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r
3320\r
3321 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)\r
3322 @param EAX Lower 32-bits of MSR value.\r
3323 @param EDX Upper 32-bits of MSR value.\r
3324\r
3325 <b>Example usage</b>\r
3326 @code\r
3327 UINT64 Msr;\r
3328\r
3329 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);\r
3330 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);\r
3331 @endcode\r
3332**/\r
3333#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12\r
3334\r
3335\r
3336/**\r
3337 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r
3338\r
3339 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)\r
3340 @param EAX Lower 32-bits of MSR value.\r
3341 @param EDX Upper 32-bits of MSR value.\r
3342\r
3343 <b>Example usage</b>\r
3344 @code\r
3345 UINT64 Msr;\r
3346\r
3347 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);\r
3348 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);\r
3349 @endcode\r
3350**/\r
3351#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13\r
3352\r
3353\r
3354/**\r
3355 Package. Uncore C-box 0 perfmon box wide filter.\r
3356\r
3357 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)\r
3358 @param EAX Lower 32-bits of MSR value.\r
3359 @param EDX Upper 32-bits of MSR value.\r
3360\r
3361 <b>Example usage</b>\r
3362 @code\r
3363 UINT64 Msr;\r
3364\r
3365 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);\r
3366 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);\r
3367 @endcode\r
3368**/\r
3369#define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14\r
3370\r
3371\r
3372/**\r
3373 Package. Uncore C-box 0 perfmon counter 0.\r
3374\r
3375 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)\r
3376 @param EAX Lower 32-bits of MSR value.\r
3377 @param EDX Upper 32-bits of MSR value.\r
3378\r
3379 <b>Example usage</b>\r
3380 @code\r
3381 UINT64 Msr;\r
3382\r
3383 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);\r
3384 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);\r
3385 @endcode\r
3386**/\r
3387#define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16\r
3388\r
3389\r
3390/**\r
3391 Package. Uncore C-box 0 perfmon counter 1.\r
3392\r
3393 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)\r
3394 @param EAX Lower 32-bits of MSR value.\r
3395 @param EDX Upper 32-bits of MSR value.\r
3396\r
3397 <b>Example usage</b>\r
3398 @code\r
3399 UINT64 Msr;\r
3400\r
3401 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);\r
3402 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);\r
3403 @endcode\r
3404**/\r
3405#define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17\r
3406\r
3407\r
3408/**\r
3409 Package. Uncore C-box 0 perfmon counter 2.\r
3410\r
3411 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)\r
3412 @param EAX Lower 32-bits of MSR value.\r
3413 @param EDX Upper 32-bits of MSR value.\r
3414\r
3415 <b>Example usage</b>\r
3416 @code\r
3417 UINT64 Msr;\r
3418\r
3419 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);\r
3420 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);\r
3421 @endcode\r
3422**/\r
3423#define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18\r
3424\r
3425\r
3426/**\r
3427 Package. Uncore C-box 0 perfmon counter 3.\r
3428\r
3429 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)\r
3430 @param EAX Lower 32-bits of MSR value.\r
3431 @param EDX Upper 32-bits of MSR value.\r
3432\r
3433 <b>Example usage</b>\r
3434 @code\r
3435 UINT64 Msr;\r
3436\r
3437 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);\r
3438 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);\r
3439 @endcode\r
3440**/\r
3441#define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19\r
3442\r
3443\r
3444/**\r
3445 Package. Uncore C-box 1 perfmon local box wide control.\r
3446\r
3447 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)\r
3448 @param EAX Lower 32-bits of MSR value.\r
3449 @param EDX Upper 32-bits of MSR value.\r
3450\r
3451 <b>Example usage</b>\r
3452 @code\r
3453 UINT64 Msr;\r
3454\r
3455 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);\r
3456 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);\r
3457 @endcode\r
3458**/\r
3459#define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24\r
3460\r
3461\r
3462/**\r
3463 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r
3464\r
3465 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)\r
3466 @param EAX Lower 32-bits of MSR value.\r
3467 @param EDX Upper 32-bits of MSR value.\r
3468\r
3469 <b>Example usage</b>\r
3470 @code\r
3471 UINT64 Msr;\r
3472\r
3473 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);\r
3474 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);\r
3475 @endcode\r
3476**/\r
3477#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30\r
3478\r
3479\r
3480/**\r
3481 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r
3482\r
3483 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)\r
3484 @param EAX Lower 32-bits of MSR value.\r
3485 @param EDX Upper 32-bits of MSR value.\r
3486\r
3487 <b>Example usage</b>\r
3488 @code\r
3489 UINT64 Msr;\r
3490\r
3491 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);\r
3492 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);\r
3493 @endcode\r
3494**/\r
3495#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31\r
3496\r
3497\r
3498/**\r
3499 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r
3500\r
3501 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)\r
3502 @param EAX Lower 32-bits of MSR value.\r
3503 @param EDX Upper 32-bits of MSR value.\r
3504\r
3505 <b>Example usage</b>\r
3506 @code\r
3507 UINT64 Msr;\r
3508\r
3509 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);\r
3510 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);\r
3511 @endcode\r
3512**/\r
3513#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32\r
3514\r
3515\r
3516/**\r
3517 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r
3518\r
3519 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)\r
3520 @param EAX Lower 32-bits of MSR value.\r
3521 @param EDX Upper 32-bits of MSR value.\r
3522\r
3523 <b>Example usage</b>\r
3524 @code\r
3525 UINT64 Msr;\r
3526\r
3527 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);\r
3528 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);\r
3529 @endcode\r
3530**/\r
3531#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33\r
3532\r
3533\r
3534/**\r
3535 Package. Uncore C-box 1 perfmon box wide filter.\r
3536\r
3537 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)\r
3538 @param EAX Lower 32-bits of MSR value.\r
3539 @param EDX Upper 32-bits of MSR value.\r
3540\r
3541 <b>Example usage</b>\r
3542 @code\r
3543 UINT64 Msr;\r
3544\r
3545 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);\r
3546 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);\r
3547 @endcode\r
3548**/\r
3549#define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34\r
3550\r
3551\r
3552/**\r
3553 Package. Uncore C-box 1 perfmon counter 0.\r
3554\r
3555 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)\r
3556 @param EAX Lower 32-bits of MSR value.\r
3557 @param EDX Upper 32-bits of MSR value.\r
3558\r
3559 <b>Example usage</b>\r
3560 @code\r
3561 UINT64 Msr;\r
3562\r
3563 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);\r
3564 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);\r
3565 @endcode\r
3566**/\r
3567#define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36\r
3568\r
3569\r
3570/**\r
3571 Package. Uncore C-box 1 perfmon counter 1.\r
3572\r
3573 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)\r
3574 @param EAX Lower 32-bits of MSR value.\r
3575 @param EDX Upper 32-bits of MSR value.\r
3576\r
3577 <b>Example usage</b>\r
3578 @code\r
3579 UINT64 Msr;\r
3580\r
3581 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);\r
3582 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);\r
3583 @endcode\r
3584**/\r
3585#define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37\r
3586\r
3587\r
3588/**\r
3589 Package. Uncore C-box 1 perfmon counter 2.\r
3590\r
3591 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)\r
3592 @param EAX Lower 32-bits of MSR value.\r
3593 @param EDX Upper 32-bits of MSR value.\r
3594\r
3595 <b>Example usage</b>\r
3596 @code\r
3597 UINT64 Msr;\r
3598\r
3599 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);\r
3600 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);\r
3601 @endcode\r
3602**/\r
3603#define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38\r
3604\r
3605\r
3606/**\r
3607 Package. Uncore C-box 1 perfmon counter 3.\r
3608\r
3609 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)\r
3610 @param EAX Lower 32-bits of MSR value.\r
3611 @param EDX Upper 32-bits of MSR value.\r
3612\r
3613 <b>Example usage</b>\r
3614 @code\r
3615 UINT64 Msr;\r
3616\r
3617 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);\r
3618 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);\r
3619 @endcode\r
3620**/\r
3621#define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39\r
3622\r
3623\r
3624/**\r
3625 Package. Uncore C-box 2 perfmon local box wide control.\r
3626\r
3627 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)\r
3628 @param EAX Lower 32-bits of MSR value.\r
3629 @param EDX Upper 32-bits of MSR value.\r
3630\r
3631 <b>Example usage</b>\r
3632 @code\r
3633 UINT64 Msr;\r
3634\r
3635 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);\r
3636 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);\r
3637 @endcode\r
3638**/\r
3639#define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44\r
3640\r
3641\r
3642/**\r
3643 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r
3644\r
3645 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)\r
3646 @param EAX Lower 32-bits of MSR value.\r
3647 @param EDX Upper 32-bits of MSR value.\r
3648\r
3649 <b>Example usage</b>\r
3650 @code\r
3651 UINT64 Msr;\r
3652\r
3653 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);\r
3654 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);\r
3655 @endcode\r
3656**/\r
3657#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50\r
3658\r
3659\r
3660/**\r
3661 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r
3662\r
3663 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)\r
3664 @param EAX Lower 32-bits of MSR value.\r
3665 @param EDX Upper 32-bits of MSR value.\r
3666\r
3667 <b>Example usage</b>\r
3668 @code\r
3669 UINT64 Msr;\r
3670\r
3671 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);\r
3672 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);\r
3673 @endcode\r
3674**/\r
3675#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51\r
3676\r
3677\r
3678/**\r
3679 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r
3680\r
3681 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)\r
3682 @param EAX Lower 32-bits of MSR value.\r
3683 @param EDX Upper 32-bits of MSR value.\r
3684\r
3685 <b>Example usage</b>\r
3686 @code\r
3687 UINT64 Msr;\r
3688\r
3689 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);\r
3690 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);\r
3691 @endcode\r
3692**/\r
3693#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52\r
3694\r
3695\r
3696/**\r
3697 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r
3698\r
3699 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)\r
3700 @param EAX Lower 32-bits of MSR value.\r
3701 @param EDX Upper 32-bits of MSR value.\r
3702\r
3703 <b>Example usage</b>\r
3704 @code\r
3705 UINT64 Msr;\r
3706\r
3707 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);\r
3708 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);\r
3709 @endcode\r
3710**/\r
3711#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53\r
3712\r
3713\r
3714/**\r
3715 Package. Uncore C-box 2 perfmon box wide filter.\r
3716\r
3717 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)\r
3718 @param EAX Lower 32-bits of MSR value.\r
3719 @param EDX Upper 32-bits of MSR value.\r
3720\r
3721 <b>Example usage</b>\r
3722 @code\r
3723 UINT64 Msr;\r
3724\r
3725 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);\r
3726 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);\r
3727 @endcode\r
3728**/\r
3729#define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54\r
3730\r
3731\r
3732/**\r
3733 Package. Uncore C-box 2 perfmon counter 0.\r
3734\r
3735 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)\r
3736 @param EAX Lower 32-bits of MSR value.\r
3737 @param EDX Upper 32-bits of MSR value.\r
3738\r
3739 <b>Example usage</b>\r
3740 @code\r
3741 UINT64 Msr;\r
3742\r
3743 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);\r
3744 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);\r
3745 @endcode\r
3746**/\r
3747#define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56\r
3748\r
3749\r
3750/**\r
3751 Package. Uncore C-box 2 perfmon counter 1.\r
3752\r
3753 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)\r
3754 @param EAX Lower 32-bits of MSR value.\r
3755 @param EDX Upper 32-bits of MSR value.\r
3756\r
3757 <b>Example usage</b>\r
3758 @code\r
3759 UINT64 Msr;\r
3760\r
3761 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);\r
3762 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);\r
3763 @endcode\r
3764**/\r
3765#define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57\r
3766\r
3767\r
3768/**\r
3769 Package. Uncore C-box 2 perfmon counter 2.\r
3770\r
3771 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)\r
3772 @param EAX Lower 32-bits of MSR value.\r
3773 @param EDX Upper 32-bits of MSR value.\r
3774\r
3775 <b>Example usage</b>\r
3776 @code\r
3777 UINT64 Msr;\r
3778\r
3779 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);\r
3780 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);\r
3781 @endcode\r
3782**/\r
3783#define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58\r
3784\r
3785\r
3786/**\r
3787 Package. Uncore C-box 2 perfmon counter 3.\r
3788\r
3789 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)\r
3790 @param EAX Lower 32-bits of MSR value.\r
3791 @param EDX Upper 32-bits of MSR value.\r
3792\r
3793 <b>Example usage</b>\r
3794 @code\r
3795 UINT64 Msr;\r
3796\r
3797 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);\r
3798 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);\r
3799 @endcode\r
3800**/\r
3801#define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59\r
3802\r
3803\r
3804/**\r
3805 Package. Uncore C-box 3 perfmon local box wide control.\r
3806\r
3807 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)\r
3808 @param EAX Lower 32-bits of MSR value.\r
3809 @param EDX Upper 32-bits of MSR value.\r
3810\r
3811 <b>Example usage</b>\r
3812 @code\r
3813 UINT64 Msr;\r
3814\r
3815 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);\r
3816 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);\r
3817 @endcode\r
3818**/\r
3819#define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64\r
3820\r
3821\r
3822/**\r
3823 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r
3824\r
3825 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)\r
3826 @param EAX Lower 32-bits of MSR value.\r
3827 @param EDX Upper 32-bits of MSR value.\r
3828\r
3829 <b>Example usage</b>\r
3830 @code\r
3831 UINT64 Msr;\r
3832\r
3833 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);\r
3834 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);\r
3835 @endcode\r
3836**/\r
3837#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70\r
3838\r
3839\r
3840/**\r
3841 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r
3842\r
3843 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)\r
3844 @param EAX Lower 32-bits of MSR value.\r
3845 @param EDX Upper 32-bits of MSR value.\r
3846\r
3847 <b>Example usage</b>\r
3848 @code\r
3849 UINT64 Msr;\r
3850\r
3851 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);\r
3852 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);\r
3853 @endcode\r
3854**/\r
3855#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71\r
3856\r
3857\r
3858/**\r
3859 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r
3860\r
3861 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)\r
3862 @param EAX Lower 32-bits of MSR value.\r
3863 @param EDX Upper 32-bits of MSR value.\r
3864\r
3865 <b>Example usage</b>\r
3866 @code\r
3867 UINT64 Msr;\r
3868\r
3869 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);\r
3870 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);\r
3871 @endcode\r
3872**/\r
3873#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72\r
3874\r
3875\r
3876/**\r
3877 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r
3878\r
3879 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)\r
3880 @param EAX Lower 32-bits of MSR value.\r
3881 @param EDX Upper 32-bits of MSR value.\r
3882\r
3883 <b>Example usage</b>\r
3884 @code\r
3885 UINT64 Msr;\r
3886\r
3887 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);\r
3888 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);\r
3889 @endcode\r
3890**/\r
3891#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73\r
3892\r
3893\r
3894/**\r
3895 Package. Uncore C-box 3 perfmon box wide filter.\r
3896\r
3897 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)\r
3898 @param EAX Lower 32-bits of MSR value.\r
3899 @param EDX Upper 32-bits of MSR value.\r
3900\r
3901 <b>Example usage</b>\r
3902 @code\r
3903 UINT64 Msr;\r
3904\r
3905 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);\r
3906 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);\r
3907 @endcode\r
3908**/\r
3909#define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74\r
3910\r
3911\r
3912/**\r
3913 Package. Uncore C-box 3 perfmon counter 0.\r
3914\r
3915 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)\r
3916 @param EAX Lower 32-bits of MSR value.\r
3917 @param EDX Upper 32-bits of MSR value.\r
3918\r
3919 <b>Example usage</b>\r
3920 @code\r
3921 UINT64 Msr;\r
3922\r
3923 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);\r
3924 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);\r
3925 @endcode\r
3926**/\r
3927#define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76\r
3928\r
3929\r
3930/**\r
3931 Package. Uncore C-box 3 perfmon counter 1.\r
3932\r
3933 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)\r
3934 @param EAX Lower 32-bits of MSR value.\r
3935 @param EDX Upper 32-bits of MSR value.\r
3936\r
3937 <b>Example usage</b>\r
3938 @code\r
3939 UINT64 Msr;\r
3940\r
3941 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);\r
3942 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);\r
3943 @endcode\r
3944**/\r
3945#define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77\r
3946\r
3947\r
3948/**\r
3949 Package. Uncore C-box 3 perfmon counter 2.\r
3950\r
3951 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)\r
3952 @param EAX Lower 32-bits of MSR value.\r
3953 @param EDX Upper 32-bits of MSR value.\r
3954\r
3955 <b>Example usage</b>\r
3956 @code\r
3957 UINT64 Msr;\r
3958\r
3959 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);\r
3960 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);\r
3961 @endcode\r
3962**/\r
3963#define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78\r
3964\r
3965\r
3966/**\r
3967 Package. Uncore C-box 3 perfmon counter 3.\r
3968\r
3969 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)\r
3970 @param EAX Lower 32-bits of MSR value.\r
3971 @param EDX Upper 32-bits of MSR value.\r
3972\r
3973 <b>Example usage</b>\r
3974 @code\r
3975 UINT64 Msr;\r
3976\r
3977 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);\r
3978 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);\r
3979 @endcode\r
3980**/\r
3981#define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79\r
3982\r
3983\r
3984/**\r
3985 Package. Uncore C-box 4 perfmon local box wide control.\r
3986\r
3987 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)\r
3988 @param EAX Lower 32-bits of MSR value.\r
3989 @param EDX Upper 32-bits of MSR value.\r
3990\r
3991 <b>Example usage</b>\r
3992 @code\r
3993 UINT64 Msr;\r
3994\r
3995 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);\r
3996 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);\r
3997 @endcode\r
3998**/\r
3999#define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84\r
4000\r
4001\r
4002/**\r
4003 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r
4004\r
4005 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)\r
4006 @param EAX Lower 32-bits of MSR value.\r
4007 @param EDX Upper 32-bits of MSR value.\r
4008\r
4009 <b>Example usage</b>\r
4010 @code\r
4011 UINT64 Msr;\r
4012\r
4013 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);\r
4014 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);\r
4015 @endcode\r
4016**/\r
4017#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90\r
4018\r
4019\r
4020/**\r
4021 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r
4022\r
4023 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)\r
4024 @param EAX Lower 32-bits of MSR value.\r
4025 @param EDX Upper 32-bits of MSR value.\r
4026\r
4027 <b>Example usage</b>\r
4028 @code\r
4029 UINT64 Msr;\r
4030\r
4031 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);\r
4032 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);\r
4033 @endcode\r
4034**/\r
4035#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91\r
4036\r
4037\r
4038/**\r
4039 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r
4040\r
4041 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)\r
4042 @param EAX Lower 32-bits of MSR value.\r
4043 @param EDX Upper 32-bits of MSR value.\r
4044\r
4045 <b>Example usage</b>\r
4046 @code\r
4047 UINT64 Msr;\r
4048\r
4049 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);\r
4050 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);\r
4051 @endcode\r
4052**/\r
4053#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92\r
4054\r
4055\r
4056/**\r
4057 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r
4058\r
4059 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)\r
4060 @param EAX Lower 32-bits of MSR value.\r
4061 @param EDX Upper 32-bits of MSR value.\r
4062\r
4063 <b>Example usage</b>\r
4064 @code\r
4065 UINT64 Msr;\r
4066\r
4067 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);\r
4068 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);\r
4069 @endcode\r
4070**/\r
4071#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93\r
4072\r
4073\r
4074/**\r
4075 Package. Uncore C-box 4 perfmon box wide filter.\r
4076\r
4077 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)\r
4078 @param EAX Lower 32-bits of MSR value.\r
4079 @param EDX Upper 32-bits of MSR value.\r
4080\r
4081 <b>Example usage</b>\r
4082 @code\r
4083 UINT64 Msr;\r
4084\r
4085 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);\r
4086 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);\r
4087 @endcode\r
4088**/\r
4089#define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94\r
4090\r
4091\r
4092/**\r
4093 Package. Uncore C-box 4 perfmon counter 0.\r
4094\r
4095 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)\r
4096 @param EAX Lower 32-bits of MSR value.\r
4097 @param EDX Upper 32-bits of MSR value.\r
4098\r
4099 <b>Example usage</b>\r
4100 @code\r
4101 UINT64 Msr;\r
4102\r
4103 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);\r
4104 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);\r
4105 @endcode\r
4106**/\r
4107#define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96\r
4108\r
4109\r
4110/**\r
4111 Package. Uncore C-box 4 perfmon counter 1.\r
4112\r
4113 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)\r
4114 @param EAX Lower 32-bits of MSR value.\r
4115 @param EDX Upper 32-bits of MSR value.\r
4116\r
4117 <b>Example usage</b>\r
4118 @code\r
4119 UINT64 Msr;\r
4120\r
4121 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);\r
4122 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);\r
4123 @endcode\r
4124**/\r
4125#define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97\r
4126\r
4127\r
4128/**\r
4129 Package. Uncore C-box 4 perfmon counter 2.\r
4130\r
4131 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)\r
4132 @param EAX Lower 32-bits of MSR value.\r
4133 @param EDX Upper 32-bits of MSR value.\r
4134\r
4135 <b>Example usage</b>\r
4136 @code\r
4137 UINT64 Msr;\r
4138\r
4139 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);\r
4140 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);\r
4141 @endcode\r
4142**/\r
4143#define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98\r
4144\r
4145\r
4146/**\r
4147 Package. Uncore C-box 4 perfmon counter 3.\r
4148\r
4149 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)\r
4150 @param EAX Lower 32-bits of MSR value.\r
4151 @param EDX Upper 32-bits of MSR value.\r
4152\r
4153 <b>Example usage</b>\r
4154 @code\r
4155 UINT64 Msr;\r
4156\r
4157 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);\r
4158 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);\r
4159 @endcode\r
4160**/\r
4161#define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99\r
4162\r
4163\r
4164/**\r
4165 Package. Uncore C-box 5 perfmon local box wide control.\r
4166\r
4167 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)\r
4168 @param EAX Lower 32-bits of MSR value.\r
4169 @param EDX Upper 32-bits of MSR value.\r
4170\r
4171 <b>Example usage</b>\r
4172 @code\r
4173 UINT64 Msr;\r
4174\r
4175 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);\r
4176 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);\r
4177 @endcode\r
4178**/\r
4179#define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4\r
4180\r
4181\r
4182/**\r
4183 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r
4184\r
4185 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)\r
4186 @param EAX Lower 32-bits of MSR value.\r
4187 @param EDX Upper 32-bits of MSR value.\r
4188\r
4189 <b>Example usage</b>\r
4190 @code\r
4191 UINT64 Msr;\r
4192\r
4193 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);\r
4194 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);\r
4195 @endcode\r
4196**/\r
4197#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0\r
4198\r
4199\r
4200/**\r
4201 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r
4202\r
4203 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)\r
4204 @param EAX Lower 32-bits of MSR value.\r
4205 @param EDX Upper 32-bits of MSR value.\r
4206\r
4207 <b>Example usage</b>\r
4208 @code\r
4209 UINT64 Msr;\r
4210\r
4211 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);\r
4212 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);\r
4213 @endcode\r
4214**/\r
4215#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1\r
4216\r
4217\r
4218/**\r
4219 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r
4220\r
4221 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)\r
4222 @param EAX Lower 32-bits of MSR value.\r
4223 @param EDX Upper 32-bits of MSR value.\r
4224\r
4225 <b>Example usage</b>\r
4226 @code\r
4227 UINT64 Msr;\r
4228\r
4229 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);\r
4230 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);\r
4231 @endcode\r
4232**/\r
4233#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2\r
4234\r
4235\r
4236/**\r
4237 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r
4238\r
4239 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)\r
4240 @param EAX Lower 32-bits of MSR value.\r
4241 @param EDX Upper 32-bits of MSR value.\r
4242\r
4243 <b>Example usage</b>\r
4244 @code\r
4245 UINT64 Msr;\r
4246\r
4247 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);\r
4248 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);\r
4249 @endcode\r
4250**/\r
4251#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3\r
4252\r
4253\r
4254/**\r
4255 Package. Uncore C-box 5 perfmon box wide filter.\r
4256\r
4257 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)\r
4258 @param EAX Lower 32-bits of MSR value.\r
4259 @param EDX Upper 32-bits of MSR value.\r
4260\r
4261 <b>Example usage</b>\r
4262 @code\r
4263 UINT64 Msr;\r
4264\r
4265 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);\r
4266 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);\r
4267 @endcode\r
4268**/\r
4269#define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4\r
4270\r
4271\r
4272/**\r
4273 Package. Uncore C-box 5 perfmon counter 0.\r
4274\r
4275 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)\r
4276 @param EAX Lower 32-bits of MSR value.\r
4277 @param EDX Upper 32-bits of MSR value.\r
4278\r
4279 <b>Example usage</b>\r
4280 @code\r
4281 UINT64 Msr;\r
4282\r
4283 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);\r
4284 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);\r
4285 @endcode\r
4286**/\r
4287#define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6\r
4288\r
4289\r
4290/**\r
4291 Package. Uncore C-box 5 perfmon counter 1.\r
4292\r
4293 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)\r
4294 @param EAX Lower 32-bits of MSR value.\r
4295 @param EDX Upper 32-bits of MSR value.\r
4296\r
4297 <b>Example usage</b>\r
4298 @code\r
4299 UINT64 Msr;\r
4300\r
4301 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);\r
4302 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);\r
4303 @endcode\r
4304**/\r
4305#define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7\r
4306\r
4307\r
4308/**\r
4309 Package. Uncore C-box 5 perfmon counter 2.\r
4310\r
4311 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)\r
4312 @param EAX Lower 32-bits of MSR value.\r
4313 @param EDX Upper 32-bits of MSR value.\r
4314\r
4315 <b>Example usage</b>\r
4316 @code\r
4317 UINT64 Msr;\r
4318\r
4319 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);\r
4320 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);\r
4321 @endcode\r
4322**/\r
4323#define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8\r
4324\r
4325\r
4326/**\r
4327 Package. Uncore C-box 5 perfmon counter 3.\r
4328\r
4329 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)\r
4330 @param EAX Lower 32-bits of MSR value.\r
4331 @param EDX Upper 32-bits of MSR value.\r
4332\r
4333 <b>Example usage</b>\r
4334 @code\r
4335 UINT64 Msr;\r
4336\r
4337 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);\r
4338 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);\r
4339 @endcode\r
4340**/\r
4341#define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9\r
4342\r
4343\r
4344/**\r
4345 Package. Uncore C-box 6 perfmon local box wide control.\r
4346\r
4347 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)\r
4348 @param EAX Lower 32-bits of MSR value.\r
4349 @param EDX Upper 32-bits of MSR value.\r
4350\r
4351 <b>Example usage</b>\r
4352 @code\r
4353 UINT64 Msr;\r
4354\r
4355 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);\r
4356 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);\r
4357 @endcode\r
4358**/\r
4359#define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4\r
4360\r
4361\r
4362/**\r
4363 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r
4364\r
4365 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)\r
4366 @param EAX Lower 32-bits of MSR value.\r
4367 @param EDX Upper 32-bits of MSR value.\r
4368\r
4369 <b>Example usage</b>\r
4370 @code\r
4371 UINT64 Msr;\r
4372\r
4373 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);\r
4374 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);\r
4375 @endcode\r
4376**/\r
4377#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0\r
4378\r
4379\r
4380/**\r
4381 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r
4382\r
4383 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)\r
4384 @param EAX Lower 32-bits of MSR value.\r
4385 @param EDX Upper 32-bits of MSR value.\r
4386\r
4387 <b>Example usage</b>\r
4388 @code\r
4389 UINT64 Msr;\r
4390\r
4391 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);\r
4392 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);\r
4393 @endcode\r
4394**/\r
4395#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1\r
4396\r
4397\r
4398/**\r
4399 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r
4400\r
4401 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)\r
4402 @param EAX Lower 32-bits of MSR value.\r
4403 @param EDX Upper 32-bits of MSR value.\r
4404\r
4405 <b>Example usage</b>\r
4406 @code\r
4407 UINT64 Msr;\r
4408\r
4409 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);\r
4410 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);\r
4411 @endcode\r
4412**/\r
4413#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2\r
4414\r
4415\r
4416/**\r
4417 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r
4418\r
4419 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)\r
4420 @param EAX Lower 32-bits of MSR value.\r
4421 @param EDX Upper 32-bits of MSR value.\r
4422\r
4423 <b>Example usage</b>\r
4424 @code\r
4425 UINT64 Msr;\r
4426\r
4427 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);\r
4428 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);\r
4429 @endcode\r
4430**/\r
4431#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3\r
4432\r
4433\r
4434/**\r
4435 Package. Uncore C-box 6 perfmon box wide filter.\r
4436\r
4437 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)\r
4438 @param EAX Lower 32-bits of MSR value.\r
4439 @param EDX Upper 32-bits of MSR value.\r
4440\r
4441 <b>Example usage</b>\r
4442 @code\r
4443 UINT64 Msr;\r
4444\r
4445 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);\r
4446 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);\r
4447 @endcode\r
4448**/\r
4449#define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4\r
4450\r
4451\r
4452/**\r
4453 Package. Uncore C-box 6 perfmon counter 0.\r
4454\r
4455 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)\r
4456 @param EAX Lower 32-bits of MSR value.\r
4457 @param EDX Upper 32-bits of MSR value.\r
4458\r
4459 <b>Example usage</b>\r
4460 @code\r
4461 UINT64 Msr;\r
4462\r
4463 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);\r
4464 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);\r
4465 @endcode\r
4466**/\r
4467#define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6\r
4468\r
4469\r
4470/**\r
4471 Package. Uncore C-box 6 perfmon counter 1.\r
4472\r
4473 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)\r
4474 @param EAX Lower 32-bits of MSR value.\r
4475 @param EDX Upper 32-bits of MSR value.\r
4476\r
4477 <b>Example usage</b>\r
4478 @code\r
4479 UINT64 Msr;\r
4480\r
4481 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);\r
4482 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);\r
4483 @endcode\r
4484**/\r
4485#define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7\r
4486\r
4487\r
4488/**\r
4489 Package. Uncore C-box 6 perfmon counter 2.\r
4490\r
4491 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)\r
4492 @param EAX Lower 32-bits of MSR value.\r
4493 @param EDX Upper 32-bits of MSR value.\r
4494\r
4495 <b>Example usage</b>\r
4496 @code\r
4497 UINT64 Msr;\r
4498\r
4499 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);\r
4500 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);\r
4501 @endcode\r
4502**/\r
4503#define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8\r
4504\r
4505\r
4506/**\r
4507 Package. Uncore C-box 6 perfmon counter 3.\r
4508\r
4509 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)\r
4510 @param EAX Lower 32-bits of MSR value.\r
4511 @param EDX Upper 32-bits of MSR value.\r
4512\r
4513 <b>Example usage</b>\r
4514 @code\r
4515 UINT64 Msr;\r
4516\r
4517 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);\r
4518 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);\r
4519 @endcode\r
4520**/\r
4521#define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9\r
4522\r
4523\r
4524/**\r
4525 Package. Uncore C-box 7 perfmon local box wide control.\r
4526\r
4527 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)\r
4528 @param EAX Lower 32-bits of MSR value.\r
4529 @param EDX Upper 32-bits of MSR value.\r
4530\r
4531 <b>Example usage</b>\r
4532 @code\r
4533 UINT64 Msr;\r
4534\r
4535 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);\r
4536 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);\r
4537 @endcode\r
4538**/\r
4539#define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4\r
4540\r
4541\r
4542/**\r
4543 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r
4544\r
4545 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)\r
4546 @param EAX Lower 32-bits of MSR value.\r
4547 @param EDX Upper 32-bits of MSR value.\r
4548\r
4549 <b>Example usage</b>\r
4550 @code\r
4551 UINT64 Msr;\r
4552\r
4553 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);\r
4554 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);\r
4555 @endcode\r
4556**/\r
4557#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0\r
4558\r
4559\r
4560/**\r
4561 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r
4562\r
4563 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)\r
4564 @param EAX Lower 32-bits of MSR value.\r
4565 @param EDX Upper 32-bits of MSR value.\r
4566\r
4567 <b>Example usage</b>\r
4568 @code\r
4569 UINT64 Msr;\r
4570\r
4571 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);\r
4572 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);\r
4573 @endcode\r
4574**/\r
4575#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1\r
4576\r
4577\r
4578/**\r
4579 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r
4580\r
4581 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)\r
4582 @param EAX Lower 32-bits of MSR value.\r
4583 @param EDX Upper 32-bits of MSR value.\r
4584\r
4585 <b>Example usage</b>\r
4586 @code\r
4587 UINT64 Msr;\r
4588\r
4589 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);\r
4590 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);\r
4591 @endcode\r
4592**/\r
4593#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2\r
4594\r
4595\r
4596/**\r
4597 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r
4598\r
4599 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)\r
4600 @param EAX Lower 32-bits of MSR value.\r
4601 @param EDX Upper 32-bits of MSR value.\r
4602\r
4603 <b>Example usage</b>\r
4604 @code\r
4605 UINT64 Msr;\r
4606\r
4607 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);\r
4608 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);\r
4609 @endcode\r
4610**/\r
4611#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3\r
4612\r
4613\r
4614/**\r
4615 Package. Uncore C-box 7 perfmon box wide filter.\r
4616\r
4617 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)\r
4618 @param EAX Lower 32-bits of MSR value.\r
4619 @param EDX Upper 32-bits of MSR value.\r
4620\r
4621 <b>Example usage</b>\r
4622 @code\r
4623 UINT64 Msr;\r
4624\r
4625 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);\r
4626 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);\r
4627 @endcode\r
4628**/\r
4629#define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4\r
4630\r
4631\r
4632/**\r
4633 Package. Uncore C-box 7 perfmon counter 0.\r
4634\r
4635 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)\r
4636 @param EAX Lower 32-bits of MSR value.\r
4637 @param EDX Upper 32-bits of MSR value.\r
4638\r
4639 <b>Example usage</b>\r
4640 @code\r
4641 UINT64 Msr;\r
4642\r
4643 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);\r
4644 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);\r
4645 @endcode\r
4646**/\r
4647#define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6\r
4648\r
4649\r
4650/**\r
4651 Package. Uncore C-box 7 perfmon counter 1.\r
4652\r
4653 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)\r
4654 @param EAX Lower 32-bits of MSR value.\r
4655 @param EDX Upper 32-bits of MSR value.\r
4656\r
4657 <b>Example usage</b>\r
4658 @code\r
4659 UINT64 Msr;\r
4660\r
4661 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);\r
4662 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);\r
4663 @endcode\r
4664**/\r
4665#define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7\r
4666\r
4667\r
4668/**\r
4669 Package. Uncore C-box 7 perfmon counter 2.\r
4670\r
4671 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)\r
4672 @param EAX Lower 32-bits of MSR value.\r
4673 @param EDX Upper 32-bits of MSR value.\r
4674\r
4675 <b>Example usage</b>\r
4676 @code\r
4677 UINT64 Msr;\r
4678\r
4679 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);\r
4680 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);\r
4681 @endcode\r
4682**/\r
4683#define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8\r
4684\r
4685\r
4686/**\r
4687 Package. Uncore C-box 7 perfmon counter 3.\r
4688\r
4689 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)\r
4690 @param EAX Lower 32-bits of MSR value.\r
4691 @param EDX Upper 32-bits of MSR value.\r
4692\r
4693 <b>Example usage</b>\r
4694 @code\r
4695 UINT64 Msr;\r
4696\r
4697 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);\r
4698 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);\r
4699 @endcode\r
4700**/\r
4701#define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9\r
4702\r
4703#endif\r
EFI Development Kit II mirror for PVE