[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / SkylakeMsr.h

/** @file\r
  MSR Definitions for Intel processors based on the Skylake microarchitecture.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15.\r
\r
**/\r
\r
#ifndef __SKYLAKE_MSR_H__\r
#define __SKYLAKE_MSR_H__\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
/**\r
  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
  RW if MSR_PLATFORM_INFO.[28] = 1.\r
\r
  @param  ECX  MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);\r
  @endcode\r
  @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_SKYLAKE_TURBO_RATIO_LIMIT            0x000001AD\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
    /// limit of 1 core active.\r
    ///\r
    UINT32  Maximum1C:8;\r
    ///\r
    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
    /// limit of 2 core active.\r
    ///\r
    UINT32  Maximum2C:8;\r
    ///\r
    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
    /// limit of 3 core active.\r
    ///\r
    UINT32  Maximum3C:8;\r
    ///\r
    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
    /// limit of 4 core active.\r
    ///\r
    UINT32  Maximum4C:8;\r
    UINT32  Reserved:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;\r
\r
\r
/**\r
  Thread. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-4)\r
  that points to the MSR containing the most recent branch record.\r
\r
  @param  ECX  MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);\r
  AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
#define MSR_SKYLAKE_LASTBRANCH_TOS               0x000001C9\r
\r
\r
/**\r
  Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of\r
  an 128-bit external entropy value for key derivation of an enclave.\r
\r
  @param  ECX  MSR_SKYLAKE_SGXOWNER0 (0x00000300)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);\r
  @endcode\r
  @note MSR_SKYLAKE_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.\r
**/\r
#define MSR_SKYLAKE_SGXOWNER0                    0x00000300\r
\r
\r
/**\r
  Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of\r
  an 128-bit external entropy value for key derivation of an enclave.\r
\r
  @param  ECX  MSR_SKYLAKE_SGXOWNER1 (0x00000301)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);\r
  @endcode\r
  @note MSR_SKYLAKE_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.\r
**/\r
#define MSR_SKYLAKE_SGXOWNER1                    0x00000301\r
\r
\r
/**\r
  See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring\r
  Version 4.".\r
\r
  @param  ECX  MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS);\r
  AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS      0x0000038E\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Thread. Ovf_PMC0.\r
    ///\r
    UINT32  Ovf_PMC0:1;\r
    ///\r
    /// [Bit 1] Thread. Ovf_PMC1.\r
    ///\r
    UINT32  Ovf_PMC1:1;\r
    ///\r
    /// [Bit 2] Thread. Ovf_PMC2.\r
    ///\r
    UINT32  Ovf_PMC2:1;\r
    ///\r
    /// [Bit 3] Thread. Ovf_PMC3.\r
    ///\r
    UINT32  Ovf_PMC3:1;\r
    ///\r
    /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
    ///\r
    UINT32  Ovf_PMC4:1;\r
    ///\r
    /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
    ///\r
    UINT32  Ovf_PMC5:1;\r
    ///\r
    /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
    ///\r
    UINT32  Ovf_PMC6:1;\r
    ///\r
    /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
    ///\r
    UINT32  Ovf_PMC7:1;\r
    UINT32  Reserved1:24;\r
    ///\r
    /// [Bit 32] Thread. Ovf_FixedCtr0.\r
    ///\r
    UINT32  Ovf_FixedCtr0:1;\r
    ///\r
    /// [Bit 33] Thread. Ovf_FixedCtr1.\r
    ///\r
    UINT32  Ovf_FixedCtr1:1;\r
    ///\r
    /// [Bit 34] Thread. Ovf_FixedCtr2.\r
    ///\r
    UINT32  Ovf_FixedCtr2:1;\r
    UINT32  Reserved2:20;\r
    ///\r
    /// [Bit 55] Thread. Trace_ToPA_PMI.\r
    ///\r
    UINT32  Trace_ToPA_PMI:1;\r
    UINT32  Reserved3:2;\r
    ///\r
    /// [Bit 58] Thread. LBR_Frz.\r
    ///\r
    UINT32  LBR_Frz:1;\r
    ///\r
    /// [Bit 59] Thread. CTR_Frz.\r
    ///\r
    UINT32  CTR_Frz:1;\r
    ///\r
    /// [Bit 60] Thread. ASCI.\r
    ///\r
    UINT32  ASCI:1;\r
    ///\r
    /// [Bit 61] Thread. Ovf_Uncore.\r
    ///\r
    UINT32  Ovf_Uncore:1;\r
    ///\r
    /// [Bit 62] Thread. Ovf_BufDSSAVE.\r
    ///\r
    UINT32  Ovf_BufDSSAVE:1;\r
    ///\r
    /// [Bit 63] Thread. CondChgd.\r
    ///\r
    UINT32  CondChgd:1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
\r
/**\r
  See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring\r
  Version 4.".\r
\r
  @param  ECX  MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);\r
  AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
**/\r
#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
\r
/**\r
  MSR information returned for MSR index\r
  #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
    ///\r
    UINT32  Ovf_PMC0:1;\r
    ///\r
    /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
    ///\r
    UINT32  Ovf_PMC1:1;\r
    ///\r
    /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
    ///\r
    UINT32  Ovf_PMC2:1;\r
    ///\r
    /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
    ///\r
    UINT32  Ovf_PMC3:1;\r
    ///\r
    /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
    ///\r
    UINT32  Ovf_PMC4:1;\r
    ///\r
    /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
    ///\r
    UINT32  Ovf_PMC5:1;\r
    ///\r
    /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
    ///\r
    UINT32  Ovf_PMC6:1;\r
    ///\r
    /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
    ///\r
    UINT32  Ovf_PMC7:1;\r
    UINT32  Reserved1:24;\r
    ///\r
    /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
    ///\r
    UINT32  Ovf_FixedCtr0:1;\r
    ///\r
    /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
    ///\r
    UINT32  Ovf_FixedCtr1:1;\r
    ///\r
    /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
    ///\r
    UINT32  Ovf_FixedCtr2:1;\r
    UINT32  Reserved2:20;\r
    ///\r
    /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.\r
    ///\r
    UINT32  Trace_ToPA_PMI:1;\r
    UINT32  Reserved3:2;\r
    ///\r
    /// [Bit 58] Thread. Set 1 to clear LBR_Frz.\r
    ///\r
    UINT32  LBR_Frz:1;\r
    ///\r
    /// [Bit 59] Thread. Set 1 to clear CTR_Frz.\r
    ///\r
    UINT32  CTR_Frz:1;\r
    ///\r
    /// [Bit 60] Thread. Set 1 to clear ASCI.\r
    ///\r
    UINT32  ASCI:1;\r
    ///\r
    /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
    ///\r
    UINT32  Ovf_Uncore:1;\r
    ///\r
    /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
    ///\r
    UINT32  Ovf_BufDSSAVE:1;\r
    ///\r
    /// [Bit 63] Thread. Set 1 to clear CondChgd.\r
    ///\r
    UINT32  CondChgd:1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
\r
\r
/**\r
  See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring\r
  Version 4.".\r
\r
  @param  ECX  MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);\r
  AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
**/\r
#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET  0x00000391\r
\r
/**\r
  MSR information returned for MSR index\r
  #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.\r
    ///\r
    UINT32  Ovf_PMC0:1;\r
    ///\r
    /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.\r
    ///\r
    UINT32  Ovf_PMC1:1;\r
    ///\r
    /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.\r
    ///\r
    UINT32  Ovf_PMC2:1;\r
    ///\r
    /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.\r
    ///\r
    UINT32  Ovf_PMC3:1;\r
    ///\r
    /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).\r
    ///\r
    UINT32  Ovf_PMC4:1;\r
    ///\r
    /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).\r
    ///\r
    UINT32  Ovf_PMC5:1;\r
    ///\r
    /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).\r
    ///\r
    UINT32  Ovf_PMC6:1;\r
    ///\r
    /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).\r
    ///\r
    UINT32  Ovf_PMC7:1;\r
    UINT32  Reserved1:24;\r
    ///\r
    /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.\r
    ///\r
    UINT32  Ovf_FixedCtr0:1;\r
    ///\r
    /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.\r
    ///\r
    UINT32  Ovf_FixedCtr1:1;\r
    ///\r
    /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.\r
    ///\r
    UINT32  Ovf_FixedCtr2:1;\r
    UINT32  Reserved2:20;\r
    ///\r
    /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.\r
    ///\r
    UINT32  Trace_ToPA_PMI:1;\r
    UINT32  Reserved3:2;\r
    ///\r
    /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.\r
    ///\r
    UINT32  LBR_Frz:1;\r
    ///\r
    /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.\r
    ///\r
    UINT32  CTR_Frz:1;\r
    ///\r
    /// [Bit 60] Thread. Set 1 to cause ASCI = 1.\r
    ///\r
    UINT32  ASCI:1;\r
    ///\r
    /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.\r
    ///\r
    UINT32  Ovf_Uncore:1;\r
    ///\r
    /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.\r
    ///\r
    UINT32  Ovf_BufDSSAVE:1;\r
    UINT32  Reserved4:1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
\r
\r
/**\r
  Thread. FrontEnd Precise Event Condition Select (R/W).\r
\r
  @param  ECX  MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_PEBS_FRONTEND_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);\r
  AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.\r
**/\r
#define MSR_SKYLAKE_PEBS_FRONTEND                0x000003F7\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 2:0] Event Code Select.\r
    ///\r
    UINT32  EventCodeSelect:3;\r
    UINT32  Reserved1:1;\r
    ///\r
    /// [Bit 4] Event Code Select High.\r
    ///\r
    UINT32  EventCodeSelectHigh:1;\r
    UINT32  Reserved2:3;\r
    ///\r
    /// [Bits 19:8] IDQ_Bubble_Length Specifier.\r
    ///\r
    UINT32  IDQ_Bubble_Length:12;\r
    ///\r
    /// [Bits 22:20] IDQ_Bubble_Width Specifier.\r
    ///\r
    UINT32  IDQ_Bubble_Width:3;\r
    UINT32  Reserved3:9;\r
    UINT32  Reserved4:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_PEBS_FRONTEND_REGISTER;\r
\r
\r
/**\r
  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL\r
  Domains.".\r
\r
  @param  ECX  MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r
  @endcode\r
  @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_SKYLAKE_PP0_ENERGY_STATUS            0x00000639\r
\r
\r
/**\r
  Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both\r
  platform vendor hardware implementation and BIOS enablement support it. This\r
  MSR will read 0 if not valid.\r
\r
  @param  ECX  MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);\r
  @endcode\r
  @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.\r
**/\r
#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER      0x0000064D\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 31:0] Total energy consumed by all devices in the platform that\r
    /// receive power from integrated power delivery mechanism, Included\r
    /// platform devices are processor cores, SOC, memory, add-on or\r
    /// peripheral devices that get powered directly from the platform power\r
    /// delivery means. The energy units are specified in the\r
    /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.\r
    ///\r
    UINT32  TotalEnergy:32;\r
    UINT32  Reserved:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER;\r
\r
\r
/**\r
  Thread. Productive Performance Count. (R/O). Hardware's view of workload\r
  scalability. See Section 14.4.5.1.\r
\r
  @param  ECX  MSR_SKYLAKE_PPERF (0x0000064E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);\r
  @endcode\r
  @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.\r
**/\r
#define MSR_SKYLAKE_PPERF                        0x0000064E\r
\r
\r
/**\r
  Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
  refers to processor core frequency).\r
\r
  @param  ECX  MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS);\r
  AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS      0x0000064F\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
    /// operating system request due to assertion of external PROCHOT.\r
    ///\r
    UINT32  PROCHOT_Status:1;\r
    ///\r
    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
    /// operating system request due to a thermal event.\r
    ///\r
    UINT32  ThermalStatus:1;\r
    UINT32  Reserved1:2;\r
    ///\r
    /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is\r
    /// reduced below the operating system request due to residency state\r
    /// regulation limit.\r
    ///\r
    UINT32  ResidencyStateRegulationStatus:1;\r
    ///\r
    /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
    /// is reduced below the operating system request due to Running Average\r
    /// Thermal Limit (RATL).\r
    ///\r
    UINT32  RunningAverageThermalLimitStatus:1;\r
    ///\r
    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
    /// below the operating system request due to a thermal alert from a\r
    /// processor Voltage Regulator (VR).\r
    ///\r
    UINT32  VRThermAlertStatus:1;\r
    ///\r
    /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is\r
    /// reduced below the operating system request due to VR thermal design\r
    /// current limit.\r
    ///\r
    UINT32  VRThermDesignCurrentStatus:1;\r
    ///\r
    /// [Bit 8] Other Status (R0) When set, frequency is reduced below the\r
    /// operating system request due to electrical or other constraints.\r
    ///\r
    UINT32  OtherStatus:1;\r
    UINT32  Reserved2:1;\r
    ///\r
    /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
    /// set, frequency is reduced below the operating system request due to\r
    /// package/platform-level power limiting PL1.\r
    ///\r
    UINT32  PL1Status:1;\r
    ///\r
    /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
    /// set, frequency is reduced below the operating system request due to\r
    /// package/platform-level power limiting PL2/PL3.\r
    ///\r
    UINT32  PL2Status:1;\r
    ///\r
    /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r
    /// below the operating system request due to multi-core turbo limits.\r
    ///\r
    UINT32  MaxTurboLimitStatus:1;\r
    ///\r
    /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
    /// is reduced below the operating system request due to Turbo transition\r
    /// attenuation. This prevents performance degradation due to frequent\r
    /// operating ratio changes.\r
    ///\r
    UINT32  TurboTransitionAttenuationStatus:1;\r
    UINT32  Reserved3:2;\r
    ///\r
    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit\r
    /// has asserted since the log bit was last cleared. This log bit will\r
    /// remain set until cleared by software writing 0.\r
    ///\r
    UINT32  PROCHOT_Log:1;\r
    ///\r
    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit\r
    /// has asserted since the log bit was last cleared. This log bit will\r
    /// remain set until cleared by software writing 0.\r
    ///\r
    UINT32  ThermalLog:1;\r
    UINT32  Reserved4:2;\r
    ///\r
    /// [Bit 20] Residency State Regulation Log  When set, indicates that the\r
    /// Residency State Regulation Status bit has asserted since the log bit\r
    /// was last cleared. This log bit will remain set until cleared by\r
    /// software writing 0.\r
    ///\r
    UINT32  ResidencyStateRegulationLog:1;\r
    ///\r
    /// [Bit 21] Running Average Thermal Limit Log  When set, indicates that\r
    /// the RATL Status bit has asserted since the log bit was last cleared.\r
    /// This log bit will remain set until cleared by software writing 0.\r
    ///\r
    UINT32  RunningAverageThermalLimitLog:1;\r
    ///\r
    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm\r
    /// Alert Status bit has asserted since the log bit was last cleared. This\r
    /// log bit will remain set until cleared by software writing 0.\r
    ///\r
    UINT32  VRThermAlertLog:1;\r
    ///\r
    /// [Bit 23] VR Thermal Design Current Log  When set, indicates that the\r
    /// VR TDC Status bit has asserted since the log bit was last cleared.\r
    /// This log bit will remain set until cleared by software writing 0.\r
    ///\r
    UINT32  VRThermalDesignCurrentLog:1;\r
    ///\r
    /// [Bit 24] Other Log  When set, indicates that the Other Status bit has\r
    /// asserted since the log bit was last cleared. This log bit will remain\r
    /// set until cleared by software writing 0.\r
    ///\r
    UINT32  OtherLog:1;\r
    UINT32  Reserved5:1;\r
    ///\r
    /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log  When set,\r
    /// indicates that the Package or Platform Level PL1 Power Limiting Status\r
    /// bit has asserted since the log bit was last cleared. This log bit will\r
    /// remain set until cleared by software writing 0.\r
    ///\r
    UINT32  PL1Log:1;\r
    ///\r
    /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
    /// indicates that the Package or Platform Level PL2/PL3 Power Limiting\r
    /// Status bit has asserted since the log bit was last cleared. This log\r
    /// bit will remain set until cleared by software writing 0.\r
    ///\r
    UINT32  PL2Log:1;\r
    ///\r
    /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
    /// Limit Status bit has asserted since the log bit was last cleared. This\r
    /// log bit will remain set until cleared by software writing 0.\r
    ///\r
    UINT32  MaxTurboLimitLog:1;\r
    ///\r
    /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
    /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
    /// was last cleared. This log bit will remain set until cleared by\r
    /// software writing 0.\r
    ///\r
    UINT32  TurboTransitionAttenuationLog:1;\r
    UINT32  Reserved6:2;\r
    UINT32  Reserved7:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER;\r
\r
\r
/**\r
  Package. HDC Configuration (R/W)..\r
\r
  @param  ECX  MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);\r
  AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.\r
**/\r
#define MSR_SKYLAKE_PKG_HDC_CONFIG               0x00000652\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 2:0] PKG_Cx_Monitor.  Configures Package Cx state threshold for\r
    /// MSR_PKG_HDC_DEEP_RESIDENCY.\r
    ///\r
    UINT32  PKG_Cx_Monitor:3;\r
    UINT32  Reserved1:29;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER;\r
\r
\r
/**\r
  Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.\r
\r
  @param  ECX  MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);\r
  @endcode\r
  @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.\r
**/\r
#define MSR_SKYLAKE_CORE_HDC_RESIDENCY           0x00000653\r
\r
\r
/**\r
  Package. Accumulate the cycles the package was in C2 state and at least one\r
  logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.\r
\r
  @param  ECX  MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);\r
  @endcode\r
  @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.\r
**/\r
#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY    0x00000655\r
\r
\r
/**\r
  Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.\r
\r
  @param  ECX  MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);\r
  @endcode\r
  @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.\r
**/\r
#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY       0x00000656\r
\r
\r
/**\r
  Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate\r
  as the TSC. The increment each cycle is weighted by the number of processor\r
  cores in the package that reside in C0. If N cores are simultaneously in C0,\r
  then each cycle the counter increments by N.\r
\r
  @param  ECX  MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);\r
  @endcode\r
  @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.\r
**/\r
#define MSR_SKYLAKE_WEIGHTED_CORE_C0             0x00000658\r
\r
\r
/**\r
  Package. Any Core C0 Residency. (R/O). Increment at the same rate as the\r
  TSC. The increment each cycle is one if any processor core in the package is\r
  in C0.\r
\r
  @param  ECX  MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);\r
  @endcode\r
  @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.\r
**/\r
#define MSR_SKYLAKE_ANY_CORE_C0                  0x00000659\r
\r
\r
/**\r
  Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate\r
  as the TSC. The increment each cycle is one if any processor graphic\r
  device's compute engines are in C0.\r
\r
  @param  ECX  MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);\r
  @endcode\r
  @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.\r
**/\r
#define MSR_SKYLAKE_ANY_GFXE_C0                  0x0000065A\r
\r
\r
/**\r
  Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment\r
  at the same rate as the TSC. The increment each cycle is one if at least one\r
  compute engine of the processor graphics is in C0 and at least one processor\r
  core in the package is also in C0.\r
\r
  @param  ECX  MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);\r
  @endcode\r
  @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.\r
**/\r
#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0         0x0000065B\r
\r
\r
/**\r
  Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to\r
  limit power consumption of the platform devices to the specified values. The\r
  Long Duration power consumption is specified via Platform_Power_Limit_1 and\r
  Platform_Power_Limit_1_Time. The Short Duration power consumption limit is\r
  specified via the Platform_Power_Limit_2 with duration chosen by the\r
  processor. The processor implements an exponential-weighted algorithm in the\r
  placement of the time windows.\r
\r
  @param  ECX  MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);\r
  AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.\r
**/\r
#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT         0x0000065C\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which\r
    /// the platform must not exceed over a time window as specified by\r
    /// Power_Limit_1_TIME field. The default value is the Thermal Design\r
    /// Power (TDP) and varies with product skus. The unit is specified in\r
    /// MSR_RAPLPOWER_UNIT.\r
    ///\r
    UINT32  PlatformPowerLimit1:15;\r
    ///\r
    /// [Bit 15] Enable Platform Power Limit #1. When set, enables the\r
    /// processor to apply control policy such that the platform power does\r
    /// not exceed Platform Power limit #1 over the time window specified by\r
    /// Power Limit #1 Time Window.\r
    ///\r
    UINT32  EnablePlatformPowerLimit1:1;\r
    ///\r
    /// [Bit 16] Platform Clamping Limitation #1. When set, allows the\r
    /// processor to go below the OS requested P states in order to maintain\r
    /// the power below specified Platform Power Limit #1 value. This bit is\r
    /// writeable only when CPUID (EAX=6):EAX[4] is set.\r
    ///\r
    UINT32  PlatformClampingLimitation1:1;\r
    ///\r
    /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the\r
    /// duration of the time window over which Platform Power Limit 1 value\r
    /// should be maintained for sustained long duration. This field is made\r
    /// up of two numbers from the following equation: Time Window = (float)\r
    /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =\r
    /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is\r
    /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,\r
    /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].\r
    ///\r
    UINT32  Time:7;\r
    UINT32  Reserved1:8;\r
    ///\r
    /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which\r
    /// the platform must not exceed over the Short Duration time window\r
    /// chosen by the processor. The recommended default value is 1.25 times\r
    /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).\r
    ///\r
    UINT32  PlatformPowerLimit2:15;\r
    ///\r
    /// [Bit 47] Enable Platform Power Limit #2. When set, enables the\r
    /// processor to apply control policy such that the platform power does\r
    /// not exceed Platform Power limit #2 over the Short Duration time window.\r
    ///\r
    UINT32  EnablePlatformPowerLimit2:1;\r
    ///\r
    /// [Bit 48] Platform Clamping Limitation #2. When set, allows the\r
    /// processor to go below the OS requested P states in order to maintain\r
    /// the power below specified Platform Power Limit #2 value.\r
    ///\r
    UINT32  PlatformClampingLimitation2:1;\r
    UINT32  Reserved2:14;\r
    ///\r
    /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR\r
    /// until system RESET.\r
    ///\r
    UINT32  Lock:1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER;\r
\r
\r
/**\r
  Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last\r
  branch record registers on the last branch record stack. This part of the\r
  stack contains pointers to the source instruction. See also: -  Last Branch\r
  Record Stack TOS at 1C9H -  Section 17.10.\r
\r
  @param  ECX  MSR_SKYLAKE_LASTBRANCH_n_FROM_IP\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);\r
  AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r
  @{\r
**/\r
#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP        0x00000690\r
#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP        0x00000691\r
#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP        0x00000692\r
#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP        0x00000693\r
#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP        0x00000694\r
#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP        0x00000695\r
#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP        0x00000696\r
#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP        0x00000697\r
#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP        0x00000698\r
#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP        0x00000699\r
#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP        0x0000069A\r
#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP        0x0000069B\r
#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP        0x0000069C\r
#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP        0x0000069D\r
#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP        0x0000069E\r
#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP        0x0000069F\r
/// @}\r
\r
\r
/**\r
  Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r
  (frequency refers to processor graphics frequency).\r
\r
  @param  ECX  MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS);\r
  AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.\r
**/\r
#define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS  0x000006B0\r
\r
/**\r
  MSR information returned for MSR index\r
  #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
    /// assertion of external PROCHOT.\r
    ///\r
    UINT32  PROCHOT_Status:1;\r
    ///\r
    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
    /// thermal event.\r
    ///\r
    UINT32  ThermalStatus:1;\r
    UINT32  Reserved1:3;\r
    ///\r
    /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
    /// is reduced due to running average thermal limit.\r
    ///\r
    UINT32  RunningAverageThermalLimitStatus:1;\r
    ///\r
    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
    /// to a thermal alert from a processor Voltage Regulator.\r
    ///\r
    UINT32  VRThermAlertStatus:1;\r
    ///\r
    /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
    /// reduced due to VR TDC limit.\r
    ///\r
    UINT32  VRThermalDesignCurrentStatus:1;\r
    ///\r
    /// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
    /// electrical or other constraints.\r
    ///\r
    UINT32  OtherStatus:1;\r
    UINT32  Reserved2:1;\r
    ///\r
    /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
    /// set, frequency is reduced due to package/platform-level power limiting\r
    /// PL1.\r
    ///\r
    UINT32  PL1Status:1;\r
    ///\r
    /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
    /// set, frequency is reduced due to package/platform-level power limiting\r
    /// PL2/PL3.\r
    ///\r
    UINT32  PL2Status:1;\r
    ///\r
    /// [Bit 12] Inefficient Operation Status (R0) When set, processor\r
    /// graphics frequency is operating below target frequency.\r
    ///\r
    UINT32  InefficientOperationStatus:1;\r
    UINT32  Reserved3:3;\r
    ///\r
    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit\r
    /// has asserted since the log bit was last cleared. This log bit will\r
    /// remain set until cleared by software writing 0.\r
    ///\r
    UINT32  PROCHOT_Log:1;\r
    ///\r
    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit\r
    /// has asserted since the log bit was last cleared. This log bit will\r
    /// remain set until cleared by software writing 0.\r
    ///\r
    UINT32  ThermalLog:1;\r
    UINT32  Reserved4:3;\r
    ///\r
    /// [Bit 21] Running Average Thermal Limit Log  When set, indicates that\r
    /// the RATL Status bit has asserted since the log bit was last cleared.\r
    /// This log bit will remain set until cleared by software writing 0.\r
    ///\r
    UINT32  RunningAverageThermalLimitLog:1;\r
    ///\r
    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm\r
    /// Alert Status bit has asserted since the log bit was last cleared. This\r
    /// log bit will remain set until cleared by software writing 0.\r
    ///\r
    UINT32  VRThermAlertLog:1;\r
    ///\r
    /// [Bit 23] VR Thermal Design Current Log  When set, indicates that the\r
    /// VR Therm Alert Status bit has asserted since the log bit was last\r
    /// cleared. This log bit will remain set until cleared by software\r
    /// writing 0.\r
    ///\r
    UINT32  VRThermalDesignCurrentLog:1;\r
    ///\r
    /// [Bit 24] Other Log  When set, indicates that the OTHER Status bit has\r
    /// asserted since the log bit was last cleared. This log bit will remain\r
    /// set until cleared by software writing 0.\r
    ///\r
    UINT32  OtherLog:1;\r
    UINT32  Reserved5:1;\r
    ///\r
    /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log  When set,\r
    /// indicates that the Package/Platform Level PL1 Power Limiting Status\r
    /// bit has asserted since the log bit was last cleared. This log bit will\r
    /// remain set until cleared by software writing 0.\r
    ///\r
    UINT32  PL1Log:1;\r
    ///\r
    /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
    /// indicates that the Package/Platform Level PL2 Power Limiting Status\r
    /// bit has asserted since the log bit was last cleared. This log bit will\r
    /// remain set until cleared by software writing 0.\r
    ///\r
    UINT32  PL2Log:1;\r
    ///\r
    /// [Bit 28] Inefficient Operation Log When set, indicates that the\r
    /// Inefficient Operation Status bit has asserted since the log bit was\r
    /// last cleared. This log bit will remain set until cleared by software\r
    /// writing 0.\r
    ///\r
    UINT32  InefficientOperationLog:1;\r
    UINT32  Reserved6:3;\r
    UINT32  Reserved7:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r
\r
\r
/**\r
  Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r
  (frequency refers to ring interconnect in the uncore).\r
\r
  @param  ECX  MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS);\r
  AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r
**/\r
#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS      0x000006B1\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
    /// assertion of external PROCHOT.\r
    ///\r
    UINT32  PROCHOT_Status:1;\r
    ///\r
    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
    /// thermal event.\r
    ///\r
    UINT32  ThermalStatus:1;\r
    UINT32  Reserved1:3;\r
    ///\r
    /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
    /// is reduced due to running average thermal limit.\r
    ///\r
    UINT32  RunningAverageThermalLimitStatus:1;\r
    ///\r
    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
    /// to a thermal alert from a processor Voltage Regulator.\r
    ///\r
    UINT32  VRThermAlertStatus:1;\r
    ///\r
    /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
    /// reduced due to VR TDC limit.\r
    ///\r
    UINT32  VRThermalDesignCurrentStatus:1;\r
    ///\r
    /// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
    /// electrical or other constraints.\r
    ///\r
    UINT32  OtherStatus:1;\r
    UINT32  Reserved2:1;\r
    ///\r
    /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
    /// set, frequency is reduced due to package/Platform-level power limiting\r
    /// PL1.\r
    ///\r
    UINT32  PL1Status:1;\r
    ///\r
    /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
    /// set, frequency is reduced due to package/Platform-level power limiting\r
    /// PL2/PL3.\r
    ///\r
    UINT32  PL2Status:1;\r
    UINT32  Reserved3:4;\r
    ///\r
    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit\r
    /// has asserted since the log bit was last cleared. This log bit will\r
    /// remain set until cleared by software writing 0.\r
    ///\r
    UINT32  PROCHOT_Log:1;\r
    ///\r
    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit\r
    /// has asserted since the log bit was last cleared. This log bit will\r
    /// remain set until cleared by software writing 0.\r
    ///\r
    UINT32  ThermalLog:1;\r
    UINT32  Reserved4:3;\r
    ///\r
    /// [Bit 21] Running Average Thermal Limit Log  When set, indicates that\r
    /// the RATL Status bit has asserted since the log bit was last cleared.\r
    /// This log bit will remain set until cleared by software writing 0.\r
    ///\r
    UINT32  RunningAverageThermalLimitLog:1;\r
    ///\r
    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm\r
    /// Alert Status bit has asserted since the log bit was last cleared. This\r
    /// log bit will remain set until cleared by software writing 0.\r
    ///\r
    UINT32  VRThermAlertLog:1;\r
    ///\r
    /// [Bit 23] VR Thermal Design Current Log  When set, indicates that the\r
    /// VR Therm Alert Status bit has asserted since the log bit was last\r
    /// cleared. This log bit will remain set until cleared by software\r
    /// writing 0.\r
    ///\r
    UINT32  VRThermalDesignCurrentLog:1;\r
    ///\r
    /// [Bit 24] Other Log  When set, indicates that the OTHER Status bit has\r
    /// asserted since the log bit was last cleared. This log bit will remain\r
    /// set until cleared by software writing 0.\r
    ///\r
    UINT32  OtherLog:1;\r
    UINT32  Reserved5:1;\r
    ///\r
    /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log  When set,\r
    /// indicates that the Package/Platform Level PL1 Power Limiting Status\r
    /// bit has asserted since the log bit was last cleared. This log bit will\r
    /// remain set until cleared by software writing 0.\r
    ///\r
    UINT32  PL1Log:1;\r
    ///\r
    /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
    /// indicates that the Package/Platform Level PL2 Power Limiting Status\r
    /// bit has asserted since the log bit was last cleared. This log bit will\r
    /// remain set until cleared by software writing 0.\r
    ///\r
    UINT32  PL2Log:1;\r
    UINT32  Reserved6:4;\r
    UINT32  Reserved7:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER;\r
\r
\r
/**\r
  Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch\r
  record registers on the last branch record stack. This part of the stack\r
  contains pointers to the destination instruction. See also: -  Last Branch\r
  Record Stack TOS at 1C9H -  Section 17.10.\r
\r
  @param  ECX  MSR_SKYLAKE_LASTBRANCH_n_TO_IP\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);\r
  AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.\r
        MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r
  @{\r
**/\r
#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP          0x000006D0\r
#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP          0x000006D1\r
#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP          0x000006D2\r
#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP          0x000006D3\r
#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP          0x000006D4\r
#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP          0x000006D5\r
#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP          0x000006D6\r
#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP          0x000006D7\r
#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP          0x000006D8\r
#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP          0x000006D9\r
#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP          0x000006DA\r
#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP          0x000006DB\r
#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP          0x000006DC\r
#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP          0x000006DD\r
#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP          0x000006DE\r
#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP          0x000006DF\r
/// @}\r
\r
\r
/**\r
  Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet\r
  of last branch record registers on the last branch record stack. This part\r
  of the stack contains flag, TSX-related and elapsed cycle information. See\r
  also: -  Last Branch Record Stack TOS at 1C9H -  Section 17.7.1, "LBR\r
  Stack.".\r
\r
  @param  ECX  MSR_SKYLAKE_LBR_INFO_n\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);\r
  AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_LBR_INFO_0  is defined as MSR_LBR_INFO_0  in SDM.\r
        MSR_SKYLAKE_LBR_INFO_1  is defined as MSR_LBR_INFO_1  in SDM.\r
        MSR_SKYLAKE_LBR_INFO_2  is defined as MSR_LBR_INFO_2  in SDM.\r
        MSR_SKYLAKE_LBR_INFO_3  is defined as MSR_LBR_INFO_3  in SDM.\r
        MSR_SKYLAKE_LBR_INFO_4  is defined as MSR_LBR_INFO_4  in SDM.\r
        MSR_SKYLAKE_LBR_INFO_5  is defined as MSR_LBR_INFO_5  in SDM.\r
        MSR_SKYLAKE_LBR_INFO_6  is defined as MSR_LBR_INFO_6  in SDM.\r
        MSR_SKYLAKE_LBR_INFO_7  is defined as MSR_LBR_INFO_7  in SDM.\r
        MSR_SKYLAKE_LBR_INFO_8  is defined as MSR_LBR_INFO_8  in SDM.\r
        MSR_SKYLAKE_LBR_INFO_9  is defined as MSR_LBR_INFO_9  in SDM.\r
        MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.\r
        MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.\r
  @{\r
**/\r
#define MSR_SKYLAKE_LBR_INFO_0                   0x00000DC0\r
#define MSR_SKYLAKE_LBR_INFO_1                   0x00000DC1\r
#define MSR_SKYLAKE_LBR_INFO_2                   0x00000DC2\r
#define MSR_SKYLAKE_LBR_INFO_3                   0x00000DC3\r
#define MSR_SKYLAKE_LBR_INFO_4                   0x00000DC4\r
#define MSR_SKYLAKE_LBR_INFO_5                   0x00000DC5\r
#define MSR_SKYLAKE_LBR_INFO_6                   0x00000DC6\r
#define MSR_SKYLAKE_LBR_INFO_7                   0x00000DC7\r
#define MSR_SKYLAKE_LBR_INFO_8                   0x00000DC8\r
#define MSR_SKYLAKE_LBR_INFO_9                   0x00000DC9\r
#define MSR_SKYLAKE_LBR_INFO_10                  0x00000DCA\r
#define MSR_SKYLAKE_LBR_INFO_11                  0x00000DCB\r
#define MSR_SKYLAKE_LBR_INFO_12                  0x00000DCC\r
#define MSR_SKYLAKE_LBR_INFO_13                  0x00000DCD\r
#define MSR_SKYLAKE_LBR_INFO_14                  0x00000DCE\r
#define MSR_SKYLAKE_LBR_INFO_15                  0x00000DCF\r
#define MSR_SKYLAKE_LBR_INFO_16                  0x00000DD0\r
#define MSR_SKYLAKE_LBR_INFO_17                  0x00000DD1\r
#define MSR_SKYLAKE_LBR_INFO_18                  0x00000DD2\r
#define MSR_SKYLAKE_LBR_INFO_19                  0x00000DD3\r
#define MSR_SKYLAKE_LBR_INFO_20                  0x00000DD4\r
#define MSR_SKYLAKE_LBR_INFO_21                  0x00000DD5\r
#define MSR_SKYLAKE_LBR_INFO_22                  0x00000DD6\r
#define MSR_SKYLAKE_LBR_INFO_23                  0x00000DD7\r
#define MSR_SKYLAKE_LBR_INFO_24                  0x00000DD8\r
#define MSR_SKYLAKE_LBR_INFO_25                  0x00000DD9\r
#define MSR_SKYLAKE_LBR_INFO_26                  0x00000DDA\r
#define MSR_SKYLAKE_LBR_INFO_27                  0x00000DDB\r
#define MSR_SKYLAKE_LBR_INFO_28                  0x00000DDC\r
#define MSR_SKYLAKE_LBR_INFO_29                  0x00000DDD\r
#define MSR_SKYLAKE_LBR_INFO_30                  0x00000DDE\r
#define MSR_SKYLAKE_LBR_INFO_31                  0x00000DDF\r
/// @}\r
\r
\r
/**\r
  Package. Uncore fixed counter control (R/W).\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL          0x00000394\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved1:20;\r
    ///\r
    /// [Bit 20] Enable overflow propagation.\r
    ///\r
    UINT32  EnableOverflow:1;\r
    UINT32  Reserved2:1;\r
    ///\r
    /// [Bit 22] Enable counting.\r
    ///\r
    UINT32  EnableCounting:1;\r
    UINT32  Reserved3:9;\r
    UINT32  Reserved4:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER;\r
\r
\r
/**\r
  Package. Uncore fixed counter.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR           0x00000395\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 31:0] Current count.\r
    ///\r
    UINT32  CurrentCount:32;\r
    ///\r
    /// [Bits 43:32] Current count.\r
    ///\r
    UINT32  CurrentCountHi:12;\r
    UINT32  Reserved:20;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER;\r
\r
\r
/**\r
  Package. Uncore C-Box configuration information (R/O).\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_CONFIG               0x00000396\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 3:0] Specifies the number of C-Box units with programmable\r
    /// counters (including processor cores and processor graphics),.\r
    ///\r
    UINT32  CBox:4;\r
    UINT32  Reserved1:28;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER;\r
\r
\r
/**\r
  Package. Uncore Arb unit, performance counter 0.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_ARB_PERFCTR0             0x000003B0\r
\r
\r
/**\r
  Package. Uncore Arb unit, performance counter 1.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_ARB_PERFCTR1             0x000003B1\r
\r
\r
/**\r
  Package. Uncore Arb unit, counter 0 event select MSR.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0          0x000003B2\r
\r
\r
/**\r
  Package. Uncore Arb unit, counter 1 event select MSR.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1          0x000003B3\r
\r
\r
/**\r
  Package. Uncore C-Box 0, counter 0 event select MSR.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0        0x00000700\r
\r
\r
/**\r
  Package. Uncore C-Box 0, counter 1 event select MSR.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1        0x00000701\r
\r
\r
/**\r
  Package. Uncore C-Box 0, performance counter 0.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0           0x00000706\r
\r
\r
/**\r
  Package. Uncore C-Box 0, performance counter 1.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1           0x00000707\r
\r
\r
/**\r
  Package. Uncore C-Box 1, counter 0 event select MSR.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0        0x00000710\r
\r
\r
/**\r
  Package. Uncore C-Box 1, counter 1 event select MSR.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1        0x00000711\r
\r
\r
/**\r
  Package. Uncore C-Box 1, performance counter 0.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0           0x00000716\r
\r
\r
/**\r
  Package. Uncore C-Box 1, performance counter 1.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1           0x00000717\r
\r
\r
/**\r
  Package. Uncore C-Box 2, counter 0 event select MSR.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0        0x00000720\r
\r
\r
/**\r
  Package. Uncore C-Box 2, counter 1 event select MSR.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1        0x00000721\r
\r
\r
/**\r
  Package. Uncore C-Box 2, performance counter 0.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0           0x00000726\r
\r
\r
/**\r
  Package. Uncore C-Box 2, performance counter 1.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1           0x00000727\r
\r
\r
/**\r
  Package. Uncore C-Box 3, counter 0 event select MSR.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0        0x00000730\r
\r
\r
/**\r
  Package. Uncore C-Box 3, counter 1 event select MSR.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1        0x00000731\r
\r
\r
/**\r
  Package. Uncore C-Box 3, performance counter 0.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0           0x00000736\r
\r
\r
/**\r
  Package. Uncore C-Box 3, performance counter 1.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1           0x00000737\r
\r
\r
/**\r
  Package. Uncore PMU global control.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL         0x00000E01\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Slice 0 select.\r
    ///\r
    UINT32  PMI_Sel_Slice0:1;\r
    ///\r
    /// [Bit 1] Slice 1 select.\r
    ///\r
    UINT32  PMI_Sel_Slice1:1;\r
    ///\r
    /// [Bit 2] Slice 2 select.\r
    ///\r
    UINT32  PMI_Sel_Slice2:1;\r
    ///\r
    /// [Bit 3] Slice 3 select.\r
    ///\r
    UINT32  PMI_Sel_Slice3:1;\r
    ///\r
    /// [Bit 4] Slice 4select.\r
    ///\r
    UINT32  PMI_Sel_Slice4:1;\r
    UINT32  Reserved1:14;\r
    UINT32  Reserved2:10;\r
    ///\r
    /// [Bit 29] Enable all uncore counters.\r
    ///\r
    UINT32  EN:1;\r
    ///\r
    /// [Bit 30] Enable wake on PMI.\r
    ///\r
    UINT32  WakePMI:1;\r
    ///\r
    /// [Bit 31] Enable Freezing counter when overflow.\r
    ///\r
    UINT32  FREEZE:1;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
\r
\r
/**\r
  Package. Uncore PMU main status.\r
\r
  @param  ECX  MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS);\r
  AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
  @endcode\r
  @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS       0x00000E02\r
\r
/**\r
  MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Fixed counter overflowed.\r
    ///\r
    UINT32  Fixed:1;\r
    ///\r
    /// [Bit 1] An ARB counter overflowed.\r
    ///\r
    UINT32  ARB:1;\r
    UINT32  Reserved1:1;\r
    ///\r
    /// [Bit 3] A CBox counter overflowed (on any slice).\r
    ///\r
    UINT32  CBox:1;\r
    UINT32  Reserved2:28;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
\r
#endif\r