projects / mirror_edk2.git / blame
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| 3adf6316 MK |
1 | /** @file\r |
| 2 | MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| ba1a2d11 | 9 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| 3adf6316 MK |
10 | This program and the accompanying materials\r |
| 11 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 12 | which accompanies this distribution. The full text of the license may be found at\r | |
| 13 | http://opensource.org/licenses/bsd-license.php\r | |
| 14 | \r | |
| 15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 17 | \r | |
| 18 | @par Specification Reference:\r | |
| ba1a2d11 ED |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
| 20 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
| 3adf6316 MK |
21 | \r |
| 22 | **/\r | |
| 23 | \r | |
| 24 | #ifndef __XEON_PHI_MSR_H__\r | |
| 25 | #define __XEON_PHI_MSR_H__\r | |
| 26 | \r | |
| 27 | #include <Register/ArchitecturalMsr.h>\r | |
| 28 | \r | |
| f4c982bf JF |
29 | /**\r |
| 30 | Is Intel(R) Xeon(R) Phi(TM) processor Family?\r | |
| 31 | \r | |
| 32 | @param DisplayFamily Display Family ID\r | |
| 33 | @param DisplayModel Display Model ID\r | |
| 34 | \r | |
| 35 | @retval TRUE Yes, it is.\r | |
| 36 | @retval FALSE No, it isn't.\r | |
| 37 | **/\r | |
| 38 | #define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
| 39 | (DisplayFamily == 0x06 && \\r | |
| 40 | ( \\r | |
| dfb20851 ED |
41 | DisplayModel == 0x57 || \\r |
| 42 | DisplayModel == 0x85 \\r | |
| f4c982bf JF |
43 | ) \\r |
| 44 | )\r | |
| 45 | \r | |
| 3adf6316 MK |
46 | /**\r |
| 47 | Thread. SMI Counter (R/O).\r | |
| 48 | \r | |
| 49 | @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)\r | |
| 50 | @param EAX Lower 32-bits of MSR value.\r | |
| 51 | Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r | |
| 52 | @param EDX Upper 32-bits of MSR value.\r | |
| 53 | Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r | |
| 54 | \r | |
| 55 | <b>Example usage</b>\r | |
| 56 | @code\r | |
| 57 | MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;\r | |
| 58 | \r | |
| 59 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);\r | |
| 60 | @endcode\r | |
| ad8a2f5e | 61 | @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r |
| 3adf6316 MK |
62 | **/\r |
| 63 | #define MSR_XEON_PHI_SMI_COUNT 0x00000034\r | |
| 64 | \r | |
| 65 | /**\r | |
| 66 | MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT\r | |
| 67 | **/\r | |
| 68 | typedef union {\r | |
| 69 | ///\r | |
| 70 | /// Individual bit fields\r | |
| 71 | ///\r | |
| 72 | struct {\r | |
| 73 | ///\r | |
| 74 | /// [Bits 31:0] SMI Count (R/O).\r | |
| 75 | ///\r | |
| 76 | UINT32 SMICount:32;\r | |
| 77 | UINT32 Reserved:32;\r | |
| 78 | } Bits;\r | |
| 79 | ///\r | |
| 80 | /// All bit fields as a 32-bit value\r | |
| 81 | ///\r | |
| 82 | UINT32 Uint32;\r | |
| 83 | ///\r | |
| 84 | /// All bit fields as a 64-bit value\r | |
| 85 | ///\r | |
| 86 | UINT64 Uint64;\r | |
| 87 | } MSR_XEON_PHI_SMI_COUNT_REGISTER;\r | |
| 88 | \r | |
| dfb20851 ED |
89 | /**\r |
| 90 | Package. Protected Processor Inventory Number Enable Control (R/W).\r | |
| 91 | \r | |
| 92 | @param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E)\r | |
| 93 | @param EAX Lower 32-bits of MSR value.\r | |
| 94 | Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.\r | |
| 95 | @param EDX Upper 32-bits of MSR value.\r | |
| 96 | Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.\r | |
| 97 | \r | |
| 98 | <b>Example usage</b>\r | |
| 99 | @code\r | |
| 100 | MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;\r | |
| 101 | \r | |
| 102 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);\r | |
| 103 | AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);\r | |
| 104 | @endcode\r | |
| 105 | **/\r | |
| 106 | #define MSR_XEON_PHI_PPIN_CTL 0x0000004E\r | |
| 3adf6316 MK |
107 | \r |
| 108 | /**\r | |
| dfb20851 ED |
109 | MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL\r |
| 110 | **/\r | |
| 111 | typedef union {\r | |
| 112 | ///\r | |
| 113 | /// Individual bit fields\r | |
| 114 | ///\r | |
| 115 | struct {\r | |
| 116 | ///\r | |
| 117 | /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to\r | |
| 118 | /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if\r | |
| 119 | /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an\r | |
| 120 | /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a\r | |
| 121 | /// privileged inventory initialization agent to access MSR_PPIN. After\r | |
| 122 | /// reading MSR_PPIN, the privileged inventory initialization agent should\r | |
| 123 | /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r | |
| 124 | /// prevent unauthorized modification to MSR_PPIN_CTL.\r | |
| 125 | ///\r | |
| 126 | UINT32 LockOut:1;\r | |
| 127 | ///\r | |
| 128 | /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r | |
| 129 | /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]\r | |
| 130 | /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.\r | |
| 131 | /// Default is 0.\r | |
| 132 | ///\r | |
| 133 | UINT32 Enable_PPIN:1;\r | |
| 134 | UINT32 Reserved1:30;\r | |
| 135 | UINT32 Reserved2:32;\r | |
| 136 | } Bits;\r | |
| 137 | ///\r | |
| 138 | /// All bit fields as a 32-bit value\r | |
| 139 | ///\r | |
| 140 | UINT32 Uint32;\r | |
| 141 | ///\r | |
| 142 | /// All bit fields as a 64-bit value\r | |
| 143 | ///\r | |
| 144 | UINT64 Uint64;\r | |
| 145 | } MSR_XEON_PHI_PPIN_CTL_REGISTER;\r | |
| 146 | \r | |
| 147 | \r | |
| 148 | /**\r | |
| 149 | Package. Protected Processor Inventory Number (R/O). Protected Processor\r | |
| 150 | Inventory Number (R/O) A unique value within a given CPUID\r | |
| 151 | family/model/stepping signature that a privileged inventory initialization\r | |
| 152 | agent can access to identify each physical processor, when access to\r | |
| 153 | MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if\r | |
| 154 | MSR_PPIN_CTL[bits 1:0] = '10b'.\r | |
| 155 | \r | |
| 156 | @param ECX MSR_XEON_PHI_PPIN (0x0000004F)\r | |
| 157 | @param EAX Lower 32-bits of MSR value.\r | |
| 158 | @param EDX Upper 32-bits of MSR value.\r | |
| 159 | \r | |
| 160 | <b>Example usage</b>\r | |
| 161 | @code\r | |
| 162 | UINT64 Msr;\r | |
| 163 | \r | |
| 164 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);\r | |
| 165 | @endcode\r | |
| 166 | **/\r | |
| 167 | #define MSR_XEON_PHI_PPIN 0x0000004F\r | |
| 168 | \r | |
| 169 | /**\r | |
| 170 | Package. Platform Information Contains power management and other model\r | |
| 171 | specific features enumeration. See http://biosbits.org.\r | |
| 3adf6316 MK |
172 | \r |
| 173 | @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)\r | |
| 174 | @param EAX Lower 32-bits of MSR value.\r | |
| 175 | Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r | |
| 176 | @param EDX Upper 32-bits of MSR value.\r | |
| 177 | Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r | |
| 178 | \r | |
| 179 | <b>Example usage</b>\r | |
| 180 | @code\r | |
| 181 | MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;\r | |
| 182 | \r | |
| 183 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);\r | |
| 184 | AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);\r | |
| 185 | @endcode\r | |
| ad8a2f5e | 186 | @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r |
| 3adf6316 MK |
187 | **/\r |
| 188 | #define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE\r | |
| 189 | \r | |
| 190 | /**\r | |
| 191 | MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO\r | |
| 192 | **/\r | |
| 193 | typedef union {\r | |
| 194 | ///\r | |
| 195 | /// Individual bit fields\r | |
| 196 | ///\r | |
| 197 | struct {\r | |
| 198 | UINT32 Reserved1:8;\r | |
| 199 | ///\r | |
| 200 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
| 201 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r | |
| 202 | /// MHz.\r | |
| 203 | ///\r | |
| 204 | UINT32 MaximumNonTurboRatio:8;\r | |
| 205 | UINT32 Reserved2:12;\r | |
| 206 | ///\r | |
| 207 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
| 208 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
| 209 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
| 210 | /// Turbo mode is disabled.\r | |
| 211 | ///\r | |
| 212 | UINT32 RatioLimit:1;\r | |
| 213 | ///\r | |
| 214 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r | |
| 215 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r | |
| 216 | /// and when set to 0, indicates TDP Limit for Turbo mode is not\r | |
| 217 | /// programmable.\r | |
| 218 | ///\r | |
| 219 | UINT32 TDPLimit:1;\r | |
| 220 | UINT32 Reserved3:2;\r | |
| 221 | UINT32 Reserved4:8;\r | |
| 222 | ///\r | |
| 223 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
| 224 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
| 225 | /// units of 100MHz.\r | |
| 226 | ///\r | |
| 227 | UINT32 MaximumEfficiencyRatio:8;\r | |
| 228 | UINT32 Reserved5:16;\r | |
| 229 | } Bits;\r | |
| 230 | ///\r | |
| 231 | /// All bit fields as a 64-bit value\r | |
| 232 | ///\r | |
| 233 | UINT64 Uint64;\r | |
| 234 | } MSR_XEON_PHI_PLATFORM_INFO_REGISTER;\r | |
| 235 | \r | |
| 236 | \r | |
| 237 | /**\r | |
| 238 | Module. C-State Configuration Control (R/W).\r | |
| 239 | \r | |
| 240 | @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
| 241 | @param EAX Lower 32-bits of MSR value.\r | |
| 242 | Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 243 | @param EDX Upper 32-bits of MSR value.\r | |
| 244 | Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 245 | \r | |
| 246 | <b>Example usage</b>\r | |
| 247 | @code\r | |
| 248 | MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
| 249 | \r | |
| 250 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);\r | |
| 251 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
| 252 | @endcode\r | |
| ad8a2f5e | 253 | @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
| 3adf6316 MK |
254 | **/\r |
| 255 | #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
| 256 | \r | |
| 257 | /**\r | |
| 258 | MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL\r | |
| 259 | **/\r | |
| 260 | typedef union {\r | |
| 261 | ///\r | |
| 262 | /// Individual bit fields\r | |
| 263 | ///\r | |
| 264 | struct {\r | |
| 265 | ///\r | |
| 266 | /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code\r | |
| 267 | /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No\r | |
| 268 | /// Retention 011b: C6 Retention 111b: No limit.\r | |
| 269 | ///\r | |
| 270 | UINT32 Limit:3;\r | |
| 271 | UINT32 Reserved1:7;\r | |
| 272 | ///\r | |
| 273 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r | |
| 274 | ///\r | |
| 275 | UINT32 IO_MWAIT:1;\r | |
| 276 | UINT32 Reserved2:4;\r | |
| 277 | ///\r | |
| 278 | /// [Bit 15] CFG Lock (R/WO).\r | |
| 279 | ///\r | |
| 280 | UINT32 CFGLock:1;\r | |
| 281 | UINT32 Reserved3:16;\r | |
| 282 | UINT32 Reserved4:32;\r | |
| 283 | } Bits;\r | |
| 284 | ///\r | |
| 285 | /// All bit fields as a 32-bit value\r | |
| 286 | ///\r | |
| 287 | UINT32 Uint32;\r | |
| 288 | ///\r | |
| 289 | /// All bit fields as a 64-bit value\r | |
| 290 | ///\r | |
| 291 | UINT64 Uint64;\r | |
| 292 | } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
| 293 | \r | |
| 294 | \r | |
| 295 | /**\r | |
| 296 | Module. Power Management IO Redirection in C-state (R/W).\r | |
| 297 | \r | |
| 298 | @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)\r | |
| 299 | @param EAX Lower 32-bits of MSR value.\r | |
| 300 | Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
| 301 | @param EDX Upper 32-bits of MSR value.\r | |
| 302 | Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
| 303 | \r | |
| 304 | <b>Example usage</b>\r | |
| 305 | @code\r | |
| 306 | MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r | |
| 307 | \r | |
| 308 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);\r | |
| 309 | AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r | |
| 310 | @endcode\r | |
| ad8a2f5e | 311 | @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r |
| 3adf6316 MK |
312 | **/\r |
| 313 | #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4\r | |
| 314 | \r | |
| 315 | /**\r | |
| 316 | MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE\r | |
| 317 | **/\r | |
| 318 | typedef union {\r | |
| 319 | ///\r | |
| 320 | /// Individual bit fields\r | |
| 321 | ///\r | |
| 322 | struct {\r | |
| 323 | ///\r | |
| 324 | /// [Bits 15:0] LVL_2 Base Address (R/W).\r | |
| 325 | ///\r | |
| 326 | UINT32 Lvl2Base:16;\r | |
| 327 | ///\r | |
| 328 | /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r | |
| 329 | /// maximum C-State code name to be included when IO read to MWAIT\r | |
| 330 | /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4\r | |
| 331 | /// is the max C-State to include 110b - C6 is the max C-State to include.\r | |
| 332 | ///\r | |
| 333 | UINT32 CStateRange:3;\r | |
| 334 | UINT32 Reserved1:13;\r | |
| 335 | UINT32 Reserved2:32;\r | |
| 336 | } Bits;\r | |
| 337 | ///\r | |
| 338 | /// All bit fields as a 32-bit value\r | |
| 339 | ///\r | |
| 340 | UINT32 Uint32;\r | |
| 341 | ///\r | |
| 342 | /// All bit fields as a 64-bit value\r | |
| 343 | ///\r | |
| 344 | UINT64 Uint64;\r | |
| 345 | } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;\r | |
| 346 | \r | |
| 347 | \r | |
| 348 | /**\r | |
| 349 | Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r | |
| 350 | handler to handle unsuccessful read of this MSR.\r | |
| 351 | \r | |
| 352 | @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)\r | |
| 353 | @param EAX Lower 32-bits of MSR value.\r | |
| 354 | Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r | |
| 355 | @param EDX Upper 32-bits of MSR value.\r | |
| 356 | Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r | |
| 357 | \r | |
| 358 | <b>Example usage</b>\r | |
| 359 | @code\r | |
| 360 | MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;\r | |
| 361 | \r | |
| 362 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);\r | |
| 363 | AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);\r | |
| 364 | @endcode\r | |
| ad8a2f5e | 365 | @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r |
| 3adf6316 MK |
366 | **/\r |
| 367 | #define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C\r | |
| 368 | \r | |
| 369 | /**\r | |
| 370 | MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG\r | |
| 371 | **/\r | |
| 372 | typedef union {\r | |
| 373 | ///\r | |
| 374 | /// Individual bit fields\r | |
| 375 | ///\r | |
| 376 | struct {\r | |
| 377 | ///\r | |
| 378 | /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r | |
| 379 | /// MSR, the configuration of AES instruction set availability is as\r | |
| 380 | /// follows: 11b: AES instructions are not available until next RESET.\r | |
| 381 | /// otherwise, AES instructions are available. Note, AES instruction set\r | |
| 382 | /// is not available if read is unsuccessful. If the configuration is not\r | |
| 383 | /// 01b, AES instruction can be mis-configured if a privileged agent\r | |
| 384 | /// unintentionally writes 11b.\r | |
| 385 | ///\r | |
| 386 | UINT32 AESConfiguration:2;\r | |
| 387 | UINT32 Reserved1:30;\r | |
| 388 | UINT32 Reserved2:32;\r | |
| 389 | } Bits;\r | |
| 390 | ///\r | |
| 391 | /// All bit fields as a 32-bit value\r | |
| 392 | ///\r | |
| 393 | UINT32 Uint32;\r | |
| 394 | ///\r | |
| 395 | /// All bit fields as a 64-bit value\r | |
| 396 | ///\r | |
| 397 | UINT64 Uint64;\r | |
| 398 | } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;\r | |
| 399 | \r | |
| 400 | \r | |
| dfb20851 ED |
401 | /**\r |
| 402 | Thread. MISC_FEATURE_ENABLES.\r | |
| 403 | \r | |
| 404 | @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)\r | |
| 405 | @param EAX Lower 32-bits of MSR value.\r | |
| 406 | Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.\r | |
| 407 | @param EDX Upper 32-bits of MSR value.\r | |
| 408 | Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.\r | |
| 409 | \r | |
| 410 | <b>Example usage</b>\r | |
| 411 | @code\r | |
| 412 | MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;\r | |
| 413 | \r | |
| 414 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);\r | |
| 415 | AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);\r | |
| 416 | @endcode\r | |
| 417 | **/\r | |
| 418 | #define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140\r | |
| 419 | \r | |
| 420 | /**\r | |
| 421 | MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES\r | |
| 422 | **/\r | |
| 423 | typedef union {\r | |
| 424 | ///\r | |
| 425 | /// Individual bit fields\r | |
| 426 | ///\r | |
| 427 | struct {\r | |
| 428 | UINT32 Reserved1:1;\r | |
| 429 | ///\r | |
| 430 | /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and\r | |
| 431 | /// MWAIT instructions do not cause invalid-opcode exceptions when\r | |
| 432 | /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed\r | |
| 433 | /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state\r | |
| 434 | /// other than C0 or C1, the instruction operates as if EAX indicated the\r | |
| 435 | /// C-state C1.\r | |
| 436 | ///\r | |
| 437 | UINT32 UserModeMonitorAndMwait:1;\r | |
| 438 | UINT32 Reserved2:30;\r | |
| 439 | UINT32 Reserved3:32;\r | |
| 440 | } Bits;\r | |
| 441 | ///\r | |
| 442 | /// All bit fields as a 32-bit value\r | |
| 443 | ///\r | |
| 444 | UINT32 Uint32;\r | |
| 445 | ///\r | |
| 446 | /// All bit fields as a 64-bit value\r | |
| 447 | ///\r | |
| 448 | UINT64 Uint64;\r | |
| 449 | } MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;\r | |
| 450 | \r | |
| 0f16be6d HW |
451 | /**\r |
| 452 | THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r | |
| 453 | Enhancement. Accessible only while in SMM.\r | |
| 454 | \r | |
| 455 | @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)\r | |
| 456 | @param EAX Lower 32-bits of MSR value.\r | |
| 457 | Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r | |
| 458 | @param EDX Upper 32-bits of MSR value.\r | |
| 459 | Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r | |
| 460 | \r | |
| 461 | <b>Example usage</b>\r | |
| 462 | @code\r | |
| 463 | MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;\r | |
| 464 | \r | |
| 465 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);\r | |
| 466 | AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);\r | |
| 467 | @endcode\r | |
| 468 | @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r | |
| 469 | **/\r | |
| 470 | #define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D\r | |
| 471 | \r | |
| 472 | /**\r | |
| 473 | MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP\r | |
| 474 | **/\r | |
| 475 | typedef union {\r | |
| 476 | ///\r | |
| 477 | /// Individual bit fields\r | |
| 478 | ///\r | |
| 479 | struct {\r | |
| 480 | UINT32 Reserved1:32;\r | |
| 481 | UINT32 Reserved2:26;\r | |
| 482 | ///\r | |
| 483 | /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r | |
| 484 | /// SMM code access restriction is supported and a host-space interface\r | |
| 485 | /// available to SMM handler.\r | |
| 486 | ///\r | |
| 487 | UINT32 SMM_Code_Access_Chk:1;\r | |
| 488 | ///\r | |
| 489 | /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r | |
| 490 | /// SMM long flow indicator is supported and a host-space interface\r | |
| 491 | /// available to SMM handler.\r | |
| 492 | ///\r | |
| 493 | UINT32 Long_Flow_Indication:1;\r | |
| 494 | UINT32 Reserved3:4;\r | |
| 495 | } Bits;\r | |
| 496 | ///\r | |
| 497 | /// All bit fields as a 64-bit value\r | |
| 498 | ///\r | |
| 499 | UINT64 Uint64;\r | |
| 500 | } MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;\r | |
| 501 | \r | |
| 502 | \r | |
| 3adf6316 MK |
503 | /**\r |
| 504 | Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
| 505 | functions to be enabled and disabled.\r | |
| 506 | \r | |
| 507 | @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)\r | |
| 508 | @param EAX Lower 32-bits of MSR value.\r | |
| 509 | Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r | |
| 510 | @param EDX Upper 32-bits of MSR value.\r | |
| 511 | Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r | |
| 512 | \r | |
| 513 | <b>Example usage</b>\r | |
| 514 | @code\r | |
| 515 | MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;\r | |
| 516 | \r | |
| 517 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);\r | |
| 518 | AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);\r | |
| 519 | @endcode\r | |
| ad8a2f5e | 520 | @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
| 3adf6316 MK |
521 | **/\r |
| 522 | #define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0\r | |
| 523 | \r | |
| 524 | /**\r | |
| 525 | MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE\r | |
| 526 | **/\r | |
| 527 | typedef union {\r | |
| 528 | ///\r | |
| 529 | /// Individual bit fields\r | |
| 530 | ///\r | |
| 531 | struct {\r | |
| 532 | ///\r | |
| 533 | /// [Bit 0] Fast-Strings Enable.\r | |
| 534 | ///\r | |
| 535 | UINT32 FastStrings:1;\r | |
| 536 | UINT32 Reserved1:2;\r | |
| 537 | ///\r | |
| 0f16be6d HW |
538 | /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value\r |
| 539 | /// is 1.\r | |
| 3adf6316 MK |
540 | ///\r |
| 541 | UINT32 AutomaticThermalControlCircuit:1;\r | |
| 542 | UINT32 Reserved2:3;\r | |
| 543 | ///\r | |
| 544 | /// [Bit 7] Performance Monitoring Available (R).\r | |
| 545 | ///\r | |
| 546 | UINT32 PerformanceMonitoring:1;\r | |
| 547 | UINT32 Reserved3:3;\r | |
| 548 | ///\r | |
| 549 | /// [Bit 11] Branch Trace Storage Unavailable (RO).\r | |
| 550 | ///\r | |
| 551 | UINT32 BTS:1;\r | |
| 552 | ///\r | |
| 0f16be6d | 553 | /// [Bit 12] Processor Event Based Sampling Unavailable (RO).\r |
| 3adf6316 MK |
554 | ///\r |
| 555 | UINT32 PEBS:1;\r | |
| 556 | UINT32 Reserved4:3;\r | |
| 557 | ///\r | |
| 558 | /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).\r | |
| 559 | ///\r | |
| 560 | UINT32 EIST:1;\r | |
| 561 | UINT32 Reserved5:1;\r | |
| 562 | ///\r | |
| 563 | /// [Bit 18] ENABLE MONITOR FSM (R/W).\r | |
| 564 | ///\r | |
| 565 | UINT32 MONITOR:1;\r | |
| 566 | UINT32 Reserved6:3;\r | |
| 567 | ///\r | |
| 568 | /// [Bit 22] Limit CPUID Maxval (R/W).\r | |
| 569 | ///\r | |
| 570 | UINT32 LimitCpuidMaxval:1;\r | |
| 571 | ///\r | |
| 572 | /// [Bit 23] xTPR Message Disable (R/W).\r | |
| 573 | ///\r | |
| 574 | UINT32 xTPR_Message_Disable:1;\r | |
| 575 | UINT32 Reserved7:8;\r | |
| 576 | UINT32 Reserved8:2;\r | |
| 577 | ///\r | |
| 578 | /// [Bit 34] XD Bit Disable (R/W).\r | |
| 579 | ///\r | |
| 580 | UINT32 XD:1;\r | |
| 581 | UINT32 Reserved9:3;\r | |
| 582 | ///\r | |
| 583 | /// [Bit 38] Turbo Mode Disable (R/W).\r | |
| 584 | ///\r | |
| 585 | UINT32 TurboModeDisable:1;\r | |
| 586 | UINT32 Reserved10:25;\r | |
| 587 | } Bits;\r | |
| 588 | ///\r | |
| 589 | /// All bit fields as a 64-bit value\r | |
| 590 | ///\r | |
| 591 | UINT64 Uint64;\r | |
| 592 | } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;\r | |
| 593 | \r | |
| 594 | \r | |
| 595 | /**\r | |
| 596 | Package.\r | |
| 597 | \r | |
| 598 | @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)\r | |
| 599 | @param EAX Lower 32-bits of MSR value.\r | |
| 600 | Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r | |
| 601 | @param EDX Upper 32-bits of MSR value.\r | |
| 602 | Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r | |
| 603 | \r | |
| 604 | <b>Example usage</b>\r | |
| 605 | @code\r | |
| 606 | MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;\r | |
| 607 | \r | |
| 608 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);\r | |
| 609 | AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);\r | |
| 610 | @endcode\r | |
| ad8a2f5e | 611 | @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r |
| 3adf6316 MK |
612 | **/\r |
| 613 | #define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2\r | |
| 614 | \r | |
| 615 | /**\r | |
| 616 | MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET\r | |
| 617 | **/\r | |
| 618 | typedef union {\r | |
| 619 | ///\r | |
| 620 | /// Individual bit fields\r | |
| 621 | ///\r | |
| 622 | struct {\r | |
| 623 | UINT32 Reserved1:16;\r | |
| 624 | ///\r | |
| 625 | /// [Bits 23:16] Temperature Target (R).\r | |
| 626 | ///\r | |
| 627 | UINT32 TemperatureTarget:8;\r | |
| 628 | ///\r | |
| 629 | /// [Bits 29:24] Target Offset (R/W).\r | |
| 630 | ///\r | |
| 631 | UINT32 TargetOffset:6;\r | |
| 632 | UINT32 Reserved2:2;\r | |
| 633 | UINT32 Reserved3:32;\r | |
| 634 | } Bits;\r | |
| 635 | ///\r | |
| 636 | /// All bit fields as a 32-bit value\r | |
| 637 | ///\r | |
| 638 | UINT32 Uint32;\r | |
| 639 | ///\r | |
| 640 | /// All bit fields as a 64-bit value\r | |
| 641 | ///\r | |
| 642 | UINT64 Uint64;\r | |
| 643 | } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;\r | |
| 644 | \r | |
| 645 | \r | |
| 0f16be6d HW |
646 | /**\r |
| 647 | Miscellaneous Feature Control (R/W).\r | |
| 648 | \r | |
| 649 | @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)\r | |
| 650 | @param EAX Lower 32-bits of MSR value.\r | |
| 651 | Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r | |
| 652 | @param EDX Upper 32-bits of MSR value.\r | |
| 653 | Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r | |
| 654 | \r | |
| 655 | <b>Example usage</b>\r | |
| 656 | @code\r | |
| 657 | MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;\r | |
| 658 | \r | |
| 659 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);\r | |
| 660 | AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);\r | |
| 661 | @endcode\r | |
| 662 | @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r | |
| 663 | **/\r | |
| 664 | #define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4\r | |
| 665 | \r | |
| 666 | /**\r | |
| 667 | MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL\r | |
| 668 | **/\r | |
| 669 | typedef union {\r | |
| 670 | ///\r | |
| 671 | /// Individual bit fields\r | |
| 672 | ///\r | |
| 673 | struct {\r | |
| 674 | ///\r | |
| 675 | /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the\r | |
| 676 | /// L1 data cache prefetcher.\r | |
| 677 | ///\r | |
| 678 | UINT32 DCUHardwarePrefetcherDisable:1;\r | |
| 679 | ///\r | |
| 680 | /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r | |
| 681 | /// L2 hardware prefetcher.\r | |
| 682 | ///\r | |
| 683 | UINT32 L2HardwarePrefetcherDisable:1;\r | |
| 684 | UINT32 Reserved1:30;\r | |
| 685 | UINT32 Reserved2:32;\r | |
| 686 | } Bits;\r | |
| 687 | ///\r | |
| 688 | /// All bit fields as a 32-bit value\r | |
| 689 | ///\r | |
| 690 | UINT32 Uint32;\r | |
| 691 | ///\r | |
| 692 | /// All bit fields as a 64-bit value\r | |
| 693 | ///\r | |
| 694 | UINT64 Uint64;\r | |
| 695 | } MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;\r | |
| 696 | \r | |
| 697 | \r | |
| 3adf6316 MK |
698 | /**\r |
| 699 | Shared. Offcore Response Event Select Register (R/W).\r | |
| 700 | \r | |
| 701 | @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)\r | |
| 702 | @param EAX Lower 32-bits of MSR value.\r | |
| 703 | @param EDX Upper 32-bits of MSR value.\r | |
| 704 | \r | |
| 705 | <b>Example usage</b>\r | |
| 706 | @code\r | |
| 707 | UINT64 Msr;\r | |
| 708 | \r | |
| 709 | Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);\r | |
| 710 | AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);\r | |
| 711 | @endcode\r | |
| ad8a2f5e | 712 | @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r |
| 3adf6316 MK |
713 | **/\r |
| 714 | #define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6\r | |
| 715 | \r | |
| 716 | \r | |
| 717 | /**\r | |
| 718 | Shared. Offcore Response Event Select Register (R/W).\r | |
| 719 | \r | |
| 720 | @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)\r | |
| 721 | @param EAX Lower 32-bits of MSR value.\r | |
| 722 | @param EDX Upper 32-bits of MSR value.\r | |
| 723 | \r | |
| 724 | <b>Example usage</b>\r | |
| 725 | @code\r | |
| 726 | UINT64 Msr;\r | |
| 727 | \r | |
| 728 | Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);\r | |
| 729 | AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);\r | |
| 730 | @endcode\r | |
| ad8a2f5e | 731 | @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r |
| 3adf6316 MK |
732 | **/\r |
| 733 | #define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7\r | |
| 734 | \r | |
| 735 | \r | |
| 736 | /**\r | |
| 737 | Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).\r | |
| 738 | \r | |
| 739 | @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)\r | |
| 740 | @param EAX Lower 32-bits of MSR value.\r | |
| 741 | Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 742 | @param EDX Upper 32-bits of MSR value.\r | |
| 743 | Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 744 | \r | |
| 745 | <b>Example usage</b>\r | |
| 746 | @code\r | |
| 747 | MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
| 748 | \r | |
| 749 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);\r | |
| 750 | AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);\r | |
| 751 | @endcode\r | |
| ad8a2f5e | 752 | @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
| 3adf6316 MK |
753 | **/\r |
| 754 | #define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD\r | |
| 755 | \r | |
| 756 | /**\r | |
| 757 | MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT\r | |
| 758 | **/\r | |
| 759 | typedef union {\r | |
| 760 | ///\r | |
| 761 | /// Individual bit fields\r | |
| 762 | ///\r | |
| 763 | struct {\r | |
| 764 | UINT32 Reserved:1;\r | |
| 765 | ///\r | |
| 766 | /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active\r | |
| 767 | /// processor cores which operates under the maximum ratio limit for group\r | |
| 768 | /// 0.\r | |
| 769 | ///\r | |
| 770 | UINT32 MaxCoresGroup0:7;\r | |
| 771 | ///\r | |
| 772 | /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo\r | |
| 773 | /// ratio limit when the number of active cores are not more than the\r | |
| 774 | /// group 0 maximum core count.\r | |
| 775 | ///\r | |
| 776 | UINT32 MaxRatioLimitGroup0:8;\r | |
| 777 | ///\r | |
| 778 | /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1\r | |
| 779 | /// Group 1, which includes the specified number of additional cores plus\r | |
| 780 | /// the cores in group 0, operates under the group 1 turbo max ratio limit\r | |
| 781 | /// = "group 0 Max ratio limit" - "group ratio delta for group 1".\r | |
| 782 | ///\r | |
| 783 | UINT32 MaxIncrementalCoresGroup1:5;\r | |
| 784 | ///\r | |
| 785 | /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned\r | |
| 786 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
| 787 | /// to Group 0.\r | |
| 788 | ///\r | |
| 789 | UINT32 DeltaRatioGroup1:3;\r | |
| 790 | ///\r | |
| 791 | /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2\r | |
| 792 | /// Group 2, which includes the specified number of additional cores plus\r | |
| 793 | /// all the cores in group 1, operates under the group 2 turbo max ratio\r | |
| 794 | /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".\r | |
| 795 | ///\r | |
| 796 | UINT32 MaxIncrementalCoresGroup2:5;\r | |
| 797 | ///\r | |
| 798 | /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned\r | |
| 799 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
| 800 | /// for Group 1.\r | |
| 801 | ///\r | |
| 802 | UINT32 DeltaRatioGroup2:3;\r | |
| 803 | ///\r | |
| 804 | /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3\r | |
| 805 | /// Group 3, which includes the specified number of additional cores plus\r | |
| 806 | /// all the cores in group 2, operates under the group 3 turbo max ratio\r | |
| 807 | /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".\r | |
| 808 | ///\r | |
| 809 | UINT32 MaxIncrementalCoresGroup3:5;\r | |
| 810 | ///\r | |
| 811 | /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned\r | |
| 812 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
| 813 | /// for Group 2.\r | |
| 814 | ///\r | |
| 815 | UINT32 DeltaRatioGroup3:3;\r | |
| 816 | ///\r | |
| 817 | /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4\r | |
| 818 | /// Group 4, which includes the specified number of additional cores plus\r | |
| 819 | /// all the cores in group 3, operates under the group 4 turbo max ratio\r | |
| 820 | /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".\r | |
| 821 | ///\r | |
| 822 | UINT32 MaxIncrementalCoresGroup4:5;\r | |
| 823 | ///\r | |
| 824 | /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned\r | |
| 825 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
| 826 | /// for Group 3.\r | |
| 827 | ///\r | |
| 828 | UINT32 DeltaRatioGroup4:3;\r | |
| 829 | ///\r | |
| 830 | /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5\r | |
| 831 | /// Group 5, which includes the specified number of additional cores plus\r | |
| 832 | /// all the cores in group 4, operates under the group 5 turbo max ratio\r | |
| 833 | /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".\r | |
| 834 | ///\r | |
| 835 | UINT32 MaxIncrementalCoresGroup5:5;\r | |
| 836 | ///\r | |
| 837 | /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned\r | |
| 838 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
| 839 | /// for Group 4.\r | |
| 840 | ///\r | |
| 841 | UINT32 DeltaRatioGroup5:3;\r | |
| 842 | ///\r | |
| 843 | /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6\r | |
| 844 | /// Group 6, which includes the specified number of additional cores plus\r | |
| 845 | /// all the cores in group 5, operates under the group 6 turbo max ratio\r | |
| 846 | /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".\r | |
| 847 | ///\r | |
| 848 | UINT32 MaxIncrementalCoresGroup6:5;\r | |
| 849 | ///\r | |
| 850 | /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned\r | |
| 851 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
| 852 | /// for Group 5.\r | |
| 853 | ///\r | |
| 854 | UINT32 DeltaRatioGroup6:3;\r | |
| 855 | } Bits;\r | |
| 856 | ///\r | |
| 857 | /// All bit fields as a 64-bit value\r | |
| 858 | ///\r | |
| 859 | UINT64 Uint64;\r | |
| 860 | } MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;\r | |
| 861 | \r | |
| 862 | \r | |
| 863 | /**\r | |
| 864 | Thread. Last Branch Record Filtering Select Register (R/W).\r | |
| 865 | \r | |
| 866 | @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)\r | |
| 867 | @param EAX Lower 32-bits of MSR value.\r | |
| 868 | @param EDX Upper 32-bits of MSR value.\r | |
| 869 | \r | |
| 870 | <b>Example usage</b>\r | |
| 871 | @code\r | |
| 872 | UINT64 Msr;\r | |
| 873 | \r | |
| 874 | Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);\r | |
| 875 | AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);\r | |
| 876 | @endcode\r | |
| ad8a2f5e | 877 | @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r |
| 3adf6316 MK |
878 | **/\r |
| 879 | #define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r | |
| 880 | \r | |
| 881 | \r | |
| dfb20851 ED |
882 | /**\r |
| 883 | MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT\r | |
| 884 | **/\r | |
| 885 | typedef union {\r | |
| 886 | ///\r | |
| 887 | /// Individual bit fields\r | |
| 888 | ///\r | |
| 889 | struct {\r | |
| 890 | ///\r | |
| 891 | /// [Bit 0] CPL_EQ_0.\r | |
| 892 | ///\r | |
| 893 | UINT32 CPL_EQ_0:1;\r | |
| 894 | ///\r | |
| 895 | /// [Bit 1] CPL_NEQ_0.\r | |
| 896 | ///\r | |
| 897 | UINT32 CPL_NEQ_0:1;\r | |
| 898 | ///\r | |
| 899 | /// [Bit 2] JCC.\r | |
| 900 | ///\r | |
| 901 | UINT32 JCC:1;\r | |
| 902 | ///\r | |
| 903 | /// [Bit 3] NEAR_REL_CALL.\r | |
| 904 | ///\r | |
| 905 | UINT32 NEAR_REL_CALL:1;\r | |
| 906 | ///\r | |
| 907 | /// [Bit 4] NEAR_IND_CALL.\r | |
| 908 | ///\r | |
| 909 | UINT32 NEAR_IND_CALL:1;\r | |
| 910 | ///\r | |
| 911 | /// [Bit 5] NEAR_RET.\r | |
| 912 | ///\r | |
| 913 | UINT32 NEAR_RET:1;\r | |
| 914 | ///\r | |
| 915 | /// [Bit 6] NEAR_IND_JMP.\r | |
| 916 | ///\r | |
| 917 | UINT32 NEAR_IND_JMP:1;\r | |
| 918 | ///\r | |
| 919 | /// [Bit 7] NEAR_REL_JMP.\r | |
| 920 | ///\r | |
| 921 | UINT32 NEAR_REL_JMP:1;\r | |
| 922 | ///\r | |
| 923 | /// [Bit 8] FAR_BRANCH.\r | |
| 924 | ///\r | |
| 925 | UINT32 FAR_BRANCH:1;\r | |
| 926 | UINT32 Reserved1:23;\r | |
| 927 | UINT32 Reserved2:32;\r | |
| 928 | } Bits;\r | |
| 929 | ///\r | |
| 930 | /// All bit fields as a 32-bit value\r | |
| 931 | ///\r | |
| 932 | UINT32 Uint32;\r | |
| 933 | ///\r | |
| 934 | /// All bit fields as a 64-bit value\r | |
| 935 | ///\r | |
| 936 | UINT64 Uint64;\r | |
| 937 | } MSR_XEON_PHI_LBR_SELECT_REGISTER;\r | |
| 938 | \r | |
| 3adf6316 MK |
939 | /**\r |
| 940 | Thread. Last Branch Record Stack TOS (R/W).\r | |
| 941 | \r | |
| 942 | @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)\r | |
| 943 | @param EAX Lower 32-bits of MSR value.\r | |
| 944 | @param EDX Upper 32-bits of MSR value.\r | |
| 945 | \r | |
| 946 | <b>Example usage</b>\r | |
| 947 | @code\r | |
| 948 | UINT64 Msr;\r | |
| 949 | \r | |
| 950 | Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);\r | |
| 951 | AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);\r | |
| 952 | @endcode\r | |
| ad8a2f5e | 953 | @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r |
| 3adf6316 MK |
954 | **/\r |
| 955 | #define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9\r | |
| 956 | \r | |
| 957 | \r | |
| 958 | /**\r | |
| 959 | Thread. Last Exception Record From Linear IP (R).\r | |
| 960 | \r | |
| 961 | @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)\r | |
| 962 | @param EAX Lower 32-bits of MSR value.\r | |
| 963 | @param EDX Upper 32-bits of MSR value.\r | |
| 964 | \r | |
| 965 | <b>Example usage</b>\r | |
| 966 | @code\r | |
| 967 | UINT64 Msr;\r | |
| 968 | \r | |
| 969 | Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);\r | |
| 970 | @endcode\r | |
| ad8a2f5e | 971 | @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r |
| 3adf6316 MK |
972 | **/\r |
| 973 | #define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD\r | |
| 974 | \r | |
| 975 | \r | |
| 976 | /**\r | |
| 977 | Thread. Last Exception Record To Linear IP (R).\r | |
| 978 | \r | |
| 979 | @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)\r | |
| 980 | @param EAX Lower 32-bits of MSR value.\r | |
| 981 | @param EDX Upper 32-bits of MSR value.\r | |
| 982 | \r | |
| 983 | <b>Example usage</b>\r | |
| 984 | @code\r | |
| 985 | UINT64 Msr;\r | |
| 986 | \r | |
| 987 | Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);\r | |
| 988 | @endcode\r | |
| ad8a2f5e | 989 | @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r |
| 3adf6316 MK |
990 | **/\r |
| 991 | #define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r | |
| 992 | \r | |
| 993 | \r | |
| 3adf6316 | 994 | /**\r |
| ba1a2d11 | 995 | Thread. See Table 2-2.\r |
| 3adf6316 MK |
996 | \r |
| 997 | @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)\r | |
| 998 | @param EAX Lower 32-bits of MSR value.\r | |
| 999 | @param EDX Upper 32-bits of MSR value.\r | |
| 1000 | \r | |
| 1001 | <b>Example usage</b>\r | |
| 1002 | @code\r | |
| 1003 | UINT64 Msr;\r | |
| 1004 | \r | |
| 1005 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);\r | |
| 1006 | AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);\r | |
| 1007 | @endcode\r | |
| ad8a2f5e | 1008 | @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r |
| 3adf6316 MK |
1009 | **/\r |
| 1010 | #define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1\r | |
| 1011 | \r | |
| 1012 | \r | |
| 1013 | /**\r | |
| 1014 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 1015 | unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3\r | |
| 1016 | Residency Counter. (R/O).\r | |
| 1017 | \r | |
| 1018 | @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)\r | |
| 1019 | @param EAX Lower 32-bits of MSR value.\r | |
| 1020 | @param EDX Upper 32-bits of MSR value.\r | |
| 1021 | \r | |
| 1022 | <b>Example usage</b>\r | |
| 1023 | @code\r | |
| 1024 | UINT64 Msr;\r | |
| 1025 | \r | |
| 1026 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);\r | |
| 1027 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);\r | |
| 1028 | @endcode\r | |
| ad8a2f5e | 1029 | @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r |
| 3adf6316 MK |
1030 | **/\r |
| 1031 | #define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8\r | |
| 1032 | \r | |
| 1033 | \r | |
| 1034 | /**\r | |
| 1035 | Package. Package C6 Residency Counter. (R/O).\r | |
| 1036 | \r | |
| 1037 | @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)\r | |
| 1038 | @param EAX Lower 32-bits of MSR value.\r | |
| 1039 | @param EDX Upper 32-bits of MSR value.\r | |
| 1040 | \r | |
| 1041 | <b>Example usage</b>\r | |
| 1042 | @code\r | |
| 1043 | UINT64 Msr;\r | |
| 1044 | \r | |
| 1045 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);\r | |
| 1046 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);\r | |
| 1047 | @endcode\r | |
| ad8a2f5e | 1048 | @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r |
| 3adf6316 MK |
1049 | **/\r |
| 1050 | #define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9\r | |
| 1051 | \r | |
| 1052 | \r | |
| 1053 | /**\r | |
| 1054 | Package. Package C7 Residency Counter. (R/O).\r | |
| 1055 | \r | |
| 1056 | @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)\r | |
| 1057 | @param EAX Lower 32-bits of MSR value.\r | |
| 1058 | @param EDX Upper 32-bits of MSR value.\r | |
| 1059 | \r | |
| 1060 | <b>Example usage</b>\r | |
| 1061 | @code\r | |
| 1062 | UINT64 Msr;\r | |
| 1063 | \r | |
| 1064 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);\r | |
| 1065 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);\r | |
| 1066 | @endcode\r | |
| ad8a2f5e | 1067 | @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r |
| 3adf6316 MK |
1068 | **/\r |
| 1069 | #define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA\r | |
| 1070 | \r | |
| 1071 | \r | |
| 1072 | /**\r | |
| 1073 | Module. Note: C-state values are processor specific C-state code names,\r | |
| 1074 | unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0\r | |
| 1075 | Residency Counter. (R/O).\r | |
| 1076 | \r | |
| 1077 | @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)\r | |
| 1078 | @param EAX Lower 32-bits of MSR value.\r | |
| 1079 | @param EDX Upper 32-bits of MSR value.\r | |
| 1080 | \r | |
| 1081 | <b>Example usage</b>\r | |
| 1082 | @code\r | |
| 1083 | UINT64 Msr;\r | |
| 1084 | \r | |
| 1085 | Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);\r | |
| 1086 | AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);\r | |
| 1087 | @endcode\r | |
| ad8a2f5e | 1088 | @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.\r |
| 3adf6316 MK |
1089 | **/\r |
| 1090 | #define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC\r | |
| 1091 | \r | |
| 1092 | \r | |
| 1093 | /**\r | |
| 1094 | Module. Module C6 Residency Counter. (R/O).\r | |
| 1095 | \r | |
| 1096 | @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)\r | |
| 1097 | @param EAX Lower 32-bits of MSR value.\r | |
| 1098 | @param EDX Upper 32-bits of MSR value.\r | |
| 1099 | \r | |
| 1100 | <b>Example usage</b>\r | |
| 1101 | @code\r | |
| 1102 | UINT64 Msr;\r | |
| 1103 | \r | |
| 1104 | Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);\r | |
| 1105 | AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);\r | |
| 1106 | @endcode\r | |
| ad8a2f5e | 1107 | @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.\r |
| 3adf6316 MK |
1108 | **/\r |
| 1109 | #define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD\r | |
| 1110 | \r | |
| 1111 | \r | |
| 1112 | /**\r | |
| 1113 | Core. Note: C-state values are processor specific C-state code names,\r | |
| 1114 | unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6\r | |
| 1115 | Residency Counter. (R/O).\r | |
| 1116 | \r | |
| 1117 | @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)\r | |
| 1118 | @param EAX Lower 32-bits of MSR value.\r | |
| 1119 | @param EDX Upper 32-bits of MSR value.\r | |
| 1120 | \r | |
| 1121 | <b>Example usage</b>\r | |
| 1122 | @code\r | |
| 1123 | UINT64 Msr;\r | |
| 1124 | \r | |
| 1125 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);\r | |
| 1126 | AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);\r | |
| 1127 | @endcode\r | |
| ad8a2f5e | 1128 | @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r |
| 3adf6316 MK |
1129 | **/\r |
| 1130 | #define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r | |
| 1131 | \r | |
| 1132 | \r | |
| 3adf6316 | 1133 | /**\r |
| ba1a2d11 | 1134 | Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r |
| 3adf6316 MK |
1135 | \r |
| 1136 | @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r | |
| 1137 | @param EAX Lower 32-bits of MSR value.\r | |
| 1138 | @param EDX Upper 32-bits of MSR value.\r | |
| 1139 | \r | |
| 1140 | <b>Example usage</b>\r | |
| 1141 | @code\r | |
| 1142 | UINT64 Msr;\r | |
| 1143 | \r | |
| 1144 | Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);\r | |
| 1145 | @endcode\r | |
| ad8a2f5e | 1146 | @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r |
| 3adf6316 MK |
1147 | **/\r |
| 1148 | #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r | |
| 1149 | \r | |
| 1150 | \r | |
| 1151 | /**\r | |
| ba1a2d11 ED |
1152 | Core. Capability Reporting Register of VM-Function Controls (R/O) See Table\r |
| 1153 | 2-2.\r | |
| 3adf6316 MK |
1154 | \r |
| 1155 | @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)\r | |
| 1156 | @param EAX Lower 32-bits of MSR value.\r | |
| 1157 | @param EDX Upper 32-bits of MSR value.\r | |
| 1158 | \r | |
| 1159 | <b>Example usage</b>\r | |
| 1160 | @code\r | |
| 1161 | UINT64 Msr;\r | |
| 1162 | \r | |
| 1163 | Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);\r | |
| 1164 | @endcode\r | |
| ad8a2f5e | 1165 | @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r |
| 3adf6316 MK |
1166 | **/\r |
| 1167 | #define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491\r | |
| 1168 | \r | |
| 1169 | \r | |
| 1170 | /**\r | |
| 1171 | Package. Unit Multipliers used in RAPL Interfaces (R/O).\r | |
| 1172 | \r | |
| 1173 | @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)\r | |
| 1174 | @param EAX Lower 32-bits of MSR value.\r | |
| 1175 | Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r | |
| 1176 | @param EDX Upper 32-bits of MSR value.\r | |
| 1177 | Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r | |
| 1178 | \r | |
| 1179 | <b>Example usage</b>\r | |
| 1180 | @code\r | |
| 1181 | MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;\r | |
| 1182 | \r | |
| 1183 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);\r | |
| 1184 | @endcode\r | |
| ad8a2f5e | 1185 | @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r |
| 3adf6316 MK |
1186 | **/\r |
| 1187 | #define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606\r | |
| 1188 | \r | |
| 1189 | /**\r | |
| 1190 | MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT\r | |
| 1191 | **/\r | |
| 1192 | typedef union {\r | |
| 1193 | ///\r | |
| 1194 | /// Individual bit fields\r | |
| 1195 | ///\r | |
| 1196 | struct {\r | |
| 1197 | ///\r | |
| 1198 | /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r | |
| 1199 | ///\r | |
| 1200 | UINT32 PowerUnits:4;\r | |
| 1201 | UINT32 Reserved1:4;\r | |
| 1202 | ///\r | |
| 1203 | /// [Bits 12:8] Package. Energy Status Units Energy related information\r | |
| 1204 | /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r | |
| 1205 | /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r | |
| 1206 | /// micro-joules).\r | |
| 1207 | ///\r | |
| 1208 | UINT32 EnergyStatusUnits:5;\r | |
| 1209 | UINT32 Reserved2:3;\r | |
| 1210 | ///\r | |
| 1211 | /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r | |
| 1212 | /// Interfaces.".\r | |
| 1213 | ///\r | |
| 1214 | UINT32 TimeUnits:4;\r | |
| 1215 | UINT32 Reserved3:12;\r | |
| 1216 | UINT32 Reserved4:32;\r | |
| 1217 | } Bits;\r | |
| 1218 | ///\r | |
| 1219 | /// All bit fields as a 32-bit value\r | |
| 1220 | ///\r | |
| 1221 | UINT32 Uint32;\r | |
| 1222 | ///\r | |
| 1223 | /// All bit fields as a 64-bit value\r | |
| 1224 | ///\r | |
| 1225 | UINT64 Uint64;\r | |
| 1226 | } MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;\r | |
| 1227 | \r | |
| 1228 | \r | |
| 1229 | /**\r | |
| 1230 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 1231 | unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2\r | |
| 1232 | Residency Counter. (R/O).\r | |
| 1233 | \r | |
| 1234 | @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)\r | |
| 1235 | @param EAX Lower 32-bits of MSR value.\r | |
| 1236 | @param EDX Upper 32-bits of MSR value.\r | |
| 1237 | \r | |
| 1238 | <b>Example usage</b>\r | |
| 1239 | @code\r | |
| 1240 | UINT64 Msr;\r | |
| 1241 | \r | |
| 1242 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);\r | |
| 1243 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);\r | |
| 1244 | @endcode\r | |
| ad8a2f5e | 1245 | @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r |
| 3adf6316 MK |
1246 | **/\r |
| 1247 | #define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D\r | |
| 1248 | \r | |
| 1249 | \r | |
| 1250 | /**\r | |
| 1251 | Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r | |
| 1252 | RAPL Domain.".\r | |
| 1253 | \r | |
| 1254 | @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)\r | |
| 1255 | @param EAX Lower 32-bits of MSR value.\r | |
| 1256 | @param EDX Upper 32-bits of MSR value.\r | |
| 1257 | \r | |
| 1258 | <b>Example usage</b>\r | |
| 1259 | @code\r | |
| 1260 | UINT64 Msr;\r | |
| 1261 | \r | |
| 1262 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);\r | |
| 1263 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);\r | |
| 1264 | @endcode\r | |
| ad8a2f5e | 1265 | @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r |
| 3adf6316 MK |
1266 | **/\r |
| 1267 | #define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610\r | |
| 1268 | \r | |
| 1269 | \r | |
| 1270 | /**\r | |
| 1271 | Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
| 1272 | \r | |
| 1273 | @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)\r | |
| 1274 | @param EAX Lower 32-bits of MSR value.\r | |
| 1275 | @param EDX Upper 32-bits of MSR value.\r | |
| 1276 | \r | |
| 1277 | <b>Example usage</b>\r | |
| 1278 | @code\r | |
| 1279 | UINT64 Msr;\r | |
| 1280 | \r | |
| 1281 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);\r | |
| 1282 | @endcode\r | |
| ad8a2f5e | 1283 | @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r |
| 3adf6316 MK |
1284 | **/\r |
| 1285 | #define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611\r | |
| 1286 | \r | |
| 1287 | \r | |
| 1288 | /**\r | |
| 1289 | Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
| 1290 | \r | |
| 1291 | @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)\r | |
| 1292 | @param EAX Lower 32-bits of MSR value.\r | |
| 1293 | @param EDX Upper 32-bits of MSR value.\r | |
| 1294 | \r | |
| 1295 | <b>Example usage</b>\r | |
| 1296 | @code\r | |
| 1297 | UINT64 Msr;\r | |
| 1298 | \r | |
| 1299 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);\r | |
| 1300 | @endcode\r | |
| ad8a2f5e | 1301 | @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r |
| 3adf6316 MK |
1302 | **/\r |
| 1303 | #define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613\r | |
| 1304 | \r | |
| 1305 | \r | |
| 1306 | /**\r | |
| 1307 | Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r | |
| 1308 | Domain.".\r | |
| 1309 | \r | |
| 1310 | @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)\r | |
| 1311 | @param EAX Lower 32-bits of MSR value.\r | |
| 1312 | @param EDX Upper 32-bits of MSR value.\r | |
| 1313 | \r | |
| 1314 | <b>Example usage</b>\r | |
| 1315 | @code\r | |
| 1316 | UINT64 Msr;\r | |
| 1317 | \r | |
| 1318 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);\r | |
| 1319 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);\r | |
| 1320 | @endcode\r | |
| ad8a2f5e | 1321 | @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r |
| 3adf6316 MK |
1322 | **/\r |
| 1323 | #define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614\r | |
| 1324 | \r | |
| 1325 | \r | |
| 1326 | /**\r | |
| 1327 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r | |
| 1328 | Domain.".\r | |
| 1329 | \r | |
| 1330 | @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)\r | |
| 1331 | @param EAX Lower 32-bits of MSR value.\r | |
| 1332 | @param EDX Upper 32-bits of MSR value.\r | |
| 1333 | \r | |
| 1334 | <b>Example usage</b>\r | |
| 1335 | @code\r | |
| 1336 | UINT64 Msr;\r | |
| 1337 | \r | |
| 1338 | Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);\r | |
| 1339 | AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);\r | |
| 1340 | @endcode\r | |
| ad8a2f5e | 1341 | @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r |
| 3adf6316 MK |
1342 | **/\r |
| 1343 | #define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618\r | |
| 1344 | \r | |
| 1345 | \r | |
| 1346 | /**\r | |
| 1347 | Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 1348 | \r | |
| 1349 | @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)\r | |
| 1350 | @param EAX Lower 32-bits of MSR value.\r | |
| 1351 | @param EDX Upper 32-bits of MSR value.\r | |
| 1352 | \r | |
| 1353 | <b>Example usage</b>\r | |
| 1354 | @code\r | |
| 1355 | UINT64 Msr;\r | |
| 1356 | \r | |
| 1357 | Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);\r | |
| 1358 | @endcode\r | |
| ad8a2f5e | 1359 | @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r |
| 3adf6316 MK |
1360 | **/\r |
| 1361 | #define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619\r | |
| 1362 | \r | |
| 1363 | \r | |
| 1364 | /**\r | |
| 1365 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
| 1366 | RAPL Domain.".\r | |
| 1367 | \r | |
| 1368 | @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)\r | |
| 1369 | @param EAX Lower 32-bits of MSR value.\r | |
| 1370 | @param EDX Upper 32-bits of MSR value.\r | |
| 1371 | \r | |
| 1372 | <b>Example usage</b>\r | |
| 1373 | @code\r | |
| 1374 | UINT64 Msr;\r | |
| 1375 | \r | |
| 1376 | Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);\r | |
| 1377 | @endcode\r | |
| ad8a2f5e | 1378 | @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r |
| 3adf6316 MK |
1379 | **/\r |
| 1380 | #define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B\r | |
| 1381 | \r | |
| 1382 | \r | |
| 1383 | /**\r | |
| 1384 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 1385 | \r | |
| 1386 | @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)\r | |
| 1387 | @param EAX Lower 32-bits of MSR value.\r | |
| 1388 | @param EDX Upper 32-bits of MSR value.\r | |
| 1389 | \r | |
| 1390 | <b>Example usage</b>\r | |
| 1391 | @code\r | |
| 1392 | UINT64 Msr;\r | |
| 1393 | \r | |
| 1394 | Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);\r | |
| 1395 | AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);\r | |
| 1396 | @endcode\r | |
| ad8a2f5e | 1397 | @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r |
| 3adf6316 MK |
1398 | **/\r |
| 1399 | #define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C\r | |
| 1400 | \r | |
| 1401 | \r | |
| 1402 | /**\r | |
| dfb20851 ED |
1403 | Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r |
| 1404 | fields represent the widest possible range of uncore frequencies. Writing to\r | |
| 1405 | these fields allows software to control the minimum and the maximum\r | |
| 1406 | frequency that hardware will select.\r | |
| 1407 | \r | |
| 1408 | @param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)\r | |
| 1409 | @param EAX Lower 32-bits of MSR value.\r | |
| 1410 | Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.\r | |
| 1411 | @param EDX Upper 32-bits of MSR value.\r | |
| 1412 | Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.\r | |
| 1413 | \r | |
| 1414 | <b>Example usage</b>\r | |
| 1415 | @code\r | |
| 1416 | MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r | |
| 1417 | \r | |
| 1418 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);\r | |
| 1419 | AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r | |
| 1420 | @endcode\r | |
| 1421 | **/\r | |
| 1422 | #define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620\r | |
| 1423 | \r | |
| 1424 | /**\r | |
| 1425 | MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT\r | |
| 1426 | **/\r | |
| 1427 | typedef union {\r | |
| 1428 | ///\r | |
| 1429 | /// Individual bit fields\r | |
| 1430 | ///\r | |
| 1431 | struct {\r | |
| 1432 | ///\r | |
| 1433 | /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r | |
| 1434 | /// LLC/Ring.\r | |
| 1435 | ///\r | |
| 1436 | UINT32 MAX_RATIO:7;\r | |
| 1437 | UINT32 Reserved1:1;\r | |
| 1438 | ///\r | |
| 1439 | /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r | |
| 1440 | /// possible ratio of the LLC/Ring.\r | |
| 1441 | ///\r | |
| 1442 | UINT32 MIN_RATIO:7;\r | |
| 1443 | UINT32 Reserved2:17;\r | |
| 1444 | UINT32 Reserved3:32;\r | |
| 1445 | } Bits;\r | |
| 1446 | ///\r | |
| 1447 | /// All bit fields as a 32-bit value\r | |
| 1448 | ///\r | |
| 1449 | UINT32 Uint32;\r | |
| 1450 | ///\r | |
| 1451 | /// All bit fields as a 64-bit value\r | |
| 1452 | ///\r | |
| 1453 | UINT64 Uint64;\r | |
| 1454 | } MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;\r | |
| 1455 | \r | |
| 1456 | \r | |
| 1457 | /**\r | |
| 1458 | Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r | |
| 3adf6316 MK |
1459 | RAPL Domains.".\r |
| 1460 | \r | |
| 1461 | @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)\r | |
| 1462 | @param EAX Lower 32-bits of MSR value.\r | |
| 1463 | @param EDX Upper 32-bits of MSR value.\r | |
| 1464 | \r | |
| 1465 | <b>Example usage</b>\r | |
| 1466 | @code\r | |
| 1467 | UINT64 Msr;\r | |
| 1468 | \r | |
| 1469 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);\r | |
| 1470 | AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);\r | |
| 1471 | @endcode\r | |
| ad8a2f5e | 1472 | @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r |
| 3adf6316 MK |
1473 | **/\r |
| 1474 | #define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638\r | |
| 1475 | \r | |
| 1476 | \r | |
| 1477 | /**\r | |
| 1478 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
| 1479 | Domains.".\r | |
| 1480 | \r | |
| 1481 | @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)\r | |
| 1482 | @param EAX Lower 32-bits of MSR value.\r | |
| 1483 | @param EDX Upper 32-bits of MSR value.\r | |
| 1484 | \r | |
| 1485 | <b>Example usage</b>\r | |
| 1486 | @code\r | |
| 1487 | UINT64 Msr;\r | |
| 1488 | \r | |
| 1489 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);\r | |
| 1490 | @endcode\r | |
| ad8a2f5e | 1491 | @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r |
| 3adf6316 MK |
1492 | **/\r |
| 1493 | #define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639\r | |
| 1494 | \r | |
| 1495 | \r | |
| 1496 | /**\r | |
| ba1a2d11 | 1497 | Package. Base TDP Ratio (R/O) See Table 2-24.\r |
| 3adf6316 MK |
1498 | \r |
| 1499 | @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)\r | |
| 1500 | @param EAX Lower 32-bits of MSR value.\r | |
| 1501 | @param EDX Upper 32-bits of MSR value.\r | |
| 1502 | \r | |
| 1503 | <b>Example usage</b>\r | |
| 1504 | @code\r | |
| 1505 | UINT64 Msr;\r | |
| 1506 | \r | |
| 1507 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);\r | |
| 1508 | @endcode\r | |
| ad8a2f5e | 1509 | @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r |
| 3adf6316 MK |
1510 | **/\r |
| 1511 | #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648\r | |
| 1512 | \r | |
| 1513 | \r | |
| 1514 | /**\r | |
| ba1a2d11 | 1515 | Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.\r |
| 3adf6316 MK |
1516 | \r |
| 1517 | @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)\r | |
| 1518 | @param EAX Lower 32-bits of MSR value.\r | |
| 1519 | @param EDX Upper 32-bits of MSR value.\r | |
| 1520 | \r | |
| 1521 | <b>Example usage</b>\r | |
| 1522 | @code\r | |
| 1523 | UINT64 Msr;\r | |
| 1524 | \r | |
| 1525 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);\r | |
| 1526 | @endcode\r | |
| ad8a2f5e | 1527 | @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r |
| 3adf6316 MK |
1528 | **/\r |
| 1529 | #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649\r | |
| 1530 | \r | |
| 1531 | \r | |
| 1532 | /**\r | |
| ba1a2d11 | 1533 | Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.\r |
| 3adf6316 MK |
1534 | \r |
| 1535 | @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)\r | |
| 1536 | @param EAX Lower 32-bits of MSR value.\r | |
| 1537 | @param EDX Upper 32-bits of MSR value.\r | |
| 1538 | \r | |
| 1539 | <b>Example usage</b>\r | |
| 1540 | @code\r | |
| 1541 | UINT64 Msr;\r | |
| 1542 | \r | |
| 1543 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);\r | |
| 1544 | @endcode\r | |
| ad8a2f5e | 1545 | @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r |
| 3adf6316 MK |
1546 | **/\r |
| 1547 | #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A\r | |
| 1548 | \r | |
| 1549 | \r | |
| 1550 | /**\r | |
| ba1a2d11 | 1551 | Package. ConfigTDP Control (R/W) See Table 2-24.\r |
| 3adf6316 MK |
1552 | \r |
| 1553 | @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)\r | |
| 1554 | @param EAX Lower 32-bits of MSR value.\r | |
| 1555 | @param EDX Upper 32-bits of MSR value.\r | |
| 1556 | \r | |
| 1557 | <b>Example usage</b>\r | |
| 1558 | @code\r | |
| 1559 | UINT64 Msr;\r | |
| 1560 | \r | |
| 1561 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);\r | |
| 1562 | AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);\r | |
| 1563 | @endcode\r | |
| ad8a2f5e | 1564 | @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r |
| 3adf6316 MK |
1565 | **/\r |
| 1566 | #define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B\r | |
| 1567 | \r | |
| 1568 | \r | |
| 1569 | /**\r | |
| ba1a2d11 | 1570 | Package. ConfigTDP Control (R/W) See Table 2-24.\r |
| 3adf6316 MK |
1571 | \r |
| 1572 | @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)\r | |
| 1573 | @param EAX Lower 32-bits of MSR value.\r | |
| 1574 | @param EDX Upper 32-bits of MSR value.\r | |
| 1575 | \r | |
| 1576 | <b>Example usage</b>\r | |
| 1577 | @code\r | |
| 1578 | UINT64 Msr;\r | |
| 1579 | \r | |
| 1580 | Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);\r | |
| 1581 | AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);\r | |
| 1582 | @endcode\r | |
| ad8a2f5e | 1583 | @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r |
| 3adf6316 MK |
1584 | **/\r |
| 1585 | #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C\r | |
| 1586 | \r | |
| 1587 | \r | |
| 1588 | /**\r | |
| 1589 | Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r | |
| 1590 | refers to processor core frequency).\r | |
| 1591 | \r | |
| 1592 | @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)\r | |
| 1593 | @param EAX Lower 32-bits of MSR value.\r | |
| 1594 | Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1595 | @param EDX Upper 32-bits of MSR value.\r | |
| 1596 | Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1597 | \r | |
| 1598 | <b>Example usage</b>\r | |
| 1599 | @code\r | |
| 1600 | MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 1601 | \r | |
| 1602 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);\r | |
| 1603 | AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 1604 | @endcode\r | |
| ad8a2f5e | 1605 | @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r |
| 3adf6316 MK |
1606 | **/\r |
| 1607 | #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690\r | |
| 1608 | \r | |
| 1609 | /**\r | |
| 1610 | MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS\r | |
| 1611 | **/\r | |
| 1612 | typedef union {\r | |
| 1613 | ///\r | |
| 1614 | /// Individual bit fields\r | |
| 1615 | ///\r | |
| 1616 | struct {\r | |
| 1617 | ///\r | |
| 1618 | /// [Bit 0] PROCHOT Status (R0).\r | |
| 1619 | ///\r | |
| 1620 | UINT32 PROCHOT_Status:1;\r | |
| 1621 | ///\r | |
| 1622 | /// [Bit 1] Thermal Status (R0).\r | |
| 1623 | ///\r | |
| 1624 | UINT32 ThermalStatus:1;\r | |
| 1625 | UINT32 Reserved1:4;\r | |
| 1626 | ///\r | |
| 1627 | /// [Bit 6] VR Therm Alert Status (R0).\r | |
| 1628 | ///\r | |
| 1629 | UINT32 VRThermAlertStatus:1;\r | |
| 1630 | UINT32 Reserved2:1;\r | |
| 1631 | ///\r | |
| 1632 | /// [Bit 8] Electrical Design Point Status (R0).\r | |
| 1633 | ///\r | |
| 1634 | UINT32 ElectricalDesignPointStatus:1;\r | |
| 1635 | UINT32 Reserved3:23;\r | |
| 1636 | UINT32 Reserved4:32;\r | |
| 1637 | } Bits;\r | |
| 1638 | ///\r | |
| 1639 | /// All bit fields as a 32-bit value\r | |
| 1640 | ///\r | |
| 1641 | UINT32 Uint32;\r | |
| 1642 | ///\r | |
| 1643 | /// All bit fields as a 64-bit value\r | |
| 1644 | ///\r | |
| 1645 | UINT64 Uint64;\r | |
| 1646 | } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;\r | |
| 1647 | \r | |
| 1648 | #endif\r |