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[mirror_edk2.git] / UefiCpuPkg / Include / Register / SmramSaveStateMap.h
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70de765d
MK		 1/** @file\r
2SMRAM Save State Map Definitions.\r
3\r
4SMRAM Save State Map definitions based on contents of the\r
5Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
6 Volume 3C, Section 34.4 SMRAM\r
7 Volume 3C, Section 34.5 SMI Handler Execution Environment\r
8 Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs\r
9\r
10Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
0acd8697 11SPDX-License-Identifier: BSD-2-Clause-Patent\r
70de765d
MK		 12\r
13**/\r
14\r
15#ifndef __SMRAM_SAVE_STATE_MAP_H__\r
16#define __SMRAM_SAVE_STATE_MAP_H__\r
17\r
18///\r
19/// Default SMBASE address\r
20///\r
21#define SMM_DEFAULT_SMBASE 0x30000\r
22\r
23///\r
24/// Offset of SMM handler from SMBASE\r
25///\r
26#define SMM_HANDLER_OFFSET 0x8000\r
27\r
28///\r
29/// Offset of SMRAM Save State Map from SMBASE\r
30///\r
31#define SMRAM_SAVE_STATE_MAP_OFFSET 0xfc00\r
32\r
33#pragma pack (1)\r
34\r
35///\r
36/// 32-bit SMRAM Save State Map\r
37///\r
38typedef struct {\r
39 UINT8 Reserved[0x200]; // 7c00h\r
40 // Padded an extra 0x200 bytes so 32-bit and 64-bit\r
41 // SMRAM Save State Maps are the same size\r
42 UINT8 Reserved1[0xf8]; // 7e00h\r
43 UINT32 SMBASE; // 7ef8h\r
44 UINT32 SMMRevId; // 7efch\r
45 UINT16 IORestart; // 7f00h\r
46 UINT16 AutoHALTRestart; // 7f02h\r
47 UINT8 Reserved2[0x9C]; // 7f08h\r
48 UINT32 IOMemAddr; // 7fa0h\r
49 UINT32 IOMisc; // 7fa4h\r
50 UINT32 _ES; // 7fa8h\r
51 UINT32 _CS; // 7fach\r
52 UINT32 _SS; // 7fb0h\r
53 UINT32 _DS; // 7fb4h\r
54 UINT32 _FS; // 7fb8h\r
55 UINT32 _GS; // 7fbch\r
56 UINT32 Reserved3; // 7fc0h\r
57 UINT32 _TR; // 7fc4h\r
58 UINT32 _DR7; // 7fc8h\r
59 UINT32 _DR6; // 7fcch\r
60 UINT32 _EAX; // 7fd0h\r
61 UINT32 _ECX; // 7fd4h\r
62 UINT32 _EDX; // 7fd8h\r
63 UINT32 _EBX; // 7fdch\r
64 UINT32 _ESP; // 7fe0h\r
65 UINT32 _EBP; // 7fe4h\r
66 UINT32 _ESI; // 7fe8h\r
67 UINT32 _EDI; // 7fech\r
68 UINT32 _EIP; // 7ff0h\r
69 UINT32 _EFLAGS; // 7ff4h\r
70 UINT32 _CR3; // 7ff8h\r
71 UINT32 _CR0; // 7ffch\r
72} SMRAM_SAVE_STATE_MAP32;\r
73\r
74///\r
75/// 64-bit SMRAM Save State Map\r
76///\r
77typedef struct {\r
78 UINT8 Reserved1[0x1d0]; // 7c00h\r
79 UINT32 GdtBaseHiDword; // 7dd0h\r
80 UINT32 LdtBaseHiDword; // 7dd4h\r
81 UINT32 IdtBaseHiDword; // 7dd8h\r
82 UINT8 Reserved2[0xc]; // 7ddch\r
83 UINT64 IO_EIP; // 7de8h\r
84 UINT8 Reserved3[0x50]; // 7df0h\r
85 UINT32 _CR4; // 7e40h\r
86 UINT8 Reserved4[0x48]; // 7e44h\r
87 UINT32 GdtBaseLoDword; // 7e8ch\r
88 UINT32 Reserved5; // 7e90h\r
89 UINT32 IdtBaseLoDword; // 7e94h\r
90 UINT32 Reserved6; // 7e98h\r
91 UINT32 LdtBaseLoDword; // 7e9ch\r
92 UINT8 Reserved7[0x38]; // 7ea0h\r
93 UINT64 EptVmxControl; // 7ed8h\r
94 UINT32 EnEptVmxControl; // 7ee0h\r
95 UINT8 Reserved8[0x14]; // 7ee4h\r
96 UINT32 SMBASE; // 7ef8h\r
97 UINT32 SMMRevId; // 7efch\r
98 UINT16 IORestart; // 7f00h\r
99 UINT16 AutoHALTRestart; // 7f02h\r
100 UINT8 Reserved9[0x18]; // 7f04h\r
101 UINT64 _R15; // 7f1ch\r
102 UINT64 _R14;\r
103 UINT64 _R13;\r
104 UINT64 _R12;\r
105 UINT64 _R11;\r
106 UINT64 _R10;\r
107 UINT64 _R9;\r
108 UINT64 _R8;\r
109 UINT64 _RAX; // 7f5ch\r
110 UINT64 _RCX;\r
111 UINT64 _RDX;\r
112 UINT64 _RBX;\r
113 UINT64 _RSP;\r
114 UINT64 _RBP;\r
115 UINT64 _RSI;\r
116 UINT64 _RDI;\r
117 UINT64 IOMemAddr; // 7f9ch\r
118 UINT32 IOMisc; // 7fa4h\r
119 UINT32 _ES; // 7fa8h\r
120 UINT32 _CS;\r
121 UINT32 _SS;\r
122 UINT32 _DS;\r
123 UINT32 _FS;\r
124 UINT32 _GS;\r
125 UINT32 _LDTR; // 7fc0h\r
126 UINT32 _TR;\r
127 UINT64 _DR7; // 7fc8h\r
128 UINT64 _DR6;\r
129 UINT64 _RIP; // 7fd8h\r
130 UINT64 IA32_EFER; // 7fe0h\r
131 UINT64 _RFLAGS; // 7fe8h\r
132 UINT64 _CR3; // 7ff0h\r
133 UINT64 _CR0; // 7ff8h\r
134} SMRAM_SAVE_STATE_MAP64;\r
135\r
136///\r
137/// Union of 32-bit and 64-bit SMRAM Save State Maps\r
138///\r
139typedef union {\r
140 SMRAM_SAVE_STATE_MAP32 x86;\r
141 SMRAM_SAVE_STATE_MAP64 x64;\r
142} SMRAM_SAVE_STATE_MAP;\r
143\r
144///\r
145/// Minimum SMM Revision ID that supports IOMisc field in SMRAM Save State Map\r
146///\r
147#define SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC 0x30004\r
148\r
149///\r
150/// SMRAM Save State Map IOMisc I/O Length Values\r
151///\r
152#define SMM_IO_LENGTH_BYTE 0x01\r
153#define SMM_IO_LENGTH_WORD 0x02\r
154#define SMM_IO_LENGTH_DWORD 0x04\r
155\r
156///\r
157/// SMRAM Save State Map IOMisc I/O Instruction Type Values\r
158///\r
159#define SMM_IO_TYPE_IN_IMMEDIATE 0x9\r
160#define SMM_IO_TYPE_IN_DX 0x1\r
161#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8\r
162#define SMM_IO_TYPE_OUT_DX 0x0\r
163#define SMM_IO_TYPE_INS 0x3\r
164#define SMM_IO_TYPE_OUTS 0x2\r
165#define SMM_IO_TYPE_REP_INS 0x7\r
166#define SMM_IO_TYPE_REP_OUTS 0x6\r
167\r
168///\r
169/// SMRAM Save State Map IOMisc structure\r
170///\r
171typedef union {\r
172 struct {\r
173 UINT32 SmiFlag:1;\r
174 UINT32 Length:3;\r
175 UINT32 Type:4;\r
176 UINT32 Reserved1:8;\r
177 UINT32 Port:16;\r
178 } Bits;\r
179 UINT32 Uint32;\r
180} SMRAM_SAVE_STATE_IOMISC;\r
181\r
182#pragma pack ()\r
183\r
184#endif\r
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