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[mirror_edk2.git] / UefiCpuPkg / Library / BaseUefiCpuLib / Ia32 / InitializeFpu.asm
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989322c3 1;------------------------------------------------------------------------------\r
2;*\r
01a1c0fc
HT
3;* Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>\r
4;* This program and the accompanying materials\r
989322c3 5;* are licensed and made available under the terms and conditions of the BSD License\r
6;* which accompanies this distribution. The full text of the license may be found at\r
7;* http://opensource.org/licenses/bsd-license.php\r
8;*\r
9;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11;*\r
12;* \r
13;------------------------------------------------------------------------------\r
14\r
15\r
16 .686\r
17 .model flat,C\r
18 .const\r
19;\r
20; Float control word initial value: \r
21; all exceptions masked, double-precision, round-to-nearest\r
22;\r
23mFpuControlWord DW 027Fh\r
24;\r
25; Multimedia-extensions control word:\r
26; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
27;\r
28mMmxControlWord DD 01F80h \r
29\r
30 .xmm\r
31 .code\r
32\r
d6d8e892 33;\r
989322c3 34; Initializes floating point units for requirement of UEFI specification.\r
35;\r
36; This function initializes floating-point control word to 0x027F (all exceptions\r
37; masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
38; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
d6d8e892 39; for masked underflow).\r
989322c3 40;\r
41InitializeFloatingPointUnits PROC PUBLIC\r
d6d8e892 42\r
43 push ebx\r
44\r
989322c3 45 ;\r
46 ; Initialize floating point units\r
47 ;\r
48 finit\r
49 fldcw mFpuControlWord\r
50 \r
51 ;\r
52 ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
53 ; whether the processor supports SSE instruction.\r
54 ;\r
55 mov eax, 1\r
56 cpuid\r
57 bt edx, 25\r
58 jnc Done\r
59 \r
60 ;\r
61 ; Set OSFXSR bit 9 in CR4\r
62 ;\r
63 mov eax, cr4\r
64 or eax, BIT9\r
65 mov cr4, eax\r
66 \r
67 ;\r
68 ; The processor should support SSE instruction and we can use\r
69 ; ldmxcsr instruction\r
70 ;\r
71 ldmxcsr mMmxControlWord\r
72Done:\r
d6d8e892 73 pop ebx\r
989322c3 74\r
75 ret\r
76\r
77InitializeFloatingPointUnits ENDP\r
78\r
79END\r