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1 | ;------------------------------------------------------------------------------\r |
2 | ;*\r | |
5b78f30d | 3 | ;* Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 4 | ;* SPDX-License-Identifier: BSD-2-Clause-Patent\r |
f893042d LG |
5 | ;*\r |
6 | ;*\r | |
7 | ;------------------------------------------------------------------------------\r | |
8 | \r | |
5b78f30d | 9 | SECTION .rodata\r |
f893042d LG |
10 | \r |
11 | ;\r | |
12 | ; Float control word initial value:\r | |
13 | ; all exceptions masked, double-precision, round-to-nearest\r | |
14 | ;\r | |
15 | mFpuControlWord: DW 0x27F\r | |
16 | ;\r | |
17 | ; Multimedia-extensions control word:\r | |
18 | ; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r | |
19 | ;\r | |
20 | mMmxControlWord: DD 0x1F80\r | |
21 | \r | |
22 | SECTION .text\r | |
23 | \r | |
24 | ;\r | |
25 | ; Initializes floating point units for requirement of UEFI specification.\r | |
26 | ;\r | |
27 | ; This function initializes floating-point control word to 0x027F (all exceptions\r | |
28 | ; masked,double-precision, round-to-nearest) and multimedia-extensions control word\r | |
29 | ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r | |
30 | ; for masked underflow).\r | |
31 | ;\r | |
32 | global ASM_PFX(InitializeFloatingPointUnits)\r | |
33 | ASM_PFX(InitializeFloatingPointUnits):\r | |
34 | \r | |
35 | push ebx\r | |
36 | \r | |
37 | ;\r | |
38 | ; Initialize floating point units\r | |
39 | ;\r | |
40 | finit\r | |
41 | fldcw [mFpuControlWord]\r | |
42 | \r | |
43 | ;\r | |
44 | ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r | |
45 | ; whether the processor supports SSE instruction.\r | |
46 | ;\r | |
47 | mov eax, 1\r | |
48 | cpuid\r | |
49 | bt edx, 25\r | |
50 | jnc Done\r | |
51 | \r | |
52 | ;\r | |
53 | ; Set OSFXSR bit 9 in CR4\r | |
54 | ;\r | |
55 | mov eax, cr4\r | |
56 | or eax, BIT9\r | |
57 | mov cr4, eax\r | |
58 | \r | |
59 | ;\r | |
60 | ; The processor should support SSE instruction and we can use\r | |
61 | ; ldmxcsr instruction\r | |
62 | ;\r | |
63 | ldmxcsr [mMmxControlWord]\r | |
64 | Done:\r | |
65 | pop ebx\r | |
66 | \r | |
67 | ret\r | |
68 | \r |