Fix a bug in GetOptionalStringByIndex() that doesn't handle the case when Index ...
[mirror_edk2.git] / UefiCpuPkg / Library / BaseXApicLib / BaseXApicLib.c
CommitLineData
bf73cc4b 1/** @file\r
2 Local APIC Library.\r
3\r
4 This local APIC library instance supports xAPIC mode only.\r
5\r
6 Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#include <Register/LocalApic.h>\r
18\r
19#include <Library/BaseLib.h>\r
20#include <Library/DebugLib.h>\r
21#include <Library/LocalApicLib.h>\r
22#include <Library/IoLib.h>\r
23#include <Library/TimerLib.h>\r
24#include <Library/PcdLib.h>\r
25\r
26//\r
27// Library internal functions\r
28//\r
29\r
30/**\r
31 Read from a local APIC register.\r
32\r
33 This function reads from a local APIC register either in xAPIC or x2APIC mode.\r
34 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r
35 accessed using multiple 32-bit loads or stores, so this function only performs\r
36 32-bit read.\r
37\r
38 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r
39 It must be 16-byte aligned.\r
40\r
41 @return 32-bit Value read from the register.\r
42**/\r
43UINT32\r
44EFIAPI\r
45ReadLocalApicReg (\r
46 IN UINTN MmioOffset\r
47 )\r
48{\r
49 ASSERT ((MmioOffset & 0xf) == 0);\r
50 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
51\r
52 return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);\r
53}\r
54\r
55/**\r
56 Write to a local APIC register.\r
57\r
58 This function writes to a local APIC register either in xAPIC or x2APIC mode.\r
59 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r
60 accessed using multiple 32-bit loads or stores, so this function only performs\r
61 32-bit write.\r
62\r
63 if the register index is invalid or unsupported in current APIC mode, then ASSERT.\r
64\r
65 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r
66 It must be 16-byte aligned.\r
67 @param Value Value to be written to the register.\r
68**/\r
69VOID\r
70EFIAPI\r
71WriteLocalApicReg (\r
72 IN UINTN MmioOffset,\r
73 IN UINT32 Value\r
74 )\r
75{\r
76 ASSERT ((MmioOffset & 0xf) == 0);\r
77 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
78\r
79 MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);\r
80}\r
81\r
82/**\r
83 Send an IPI by writing to ICR.\r
84\r
85 This function returns after the IPI has been accepted by the target processor. \r
86\r
87 @param IcrLow 32-bit value to be written to the low half of ICR.\r
88 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r
89**/\r
90VOID\r
91SendIpi (\r
92 IN UINT32 IcrLow,\r
93 IN UINT32 ApicId\r
94 )\r
95{\r
96 LOCAL_APIC_ICR_LOW IcrLowReg;\r
97\r
98 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
99 ASSERT (ApicId <= 0xff);\r
100\r
101 //\r
102 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r
103 //\r
104 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r
105 WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);\r
106 do {\r
107 IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r
108 } while (IcrLowReg.Bits.DeliveryStatus != 0);\r
109}\r
110\r
111//\r
112// Library API implementation functions\r
113//\r
114\r
115/**\r
116 Get the current local APIC mode.\r
117\r
118 If local APIC is disabled, then ASSERT.\r
119\r
120 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r
121 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r
122**/\r
123UINTN\r
124EFIAPI\r
125GetApicMode (\r
126 VOID\r
127 )\r
128{\r
129 DEBUG_CODE (\r
130 {\r
131 MSR_IA32_APIC_BASE ApicBaseMsr;\r
132\r
133 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
134 //\r
135 // Local APIC should have been enabled\r
136 //\r
137 ASSERT (ApicBaseMsr.Bits.En != 0);\r
138 ASSERT (ApicBaseMsr.Bits.Extd == 0);\r
139 }\r
140 );\r
141 return LOCAL_APIC_MODE_XAPIC;\r
142}\r
143\r
144/**\r
145 Set the current local APIC mode.\r
146\r
147 If the specified local APIC mode is not valid, then ASSERT.\r
148 If the specified local APIC mode can't be set as current, then ASSERT.\r
149\r
150 @param ApicMode APIC mode to be set.\r
151**/\r
152VOID\r
153EFIAPI\r
154SetApicMode (\r
155 IN UINTN ApicMode\r
156 )\r
157{\r
158 ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);\r
159 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
160}\r
161\r
162/**\r
163 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
164\r
165 In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.\r
166 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
167 the 32-bit local APIC ID is returned as initial APIC ID.\r
168\r
169 @return 32-bit initial local APIC ID of the executing processor.\r
170**/\r
171UINT32\r
172EFIAPI\r
173GetInitialApicId (\r
174 VOID\r
175 )\r
176{\r
177 UINT32 RegEbx;\r
178\r
179 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
180\r
181 AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r
182 return RegEbx >> 24;\r
183}\r
184\r
185/**\r
186 Get the local APIC ID of the executing processor.\r
187\r
188 @return 32-bit local APIC ID of the executing processor.\r
189**/\r
190UINT32\r
191EFIAPI\r
192GetApicId (\r
193 VOID\r
194 )\r
195{\r
196 UINT32 ApicId;\r
197\r
198 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
199\r
200 ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r
201 ApicId >>= 24;\r
202 return ApicId;\r
203}\r
204\r
205/**\r
206 Send a SMI IPI to a specified target processor.\r
207\r
208 This function returns after the IPI has been accepted by the target processor. \r
209\r
210 @param ApicId Specify the local APIC ID of the target processor.\r
211**/\r
212VOID\r
213EFIAPI\r
214SendSmiIpi (\r
215 IN UINT32 ApicId\r
216 )\r
217{\r
218 LOCAL_APIC_ICR_LOW IcrLow;\r
219\r
220 IcrLow.Uint32 = 0;\r
221 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
222 IcrLow.Bits.Level = 1;\r
223 SendIpi (IcrLow.Uint32, ApicId);\r
224}\r
225\r
226/**\r
227 Send a SMI IPI to all processors excluding self.\r
228\r
229 This function returns after the IPI has been accepted by the target processors. \r
230**/\r
231VOID\r
232EFIAPI\r
233SendSmiIpiAllExcludingSelf (\r
234 VOID\r
235 )\r
236{\r
237 LOCAL_APIC_ICR_LOW IcrLow;\r
238\r
239 IcrLow.Uint32 = 0;\r
240 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
241 IcrLow.Bits.Level = 1;\r
242 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
243 SendIpi (IcrLow.Uint32, 0);\r
244}\r
245\r
246/**\r
247 Send an INIT IPI to a specified target processor.\r
248\r
249 This function returns after the IPI has been accepted by the target processor. \r
250\r
251 @param ApicId Specify the local APIC ID of the target processor.\r
252**/\r
253VOID\r
254EFIAPI\r
255SendInitIpi (\r
256 IN UINT32 ApicId\r
257 )\r
258{\r
259 LOCAL_APIC_ICR_LOW IcrLow;\r
260\r
261 IcrLow.Uint32 = 0;\r
262 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
263 IcrLow.Bits.Level = 1;\r
264 SendIpi (IcrLow.Uint32, ApicId);\r
265}\r
266\r
267/**\r
268 Send an INIT IPI to all processors excluding self.\r
269\r
270 This function returns after the IPI has been accepted by the target processors. \r
271**/\r
272VOID\r
273EFIAPI\r
274SendInitIpiAllExcludingSelf (\r
275 VOID\r
276 )\r
277{\r
278 LOCAL_APIC_ICR_LOW IcrLow;\r
279\r
280 IcrLow.Uint32 = 0;\r
281 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
282 IcrLow.Bits.Level = 1;\r
283 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
284 SendIpi (IcrLow.Uint32, 0);\r
285}\r
286\r
287/**\r
288 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
289\r
290 This function returns after the IPI has been accepted by the target processor. \r
291\r
292 if StartupRoutine >= 1M, then ASSERT.\r
293 if StartupRoutine is not multiple of 4K, then ASSERT.\r
294\r
295 @param ApicId Specify the local APIC ID of the target processor.\r
296 @param StartupRoutine Points to a start-up routine which is below 1M physical\r
297 address and 4K aligned.\r
298**/\r
299VOID\r
300EFIAPI\r
301SendInitSipiSipi (\r
302 IN UINT32 ApicId,\r
303 IN UINT32 StartupRoutine\r
304 )\r
305{\r
306 LOCAL_APIC_ICR_LOW IcrLow;\r
307\r
308 ASSERT (StartupRoutine < 0x100000);\r
309 ASSERT ((StartupRoutine & 0xfff) == 0);\r
310\r
311 SendInitIpi (ApicId);\r
312 MicroSecondDelay (10);\r
313 IcrLow.Uint32 = 0;\r
314 IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
315 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
316 IcrLow.Bits.Level = 1;\r
317 SendIpi (IcrLow.Uint32, ApicId);\r
318 MicroSecondDelay (200);\r
319 SendIpi (IcrLow.Uint32, ApicId);\r
320}\r
321\r
322/**\r
323 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
324\r
325 This function returns after the IPI has been accepted by the target processors. \r
326\r
327 if StartupRoutine >= 1M, then ASSERT.\r
328 if StartupRoutine is not multiple of 4K, then ASSERT.\r
329\r
330 @param StartupRoutine Points to a start-up routine which is below 1M physical\r
331 address and 4K aligned.\r
332**/\r
333VOID\r
334EFIAPI\r
335SendInitSipiSipiAllExcludingSelf (\r
336 IN UINT32 StartupRoutine\r
337 )\r
338{\r
339 LOCAL_APIC_ICR_LOW IcrLow;\r
340\r
341 ASSERT (StartupRoutine < 0x100000);\r
342 ASSERT ((StartupRoutine & 0xfff) == 0);\r
343\r
344 SendInitIpiAllExcludingSelf ();\r
345 MicroSecondDelay (10);\r
346 IcrLow.Uint32 = 0;\r
347 IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
348 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
349 IcrLow.Bits.Level = 1;\r
350 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
351 SendIpi (IcrLow.Uint32, 0);\r
352 MicroSecondDelay (200);\r
353 SendIpi (IcrLow.Uint32, 0);\r
354}\r
355\r
356/**\r
357 Programming Virtual Wire Mode.\r
358\r
359 This function programs the local APIC for virtual wire mode following\r
360 the example described in chapter A.3 of the MP 1.4 spec.\r
361\r
362 IOxAPIC is not involved in this type of virtual wire mode.\r
363**/\r
364VOID\r
365EFIAPI\r
366ProgramVirtualWireMode (\r
367 VOID\r
368 )\r
369{\r
370 LOCAL_APIC_SVR Svr;\r
371 LOCAL_APIC_LVT_LINT Lint;\r
372\r
373 //\r
374 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r
375 //\r
376 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
377 Svr.Bits.SpuriousVector = 0xf;\r
378 Svr.Bits.SoftwareEnable = 1;\r
379 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
380\r
381 //\r
382 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r
383 //\r
384 Lint.Uint32 = ReadLocalApicReg (XAPIC_LINT0_VECTOR_OFFSET);\r
385 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r
386 Lint.Bits.InputPinPolarity = 0;\r
387 Lint.Bits.TriggerMode = 0;\r
388 Lint.Bits.Mask = 0;\r
389 WriteLocalApicReg (XAPIC_LINT0_VECTOR_OFFSET, Lint.Uint32);\r
390\r
391 //\r
392 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r
393 //\r
394 Lint.Uint32 = ReadLocalApicReg (XAPIC_LINT1_VECTOR_OFFSET);\r
395 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r
396 Lint.Bits.InputPinPolarity = 0;\r
397 Lint.Bits.TriggerMode = 0;\r
398 Lint.Bits.Mask = 0;\r
399 WriteLocalApicReg (XAPIC_LINT1_VECTOR_OFFSET, Lint.Uint32);\r
400}\r
401\r
402/**\r
403 Get the divide value from the DCR (Divide Configuration Register) by which\r
404 the processor's bus clock is divided to form the time base for the APIC timer.\r
405\r
406 @return The divide value is one of 1,2,4,8,16,32,64,128.\r
407**/\r
408UINTN\r
409EFIAPI\r
410GetApicTimerDivisor (\r
411 VOID\r
412 )\r
413{\r
414 UINT32 DivideValue;\r
415 LOCAL_APIC_DCR Dcr;\r
416\r
417 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
418 DivideValue = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
419 DivideValue = (DivideValue + 1) & 0x7;\r
420 return ((UINTN)1) << DivideValue;\r
421}\r
422\r
423/**\r
424 Read the initial count value from the init-count register.\r
425\r
426 @return The initial count value read from the init-count register.\r
427**/\r
428UINT32\r
429EFIAPI\r
430GetApicTimerInitCount (\r
431 VOID\r
432 )\r
433{\r
434 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);\r
435}\r
436\r
437/**\r
438 Read the current count value from the current-count register.\r
439\r
440 @return The current count value read from the current-count register.\r
441**/\r
442UINT32\r
443EFIAPI\r
444GetApicTimerCurrentCount (\r
445 VOID\r
446 )\r
447{\r
448 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);\r
449}\r
450\r
451/**\r
452 Initialize the local APIC timer.\r
453\r
454 The local APIC timer is initialized and enabled.\r
455\r
456 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
457 If it is 0, then use the current divide value in the DCR.\r
458 @param InitCount The initial count value.\r
459 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
460 @param Vector The timer interrupt vector number.\r
461**/\r
462VOID\r
463EFIAPI\r
464InitializeApicTimer (\r
465 IN UINTN DivideValue,\r
466 IN UINT32 InitCount,\r
467 IN BOOLEAN PeriodicMode,\r
468 IN UINT8 Vector\r
469 )\r
470{\r
471 LOCAL_APIC_SVR Svr;\r
472 LOCAL_APIC_DCR Dcr;\r
473 LOCAL_APIC_LVT_TIMER LvtTimer;\r
474 UINT32 Divisor;\r
475\r
476 //\r
477 // Ensure local APIC is in software-enabled state.\r
478 //\r
479 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
480 Svr.Bits.SoftwareEnable = 1;\r
481 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
482\r
483 //\r
484 // Program init-count register.\r
485 //\r
486 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);\r
487\r
488 if (DivideValue != 0) {\r
489 ASSERT (DivideValue <= 128);\r
490 ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));\r
491 Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r
492\r
493 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
494 Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
495 Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
496 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); \r
497 }\r
498\r
499 //\r
500 // Enable APIC timer interrupt with specified timer mode.\r
501 //\r
502 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
503 if (PeriodicMode) {\r
504 LvtTimer.Bits.TimerMode = 1;\r
505 } else {\r
506 LvtTimer.Bits.TimerMode = 0;\r
507 }\r
508 LvtTimer.Bits.Mask = 0;\r
509 LvtTimer.Bits.Vector = Vector;\r
510 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
511}\r
512\r
513/**\r
514 Enable the local APIC timer interrupt.\r
515**/\r
516VOID\r
517EFIAPI\r
518EnableApicTimerInterrupt (\r
519 VOID\r
520 )\r
521{\r
522 LOCAL_APIC_LVT_TIMER LvtTimer;\r
523\r
524 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
525 LvtTimer.Bits.Mask = 0;\r
526 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
527}\r
528\r
529/**\r
530 Disable the local APIC timer interrupt.\r
531**/\r
532VOID\r
533EFIAPI\r
534DisableApicTimerInterrupt (\r
535 VOID\r
536 )\r
537{\r
538 LOCAL_APIC_LVT_TIMER LvtTimer;\r
539\r
540 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
541 LvtTimer.Bits.Mask = 1;\r
542 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
543}\r
544\r
545/**\r
546 Get the local APIC timer interrupt state.\r
547\r
548 @retval TRUE The local APIC timer interrupt is enabled.\r
549 @retval FALSE The local APIC timer interrupt is disabled.\r
550**/\r
551BOOLEAN\r
552EFIAPI\r
553GetApicTimerInterruptState (\r
554 VOID\r
555 )\r
556{\r
557 LOCAL_APIC_LVT_TIMER LvtTimer;\r
558\r
559 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
560 return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r
561}\r
562\r
563/**\r
564 Send EOI to the local APIC.\r
565**/\r
566VOID\r
567EFIAPI\r
568SendApicEoi (\r
569 VOID\r
570 )\r
571{\r
572 WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r
573}\r
574\r