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bf73cc4b | 1 | /** @file\r |
2 | Local APIC Library.\r | |
3 | \r | |
4 | This local APIC library instance supports x2APIC capable processors\r | |
5 | which have xAPIC and x2APIC modes.\r | |
6 | \r | |
cf1eb6e6 | 7 | Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r |
bf73cc4b | 8 | This program and the accompanying materials\r |
9 | are licensed and made available under the terms and conditions of the BSD License\r | |
10 | which accompanies this distribution. The full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
12 | \r | |
13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #include <Register/LocalApic.h>\r | |
19 | \r | |
20 | #include <Library/BaseLib.h>\r | |
21 | #include <Library/DebugLib.h>\r | |
22 | #include <Library/LocalApicLib.h>\r | |
23 | #include <Library/IoLib.h>\r | |
24 | #include <Library/TimerLib.h>\r | |
bf73cc4b | 25 | \r |
26 | //\r | |
27 | // Library internal functions\r | |
28 | //\r | |
29 | \r | |
a66e0c7d | 30 | /**\r |
31 | Retrieve the base address of local APIC.\r | |
32 | \r | |
33 | @return The base address of local APIC.\r | |
34 | \r | |
35 | **/\r | |
36 | UINTN\r | |
37 | EFIAPI\r | |
38 | GetLocalApicBaseAddress (\r | |
39 | VOID\r | |
40 | )\r | |
41 | {\r | |
42 | MSR_IA32_APIC_BASE ApicBaseMsr;\r | |
43 | \r | |
44 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r | |
45 | \r | |
46 | return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r | |
47 | (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);\r | |
48 | }\r | |
49 | \r | |
50 | /**\r | |
51 | Set the base address of local APIC.\r | |
52 | \r | |
53 | If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r | |
54 | \r | |
55 | @param[in] BaseAddress Local APIC base address to be set.\r | |
56 | \r | |
57 | **/\r | |
58 | VOID\r | |
59 | EFIAPI\r | |
60 | SetLocalApicBaseAddress (\r | |
61 | IN UINTN BaseAddress\r | |
62 | )\r | |
63 | {\r | |
64 | MSR_IA32_APIC_BASE ApicBaseMsr;\r | |
65 | \r | |
66 | ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r | |
67 | \r | |
68 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r | |
69 | \r | |
70 | ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);\r | |
71 | ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r | |
72 | \r | |
73 | AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r | |
74 | }\r | |
75 | \r | |
bf73cc4b | 76 | /**\r |
77 | Read from a local APIC register.\r | |
78 | \r | |
79 | This function reads from a local APIC register either in xAPIC or x2APIC mode.\r | |
80 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
81 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
82 | 32-bit read.\r | |
83 | \r | |
84 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
85 | It must be 16-byte aligned.\r | |
86 | \r | |
87 | @return 32-bit Value read from the register.\r | |
88 | **/\r | |
89 | UINT32\r | |
90 | EFIAPI\r | |
91 | ReadLocalApicReg (\r | |
92 | IN UINTN MmioOffset\r | |
93 | )\r | |
94 | {\r | |
95 | UINT32 MsrIndex;\r | |
96 | \r | |
97 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
98 | \r | |
99 | if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r | |
a66e0c7d | 100 | return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r |
bf73cc4b | 101 | } else {\r |
102 | //\r | |
103 | // DFR is not supported in x2APIC mode.\r | |
104 | //\r | |
105 | ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);\r | |
106 | //\r | |
107 | // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It\r | |
108 | // is not supported in this function for simplicity.\r | |
109 | //\r | |
110 | ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);\r | |
111 | \r | |
112 | MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;\r | |
113 | return AsmReadMsr32 (MsrIndex);\r | |
114 | }\r | |
115 | }\r | |
116 | \r | |
117 | /**\r | |
118 | Write to a local APIC register.\r | |
119 | \r | |
120 | This function writes to a local APIC register either in xAPIC or x2APIC mode.\r | |
121 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
122 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
123 | 32-bit write.\r | |
124 | \r | |
125 | if the register index is invalid or unsupported in current APIC mode, then ASSERT.\r | |
126 | \r | |
127 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
128 | It must be 16-byte aligned.\r | |
129 | @param Value Value to be written to the register.\r | |
130 | **/\r | |
131 | VOID\r | |
132 | EFIAPI\r | |
133 | WriteLocalApicReg (\r | |
134 | IN UINTN MmioOffset,\r | |
135 | IN UINT32 Value\r | |
136 | )\r | |
137 | {\r | |
138 | UINT32 MsrIndex;\r | |
139 | \r | |
140 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
141 | \r | |
142 | if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r | |
a66e0c7d | 143 | MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r |
bf73cc4b | 144 | } else {\r |
145 | //\r | |
146 | // DFR is not supported in x2APIC mode.\r | |
147 | //\r | |
148 | ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);\r | |
149 | //\r | |
150 | // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It\r | |
151 | // is not supported in this function for simplicity.\r | |
152 | //\r | |
153 | ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);\r | |
154 | ASSERT (MmioOffset != XAPIC_ICR_LOW_OFFSET);\r | |
155 | \r | |
156 | MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;\r | |
157 | //\r | |
158 | // The serializing semantics of WRMSR are relaxed when writing to the APIC registers.\r | |
159 | // Use memory fence here to force the serializing semantics to be consisent with xAPIC mode.\r | |
160 | //\r | |
161 | MemoryFence ();\r | |
162 | AsmWriteMsr32 (MsrIndex, Value);\r | |
163 | }\r | |
164 | }\r | |
165 | \r | |
166 | /**\r | |
167 | Send an IPI by writing to ICR.\r | |
168 | \r | |
169 | This function returns after the IPI has been accepted by the target processor. \r | |
170 | \r | |
171 | @param IcrLow 32-bit value to be written to the low half of ICR.\r | |
172 | @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r | |
173 | **/\r | |
174 | VOID\r | |
175 | SendIpi (\r | |
176 | IN UINT32 IcrLow,\r | |
177 | IN UINT32 ApicId\r | |
178 | )\r | |
179 | {\r | |
180 | UINT64 MsrValue;\r | |
181 | LOCAL_APIC_ICR_LOW IcrLowReg;\r | |
a66e0c7d | 182 | UINTN LocalApciBaseAddress;\r |
9c71e1e0 JF |
183 | UINT32 IcrHigh;\r |
184 | BOOLEAN InterruptState;\r | |
bf73cc4b | 185 | \r |
9c71e1e0 JF |
186 | //\r |
187 | // Legacy APIC or X2APIC?\r | |
188 | //\r | |
bf73cc4b | 189 | if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r |
190 | ASSERT (ApicId <= 0xff);\r | |
191 | \r | |
9c71e1e0 JF |
192 | InterruptState = SaveAndDisableInterrupts ();\r |
193 | \r | |
bf73cc4b | 194 | //\r |
9c71e1e0 | 195 | // Get base address of this LAPIC\r |
bf73cc4b | 196 | //\r |
a66e0c7d | 197 | LocalApciBaseAddress = GetLocalApicBaseAddress();\r |
9c71e1e0 JF |
198 | \r |
199 | //\r | |
200 | // Save existing contents of ICR high 32 bits\r | |
201 | //\r | |
202 | IcrHigh = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET);\r | |
203 | \r | |
204 | //\r | |
205 | // Wait for DeliveryStatus clear in case a previous IPI\r | |
206 | // is still being sent\r | |
207 | //\r | |
208 | do {\r | |
209 | IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);\r | |
210 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r | |
211 | \r | |
212 | //\r | |
213 | // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r | |
214 | //\r | |
a66e0c7d | 215 | MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r |
216 | MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);\r | |
9c71e1e0 JF |
217 | \r |
218 | //\r | |
219 | // Wait for DeliveryStatus clear again\r | |
220 | //\r | |
bf73cc4b | 221 | do {\r |
a66e0c7d | 222 | IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);\r |
bf73cc4b | 223 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r |
9c71e1e0 JF |
224 | \r |
225 | //\r | |
226 | // And restore old contents of ICR high\r | |
227 | //\r | |
228 | MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r | |
229 | \r | |
230 | SetInterruptState (InterruptState);\r | |
231 | \r | |
bf73cc4b | 232 | } else {\r |
233 | //\r | |
234 | // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an \r | |
235 | // interrupt in x2APIC mode.\r | |
236 | //\r | |
23394428 | 237 | MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;\r |
bf73cc4b | 238 | AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);\r |
239 | }\r | |
240 | }\r | |
241 | \r | |
242 | //\r | |
243 | // Library API implementation functions\r | |
244 | //\r | |
245 | \r | |
246 | /**\r | |
247 | Get the current local APIC mode.\r | |
248 | \r | |
249 | If local APIC is disabled, then ASSERT.\r | |
250 | \r | |
251 | @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r | |
252 | @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r | |
253 | **/\r | |
254 | UINTN\r | |
255 | EFIAPI\r | |
256 | GetApicMode (\r | |
257 | VOID\r | |
258 | )\r | |
259 | {\r | |
260 | MSR_IA32_APIC_BASE ApicBaseMsr;\r | |
261 | \r | |
262 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r | |
263 | //\r | |
264 | // Local APIC should have been enabled\r | |
265 | //\r | |
266 | ASSERT (ApicBaseMsr.Bits.En != 0);\r | |
267 | if (ApicBaseMsr.Bits.Extd != 0) {\r | |
268 | return LOCAL_APIC_MODE_X2APIC;\r | |
269 | } else {\r | |
270 | return LOCAL_APIC_MODE_XAPIC;\r | |
271 | }\r | |
272 | }\r | |
273 | \r | |
274 | /**\r | |
275 | Set the current local APIC mode.\r | |
276 | \r | |
277 | If the specified local APIC mode is not valid, then ASSERT.\r | |
278 | If the specified local APIC mode can't be set as current, then ASSERT.\r | |
279 | \r | |
280 | @param ApicMode APIC mode to be set.\r | |
9c71e1e0 JF |
281 | \r |
282 | @note This API must not be called from an interrupt handler or SMI handler.\r | |
283 | It may result in unpredictable behavior.\r | |
bf73cc4b | 284 | **/\r |
285 | VOID\r | |
286 | EFIAPI\r | |
287 | SetApicMode (\r | |
288 | IN UINTN ApicMode\r | |
289 | )\r | |
290 | {\r | |
291 | UINTN CurrentMode;\r | |
292 | MSR_IA32_APIC_BASE ApicBaseMsr;\r | |
293 | \r | |
294 | CurrentMode = GetApicMode ();\r | |
295 | if (CurrentMode == LOCAL_APIC_MODE_XAPIC) {\r | |
296 | switch (ApicMode) {\r | |
297 | case LOCAL_APIC_MODE_XAPIC:\r | |
298 | break;\r | |
299 | case LOCAL_APIC_MODE_X2APIC:\r | |
300 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r | |
301 | ApicBaseMsr.Bits.Extd = 1;\r | |
302 | AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r | |
303 | break;\r | |
304 | default:\r | |
305 | ASSERT (FALSE);\r | |
306 | }\r | |
307 | } else {\r | |
308 | switch (ApicMode) {\r | |
309 | case LOCAL_APIC_MODE_XAPIC:\r | |
310 | //\r | |
311 | // Transition from x2APIC mode to xAPIC mode is a two-step process:\r | |
312 | // x2APIC -> Local APIC disabled -> xAPIC\r | |
313 | //\r | |
314 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r | |
315 | ApicBaseMsr.Bits.Extd = 0;\r | |
316 | ApicBaseMsr.Bits.En = 0;\r | |
317 | AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r | |
318 | ApicBaseMsr.Bits.En = 1;\r | |
319 | AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r | |
320 | break;\r | |
321 | case LOCAL_APIC_MODE_X2APIC:\r | |
322 | break;\r | |
323 | default:\r | |
324 | ASSERT (FALSE);\r | |
325 | }\r | |
326 | }\r | |
327 | }\r | |
328 | \r | |
329 | /**\r | |
330 | Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r | |
331 | \r | |
6e3e4d70 | 332 | In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r |
bf73cc4b | 333 | In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r |
334 | the 32-bit local APIC ID is returned as initial APIC ID.\r | |
335 | \r | |
336 | @return 32-bit initial local APIC ID of the executing processor.\r | |
337 | **/\r | |
338 | UINT32\r | |
339 | EFIAPI\r | |
340 | GetInitialApicId (\r | |
341 | VOID\r | |
342 | )\r | |
343 | {\r | |
6e3e4d70 JF |
344 | UINT32 ApicId;\r |
345 | UINT32 MaxCpuIdIndex;\r | |
bf73cc4b | 346 | UINT32 RegEbx;\r |
347 | \r | |
348 | if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r | |
6e3e4d70 JF |
349 | //\r |
350 | // Get the max index of basic CPUID\r | |
351 | //\r | |
352 | AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r | |
353 | //\r | |
354 | // If CPUID Leaf B is supported, \r | |
355 | // Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r | |
356 | // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r | |
357 | //\r | |
358 | if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r | |
359 | AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, NULL, NULL, &ApicId);\r | |
360 | return ApicId;\r | |
361 | }\r | |
bf73cc4b | 362 | AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r |
363 | return RegEbx >> 24;\r | |
364 | } else {\r | |
365 | return GetApicId ();\r | |
366 | }\r | |
367 | }\r | |
368 | \r | |
369 | /**\r | |
370 | Get the local APIC ID of the executing processor.\r | |
371 | \r | |
372 | @return 32-bit local APIC ID of the executing processor.\r | |
373 | **/\r | |
374 | UINT32\r | |
375 | EFIAPI\r | |
376 | GetApicId (\r | |
377 | VOID\r | |
378 | )\r | |
379 | {\r | |
380 | UINT32 ApicId;\r | |
6e3e4d70 | 381 | UINT32 InitApicId;\r |
bf73cc4b | 382 | \r |
383 | ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r | |
384 | if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r | |
6e3e4d70 | 385 | ApicId = ((InitApicId = GetInitialApicId ()) < 0x100) ? (ApicId >> 24) : InitApicId;\r |
bf73cc4b | 386 | }\r |
6e3e4d70 | 387 | \r |
bf73cc4b | 388 | return ApicId;\r |
389 | }\r | |
390 | \r | |
ae40aef1 | 391 | /**\r |
392 | Get the value of the local APIC version register.\r | |
393 | \r | |
394 | @return the value of the local APIC version register.\r | |
395 | **/\r | |
396 | UINT32\r | |
397 | EFIAPI\r | |
398 | GetApicVersion (\r | |
399 | VOID\r | |
400 | )\r | |
401 | {\r | |
402 | return ReadLocalApicReg (XAPIC_VERSION_OFFSET);\r | |
403 | }\r | |
404 | \r | |
405 | /**\r | |
406 | Send a Fixed IPI to a specified target processor.\r | |
407 | \r | |
408 | This function returns after the IPI has been accepted by the target processor. \r | |
409 | \r | |
410 | @param ApicId The local APIC ID of the target processor.\r | |
411 | @param Vector The vector number of the interrupt being sent.\r | |
412 | **/\r | |
413 | VOID\r | |
414 | EFIAPI\r | |
415 | SendFixedIpi (\r | |
416 | IN UINT32 ApicId,\r | |
417 | IN UINT8 Vector\r | |
418 | )\r | |
419 | {\r | |
420 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
421 | \r | |
422 | IcrLow.Uint32 = 0;\r | |
423 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r | |
424 | IcrLow.Bits.Level = 1;\r | |
425 | IcrLow.Bits.Vector = Vector;\r | |
426 | SendIpi (IcrLow.Uint32, ApicId);\r | |
427 | }\r | |
428 | \r | |
429 | /**\r | |
430 | Send a Fixed IPI to all processors excluding self.\r | |
431 | \r | |
432 | This function returns after the IPI has been accepted by the target processors. \r | |
433 | \r | |
434 | @param Vector The vector number of the interrupt being sent.\r | |
435 | **/\r | |
436 | VOID\r | |
437 | EFIAPI\r | |
438 | SendFixedIpiAllExcludingSelf (\r | |
439 | IN UINT8 Vector\r | |
440 | )\r | |
441 | {\r | |
442 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
443 | \r | |
444 | IcrLow.Uint32 = 0;\r | |
445 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r | |
446 | IcrLow.Bits.Level = 1;\r | |
447 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
448 | IcrLow.Bits.Vector = Vector;\r | |
449 | SendIpi (IcrLow.Uint32, 0);\r | |
450 | }\r | |
451 | \r | |
bf73cc4b | 452 | /**\r |
453 | Send a SMI IPI to a specified target processor.\r | |
454 | \r | |
455 | This function returns after the IPI has been accepted by the target processor. \r | |
456 | \r | |
457 | @param ApicId Specify the local APIC ID of the target processor.\r | |
458 | **/\r | |
459 | VOID\r | |
460 | EFIAPI\r | |
461 | SendSmiIpi (\r | |
462 | IN UINT32 ApicId\r | |
463 | )\r | |
464 | {\r | |
465 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
466 | \r | |
467 | IcrLow.Uint32 = 0;\r | |
468 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r | |
469 | IcrLow.Bits.Level = 1;\r | |
470 | SendIpi (IcrLow.Uint32, ApicId);\r | |
471 | }\r | |
472 | \r | |
473 | /**\r | |
474 | Send a SMI IPI to all processors excluding self.\r | |
475 | \r | |
476 | This function returns after the IPI has been accepted by the target processors. \r | |
477 | **/\r | |
478 | VOID\r | |
479 | EFIAPI\r | |
480 | SendSmiIpiAllExcludingSelf (\r | |
481 | VOID\r | |
482 | )\r | |
483 | {\r | |
484 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
485 | \r | |
486 | IcrLow.Uint32 = 0;\r | |
487 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r | |
488 | IcrLow.Bits.Level = 1;\r | |
489 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
490 | SendIpi (IcrLow.Uint32, 0);\r | |
491 | }\r | |
492 | \r | |
493 | /**\r | |
494 | Send an INIT IPI to a specified target processor.\r | |
495 | \r | |
496 | This function returns after the IPI has been accepted by the target processor. \r | |
497 | \r | |
498 | @param ApicId Specify the local APIC ID of the target processor.\r | |
499 | **/\r | |
500 | VOID\r | |
501 | EFIAPI\r | |
502 | SendInitIpi (\r | |
503 | IN UINT32 ApicId\r | |
504 | )\r | |
505 | {\r | |
506 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
507 | \r | |
508 | IcrLow.Uint32 = 0;\r | |
509 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r | |
510 | IcrLow.Bits.Level = 1;\r | |
511 | SendIpi (IcrLow.Uint32, ApicId);\r | |
512 | }\r | |
513 | \r | |
514 | /**\r | |
515 | Send an INIT IPI to all processors excluding self.\r | |
516 | \r | |
517 | This function returns after the IPI has been accepted by the target processors. \r | |
518 | **/\r | |
519 | VOID\r | |
520 | EFIAPI\r | |
521 | SendInitIpiAllExcludingSelf (\r | |
522 | VOID\r | |
523 | )\r | |
524 | {\r | |
525 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
526 | \r | |
527 | IcrLow.Uint32 = 0;\r | |
528 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r | |
529 | IcrLow.Bits.Level = 1;\r | |
530 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
531 | SendIpi (IcrLow.Uint32, 0);\r | |
532 | }\r | |
533 | \r | |
534 | /**\r | |
535 | Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r | |
536 | \r | |
537 | This function returns after the IPI has been accepted by the target processor. \r | |
538 | \r | |
539 | if StartupRoutine >= 1M, then ASSERT.\r | |
540 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
541 | \r | |
542 | @param ApicId Specify the local APIC ID of the target processor.\r | |
543 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
544 | address and 4K aligned.\r | |
545 | **/\r | |
546 | VOID\r | |
547 | EFIAPI\r | |
548 | SendInitSipiSipi (\r | |
549 | IN UINT32 ApicId,\r | |
550 | IN UINT32 StartupRoutine\r | |
551 | )\r | |
552 | {\r | |
553 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
554 | \r | |
555 | ASSERT (StartupRoutine < 0x100000);\r | |
556 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
557 | \r | |
558 | SendInitIpi (ApicId);\r | |
cf1eb6e6 | 559 | MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r |
bf73cc4b | 560 | IcrLow.Uint32 = 0;\r |
561 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
562 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r | |
563 | IcrLow.Bits.Level = 1;\r | |
564 | SendIpi (IcrLow.Uint32, ApicId);\r | |
565 | MicroSecondDelay (200);\r | |
566 | SendIpi (IcrLow.Uint32, ApicId);\r | |
567 | }\r | |
568 | \r | |
569 | /**\r | |
570 | Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r | |
571 | \r | |
572 | This function returns after the IPI has been accepted by the target processors. \r | |
573 | \r | |
574 | if StartupRoutine >= 1M, then ASSERT.\r | |
575 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
576 | \r | |
577 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
578 | address and 4K aligned.\r | |
579 | **/\r | |
580 | VOID\r | |
581 | EFIAPI\r | |
582 | SendInitSipiSipiAllExcludingSelf (\r | |
583 | IN UINT32 StartupRoutine\r | |
584 | )\r | |
585 | {\r | |
586 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
587 | \r | |
588 | ASSERT (StartupRoutine < 0x100000);\r | |
589 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
590 | \r | |
591 | SendInitIpiAllExcludingSelf ();\r | |
cf1eb6e6 | 592 | MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r |
bf73cc4b | 593 | IcrLow.Uint32 = 0;\r |
594 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
595 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r | |
596 | IcrLow.Bits.Level = 1;\r | |
597 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
598 | SendIpi (IcrLow.Uint32, 0);\r | |
599 | MicroSecondDelay (200);\r | |
600 | SendIpi (IcrLow.Uint32, 0);\r | |
601 | }\r | |
602 | \r | |
603 | /**\r | |
604 | Programming Virtual Wire Mode.\r | |
605 | \r | |
606 | This function programs the local APIC for virtual wire mode following\r | |
607 | the example described in chapter A.3 of the MP 1.4 spec.\r | |
608 | \r | |
609 | IOxAPIC is not involved in this type of virtual wire mode.\r | |
610 | **/\r | |
611 | VOID\r | |
612 | EFIAPI\r | |
613 | ProgramVirtualWireMode (\r | |
614 | VOID\r | |
615 | )\r | |
616 | {\r | |
617 | LOCAL_APIC_SVR Svr;\r | |
618 | LOCAL_APIC_LVT_LINT Lint;\r | |
619 | \r | |
620 | //\r | |
621 | // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r | |
622 | //\r | |
623 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r | |
624 | Svr.Bits.SpuriousVector = 0xf;\r | |
625 | Svr.Bits.SoftwareEnable = 1;\r | |
626 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
627 | \r | |
628 | //\r | |
629 | // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r | |
630 | //\r | |
ae40aef1 | 631 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r |
bf73cc4b | 632 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r |
633 | Lint.Bits.InputPinPolarity = 0;\r | |
634 | Lint.Bits.TriggerMode = 0;\r | |
635 | Lint.Bits.Mask = 0;\r | |
ae40aef1 | 636 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r |
bf73cc4b | 637 | \r |
638 | //\r | |
639 | // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r | |
640 | //\r | |
ae40aef1 | 641 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r |
bf73cc4b | 642 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r |
643 | Lint.Bits.InputPinPolarity = 0;\r | |
644 | Lint.Bits.TriggerMode = 0;\r | |
645 | Lint.Bits.Mask = 0;\r | |
ae40aef1 | 646 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r |
bf73cc4b | 647 | }\r |
648 | \r | |
b1b8c631 | 649 | /**\r |
650 | Disable LINT0 & LINT1 interrupts.\r | |
651 | \r | |
652 | This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r | |
653 | **/\r | |
654 | VOID\r | |
655 | EFIAPI\r | |
656 | DisableLvtInterrupts (\r | |
657 | VOID\r | |
658 | )\r | |
659 | {\r | |
660 | LOCAL_APIC_LVT_LINT LvtLint;\r | |
661 | \r | |
662 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r | |
663 | LvtLint.Bits.Mask = 1;\r | |
664 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r | |
665 | \r | |
666 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r | |
667 | LvtLint.Bits.Mask = 1;\r | |
668 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r | |
669 | }\r | |
670 | \r | |
bf73cc4b | 671 | /**\r |
672 | Read the initial count value from the init-count register.\r | |
673 | \r | |
674 | @return The initial count value read from the init-count register.\r | |
675 | **/\r | |
676 | UINT32\r | |
677 | EFIAPI\r | |
678 | GetApicTimerInitCount (\r | |
679 | VOID\r | |
680 | )\r | |
681 | {\r | |
682 | return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);\r | |
683 | }\r | |
684 | \r | |
685 | /**\r | |
686 | Read the current count value from the current-count register.\r | |
687 | \r | |
688 | @return The current count value read from the current-count register.\r | |
689 | **/\r | |
690 | UINT32\r | |
691 | EFIAPI\r | |
692 | GetApicTimerCurrentCount (\r | |
693 | VOID\r | |
694 | )\r | |
695 | {\r | |
696 | return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);\r | |
697 | }\r | |
698 | \r | |
699 | /**\r | |
700 | Initialize the local APIC timer.\r | |
701 | \r | |
702 | The local APIC timer is initialized and enabled.\r | |
703 | \r | |
704 | @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
705 | If it is 0, then use the current divide value in the DCR.\r | |
706 | @param InitCount The initial count value.\r | |
707 | @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
708 | @param Vector The timer interrupt vector number.\r | |
709 | **/\r | |
710 | VOID\r | |
711 | EFIAPI\r | |
712 | InitializeApicTimer (\r | |
713 | IN UINTN DivideValue,\r | |
714 | IN UINT32 InitCount,\r | |
715 | IN BOOLEAN PeriodicMode,\r | |
716 | IN UINT8 Vector\r | |
717 | )\r | |
718 | {\r | |
719 | LOCAL_APIC_SVR Svr;\r | |
720 | LOCAL_APIC_DCR Dcr;\r | |
721 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
722 | UINT32 Divisor;\r | |
723 | \r | |
724 | //\r | |
725 | // Ensure local APIC is in software-enabled state.\r | |
726 | //\r | |
727 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r | |
728 | Svr.Bits.SoftwareEnable = 1;\r | |
729 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
730 | \r | |
731 | //\r | |
732 | // Program init-count register.\r | |
733 | //\r | |
734 | WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);\r | |
735 | \r | |
736 | if (DivideValue != 0) {\r | |
737 | ASSERT (DivideValue <= 128);\r | |
738 | ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));\r | |
739 | Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r | |
740 | \r | |
741 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r | |
742 | Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r | |
743 | Dcr.Bits.DivideValue2 = (Divisor >> 2);\r | |
744 | WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); \r | |
745 | }\r | |
746 | \r | |
747 | //\r | |
748 | // Enable APIC timer interrupt with specified timer mode.\r | |
749 | //\r | |
750 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
751 | if (PeriodicMode) {\r | |
752 | LvtTimer.Bits.TimerMode = 1;\r | |
753 | } else {\r | |
754 | LvtTimer.Bits.TimerMode = 0;\r | |
755 | }\r | |
756 | LvtTimer.Bits.Mask = 0;\r | |
757 | LvtTimer.Bits.Vector = Vector;\r | |
758 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
759 | }\r | |
760 | \r | |
ae40aef1 | 761 | /**\r |
762 | Get the state of the local APIC timer.\r | |
763 | \r | |
764 | @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
765 | @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
766 | @param Vector Return the timer interrupt vector number.\r | |
767 | **/\r | |
768 | VOID\r | |
769 | EFIAPI\r | |
770 | GetApicTimerState (\r | |
771 | OUT UINTN *DivideValue OPTIONAL,\r | |
772 | OUT BOOLEAN *PeriodicMode OPTIONAL,\r | |
773 | OUT UINT8 *Vector OPTIONAL\r | |
774 | )\r | |
775 | {\r | |
776 | UINT32 Divisor;\r | |
777 | LOCAL_APIC_DCR Dcr;\r | |
778 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
779 | \r | |
780 | if (DivideValue != NULL) {\r | |
781 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r | |
782 | Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r | |
783 | Divisor = (Divisor + 1) & 0x7;\r | |
784 | *DivideValue = ((UINTN)1) << Divisor;\r | |
785 | }\r | |
786 | \r | |
787 | if (PeriodicMode != NULL || Vector != NULL) {\r | |
788 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
789 | if (PeriodicMode != NULL) {\r | |
790 | if (LvtTimer.Bits.TimerMode == 1) {\r | |
791 | *PeriodicMode = TRUE;\r | |
792 | } else {\r | |
793 | *PeriodicMode = FALSE;\r | |
794 | }\r | |
795 | }\r | |
796 | if (Vector != NULL) {\r | |
797 | *Vector = (UINT8) LvtTimer.Bits.Vector;\r | |
798 | }\r | |
799 | }\r | |
800 | }\r | |
801 | \r | |
bf73cc4b | 802 | /**\r |
803 | Enable the local APIC timer interrupt.\r | |
804 | **/\r | |
805 | VOID\r | |
806 | EFIAPI\r | |
807 | EnableApicTimerInterrupt (\r | |
808 | VOID\r | |
809 | )\r | |
810 | {\r | |
811 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
812 | \r | |
813 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
814 | LvtTimer.Bits.Mask = 0;\r | |
815 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
816 | }\r | |
817 | \r | |
818 | /**\r | |
819 | Disable the local APIC timer interrupt.\r | |
820 | **/\r | |
821 | VOID\r | |
822 | EFIAPI\r | |
823 | DisableApicTimerInterrupt (\r | |
824 | VOID\r | |
825 | )\r | |
826 | {\r | |
827 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
828 | \r | |
829 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
830 | LvtTimer.Bits.Mask = 1;\r | |
831 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
832 | }\r | |
833 | \r | |
834 | /**\r | |
835 | Get the local APIC timer interrupt state.\r | |
836 | \r | |
837 | @retval TRUE The local APIC timer interrupt is enabled.\r | |
838 | @retval FALSE The local APIC timer interrupt is disabled.\r | |
839 | **/\r | |
840 | BOOLEAN\r | |
841 | EFIAPI\r | |
842 | GetApicTimerInterruptState (\r | |
843 | VOID\r | |
844 | )\r | |
845 | {\r | |
846 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
847 | \r | |
848 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
849 | return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r | |
850 | }\r | |
851 | \r | |
852 | /**\r | |
853 | Send EOI to the local APIC.\r | |
854 | **/\r | |
855 | VOID\r | |
856 | EFIAPI\r | |
857 | SendApicEoi (\r | |
858 | VOID\r | |
859 | )\r | |
860 | {\r | |
861 | WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r | |
862 | }\r | |
863 | \r | |
5f867ad0 | 864 | /**\r |
865 | Get the 32-bit address that a device should use to send a Message Signaled \r | |
866 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r | |
867 | \r | |
868 | @return 32-bit address used to send an MSI to the Local APIC.\r | |
869 | **/\r | |
870 | UINT32\r | |
871 | EFIAPI \r | |
872 | GetApicMsiAddress (\r | |
873 | VOID\r | |
874 | )\r | |
875 | {\r | |
876 | LOCAL_APIC_MSI_ADDRESS MsiAddress;\r | |
877 | \r | |
878 | //\r | |
879 | // Return address for an MSI interrupt to be delivered only to the APIC ID \r | |
880 | // of the currently executing processor.\r | |
881 | //\r | |
882 | MsiAddress.Uint32 = 0;\r | |
883 | MsiAddress.Bits.BaseAddress = 0xFEE;\r | |
884 | MsiAddress.Bits.DestinationId = GetApicId ();\r | |
885 | return MsiAddress.Uint32;\r | |
886 | }\r | |
887 | \r | |
888 | /**\r | |
889 | Get the 64-bit data value that a device should use to send a Message Signaled \r | |
890 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r | |
891 | \r | |
892 | If Vector is not in range 0x10..0xFE, then ASSERT().\r | |
893 | If DeliveryMode is not supported, then ASSERT().\r | |
894 | \r | |
895 | @param Vector The 8-bit interrupt vector associated with the MSI. \r | |
896 | Must be in the range 0x10..0xFE\r | |
897 | @param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r | |
898 | is handled. The only supported values are:\r | |
899 | 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r | |
900 | 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r | |
901 | 2: LOCAL_APIC_DELIVERY_MODE_SMI\r | |
902 | 4: LOCAL_APIC_DELIVERY_MODE_NMI\r | |
903 | 5: LOCAL_APIC_DELIVERY_MODE_INIT\r | |
904 | 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r | |
905 | \r | |
906 | @param LevelTriggered TRUE specifies a level triggered interrupt. \r | |
907 | FALSE specifies an edge triggered interrupt.\r | |
908 | @param AssertionLevel Ignored if LevelTriggered is FALSE.\r | |
909 | TRUE specifies a level triggered interrupt that active \r | |
910 | when the interrupt line is asserted.\r | |
911 | FALSE specifies a level triggered interrupt that active \r | |
912 | when the interrupt line is deasserted.\r | |
913 | \r | |
914 | @return 64-bit data value used to send an MSI to the Local APIC.\r | |
915 | **/\r | |
916 | UINT64\r | |
917 | EFIAPI \r | |
918 | GetApicMsiValue (\r | |
919 | IN UINT8 Vector,\r | |
920 | IN UINTN DeliveryMode,\r | |
921 | IN BOOLEAN LevelTriggered,\r | |
922 | IN BOOLEAN AssertionLevel\r | |
923 | )\r | |
924 | {\r | |
925 | LOCAL_APIC_MSI_DATA MsiData;\r | |
926 | \r | |
927 | ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r | |
928 | ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r | |
929 | \r | |
930 | MsiData.Uint64 = 0;\r | |
931 | MsiData.Bits.Vector = Vector;\r | |
932 | MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r | |
933 | if (LevelTriggered) {\r | |
934 | MsiData.Bits.TriggerMode = 1;\r | |
935 | if (AssertionLevel) {\r | |
936 | MsiData.Bits.Level = 1;\r | |
937 | }\r | |
938 | }\r | |
939 | return MsiData.Uint64;\r | |
940 | }\r |