UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / UefiCpuPkg / Library / CpuCommonFeaturesLib / Ppin.c

/** @file\r
  Protected Processor Inventory Number(PPIN) feature.\r
\r
  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "CpuCommonFeatures.h"\r
\r
/**\r
  Prepares for the data used by CPU feature detection and initialization.\r
\r
  @param[in]  NumberOfProcessors  The number of CPUs in the platform.\r
\r
  @return  Pointer to a buffer of CPU related configuration data.\r
\r
  @note This service could be called by BSP only.\r
**/\r
VOID *\r
EFIAPI\r
PpinGetConfigData (\r
  IN UINTN  NumberOfProcessors\r
  )\r
{\r
  VOID  *ConfigData;\r
\r
  ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors);\r
  ASSERT (ConfigData != NULL);\r
  return ConfigData;\r
}\r
\r
/**\r
  Detects if Protected Processor Inventory Number feature supported on current\r
  processor.\r
\r
  @param[in]  ProcessorNumber  The index of the CPU executing this function.\r
  @param[in]  CpuInfo          A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r
                               structure for the CPU executing this function.\r
  @param[in]  ConfigData       A pointer to the configuration buffer returned\r
                               by CPU_FEATURE_GET_CONFIG_DATA.  NULL if\r
                               CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
                               RegisterCpuFeature().\r
\r
  @retval TRUE     Protected Processor Inventory Number feature is supported.\r
  @retval FALSE    Protected Processor Inventory Number feature is not supported.\r
\r
  @note This service could be called by BSP/APs.\r
**/\r
BOOLEAN\r
EFIAPI\r
PpinSupport (\r
  IN UINTN                             ProcessorNumber,\r
  IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,\r
  IN VOID                              *ConfigData  OPTIONAL\r
  )\r
{\r
  MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER  PlatformInfo;\r
  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER         *MsrPpinCtrl;\r
\r
  if ((CpuInfo->DisplayFamily == 0x06) &&\r
      ((CpuInfo->DisplayModel == 0x3E) ||      // Xeon E5 V2\r
       (CpuInfo->DisplayModel == 0x56) ||      // Xeon Processor D Product\r
       (CpuInfo->DisplayModel == 0x4F) ||      // Xeon E5 v4, E7 v4\r
       (CpuInfo->DisplayModel == 0x55) ||      // Xeon Processor Scalable\r
       (CpuInfo->DisplayModel == 0x57) ||      // Xeon Phi processor 3200, 5200, 7200 series.\r
       (CpuInfo->DisplayModel == 0x85)         // Future Xeon phi processor\r
      ))\r
  {\r
    //\r
    // Check whether platform support this feature.\r
    //\r
    PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r
    if (PlatformInfo.Bits.PPIN_CAP != 0) {\r
      MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;\r
      ASSERT (MsrPpinCtrl != NULL);\r
      MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r
      return TRUE;\r
    }\r
  }\r
\r
  return FALSE;\r
}\r
\r
/**\r
  Initializes Protected Processor Inventory Number feature to specific state.\r
\r
  @param[in]  ProcessorNumber  The index of the CPU executing this function.\r
  @param[in]  CpuInfo          A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r
                               structure for the CPU executing this function.\r
  @param[in]  ConfigData       A pointer to the configuration buffer returned\r
                               by CPU_FEATURE_GET_CONFIG_DATA.  NULL if\r
                               CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
                               RegisterCpuFeature().\r
  @param[in]  State            If TRUE, then the Protected Processor Inventory\r
                               Number feature must be enabled.\r
                               If FALSE, then the Protected Processor Inventory\r
                               Number feature must be disabled.\r
\r
  @retval RETURN_SUCCESS       Protected Processor Inventory Number feature is\r
                               initialized.\r
  @retval RETURN_DEVICE_ERROR  Device can't change state because it has been\r
                               locked.\r
\r
  @note This service could be called by BSP only.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PpinInitialize (\r
  IN UINTN                             ProcessorNumber,\r
  IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,\r
  IN VOID                              *ConfigData   OPTIONAL,\r
  IN BOOLEAN                           State\r
  )\r
{\r
  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER  *MsrPpinCtrl;\r
\r
  MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;\r
  ASSERT (MsrPpinCtrl != NULL);\r
\r
  //\r
  // Check whether processor already lock this register.\r
  // If already locked, just based on the request state and\r
  // the current state to return the status.\r
  //\r
  if (MsrPpinCtrl[ProcessorNumber].Bits.LockOut != 0) {\r
    return MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN == State ? RETURN_SUCCESS : RETURN_DEVICE_ERROR;\r
  }\r
\r
  //\r
  // Support function already check the processor which support PPIN feature, so this function not need\r
  // to check the processor again.\r
  //\r
  // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL\r
  // once for each package.\r
  //\r
  if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {\r
    return RETURN_SUCCESS;\r
  }\r
\r
  if (State) {\r
    //\r
    // Enable and Unlock.\r
    // According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP.\r
    //\r
    MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1;\r
    MsrPpinCtrl[ProcessorNumber].Bits.LockOut     = 0;\r
  } else {\r
    //\r
    // Disable and Lock.\r
    // According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear.\r
    //\r
    MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0;\r
    MsrPpinCtrl[ProcessorNumber].Bits.LockOut     = 1;\r
  }\r
\r
  CPU_REGISTER_TABLE_WRITE64 (\r
    ProcessorNumber,\r
    Msr,\r
    MSR_IVY_BRIDGE_PPIN_CTL,\r
    MsrPpinCtrl[ProcessorNumber].Uint64\r
    );\r
\r
  return RETURN_SUCCESS;\r
}\r