UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / UefiCpuPkg / Library / CpuCommonFeaturesLib / ProcTrace.c

/** @file\r
  Intel Processor Trace feature.\r
\r
  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "CpuCommonFeatures.h"\r
\r
///\r
/// This macro define the max entries in the Topa table.\r
/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.\r
/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the\r
/// current table (for circular array) or to the base of another table.\r
/// At least 2 entries are needed because the list of entries must\r
/// be terminated by an entry with the END bit set to 1, so 2\r
/// entries are required to use a single valid entry.\r
///\r
#define MAX_TOPA_ENTRY_COUNT  2\r
\r
///\r
/// Processor trace output scheme selection.\r
///\r
typedef enum {\r
  RtitOutputSchemeSingleRange = 0,\r
  RtitOutputSchemeToPA\r
} RTIT_OUTPUT_SCHEME;\r
\r
typedef struct  {\r
  BOOLEAN                                    TopaSupported;\r
  BOOLEAN                                    SingleRangeSupported;\r
  MSR_IA32_RTIT_CTL_REGISTER                 RtitCtrl;\r
  MSR_IA32_RTIT_OUTPUT_BASE_REGISTER         RtitOutputBase;\r
  MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER    RtitOutputMaskPtrs;\r
} PROC_TRACE_PROCESSOR_DATA;\r
\r
typedef struct  {\r
  UINT32                       NumberOfProcessors;\r
\r
  UINT8                        ProcTraceOutputScheme;\r
  UINT32                       ProcTraceMemSize;\r
\r
  UINTN                        *ThreadMemRegionTable;\r
  UINTN                        AllocatedThreads;\r
\r
  UINTN                        *TopaMemArray;\r
\r
  PROC_TRACE_PROCESSOR_DATA    *ProcessorData;\r
} PROC_TRACE_DATA;\r
\r
typedef struct {\r
  RTIT_TOPA_TABLE_ENTRY    TopaEntry[MAX_TOPA_ENTRY_COUNT];\r
} PROC_TRACE_TOPA_TABLE;\r
\r
/**\r
  Prepares for the data used by CPU feature detection and initialization.\r
\r
  @param[in]  NumberOfProcessors  The number of CPUs in the platform.\r
\r
  @return  Pointer to a buffer of CPU related configuration data.\r
\r
  @note This service could be called by BSP only.\r
**/\r
VOID *\r
EFIAPI\r
ProcTraceGetConfigData (\r
  IN UINTN  NumberOfProcessors\r
  )\r
{\r
  PROC_TRACE_DATA  *ConfigData;\r
\r
  ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors);\r
  ASSERT (ConfigData != NULL);\r
  ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *)((UINT8 *)ConfigData + sizeof (PROC_TRACE_DATA));\r
\r
  ConfigData->NumberOfProcessors    = (UINT32)NumberOfProcessors;\r
  ConfigData->ProcTraceMemSize      = PcdGet32 (PcdCpuProcTraceMemSize);\r
  ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme);\r
\r
  return ConfigData;\r
}\r
\r
/**\r
  Detects if Intel Processor Trace feature supported on current\r
  processor.\r
\r
  @param[in]  ProcessorNumber  The index of the CPU executing this function.\r
  @param[in]  CpuInfo          A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r
                               structure for the CPU executing this function.\r
  @param[in]  ConfigData       A pointer to the configuration buffer returned\r
                               by CPU_FEATURE_GET_CONFIG_DATA.  NULL if\r
                               CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
                               RegisterCpuFeature().\r
\r
  @retval TRUE     Processor Trace feature is supported.\r
  @retval FALSE    Processor Trace feature is not supported.\r
\r
  @note This service could be called by BSP/APs.\r
**/\r
BOOLEAN\r
EFIAPI\r
ProcTraceSupport (\r
  IN UINTN                             ProcessorNumber,\r
  IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,\r
  IN VOID                              *ConfigData  OPTIONAL\r
  )\r
{\r
  PROC_TRACE_DATA                              *ProcTraceData;\r
  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX  Ebx;\r
  CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX    Ecx;\r
\r
  //\r
  // Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)\r
  //\r
  ProcTraceData = (PROC_TRACE_DATA *)ConfigData;\r
  ASSERT (ProcTraceData != NULL);\r
  if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||\r
      (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA))\r
  {\r
    return FALSE;\r
  }\r
\r
  //\r
  // Check if Processor Trace is supported\r
  //\r
  AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, &Ebx.Uint32, NULL, NULL);\r
  if (Ebx.Bits.IntelProcessorTrace == 0) {\r
    return FALSE;\r
  }\r
\r
  AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);\r
  ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported        = (BOOLEAN)(Ecx.Bits.RTIT == 1);\r
  ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN)(Ecx.Bits.SingleRangeOutput == 1);\r
  if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||\r
      (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)))\r
  {\r
    ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64           = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
    ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64     = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);\r
    ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);\r
    return TRUE;\r
  }\r
\r
  return FALSE;\r
}\r
\r
/**\r
  Initializes Intel Processor Trace feature to specific state.\r
\r
  @param[in]  ProcessorNumber  The index of the CPU executing this function.\r
  @param[in]  CpuInfo          A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r
                               structure for the CPU executing this function.\r
  @param[in]  ConfigData       A pointer to the configuration buffer returned\r
                               by CPU_FEATURE_GET_CONFIG_DATA.  NULL if\r
                               CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
                               RegisterCpuFeature().\r
  @param[in]  State            If TRUE, then the Processor Trace feature must be\r
                               enabled.\r
                               If FALSE, then the Processor Trace feature must be\r
                               disabled.\r
\r
  @retval RETURN_SUCCESS       Intel Processor Trace feature is initialized.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
ProcTraceInitialize (\r
  IN UINTN                             ProcessorNumber,\r
  IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,\r
  IN VOID                              *ConfigData   OPTIONAL,\r
  IN BOOLEAN                           State\r
  )\r
{\r
  UINT32                                   MemRegionSize;\r
  UINTN                                    Pages;\r
  UINTN                                    Alignment;\r
  UINTN                                    MemRegionBaseAddr;\r
  UINTN                                    *ThreadMemRegionTable;\r
  UINTN                                    Index;\r
  UINTN                                    TopaTableBaseAddr;\r
  UINTN                                    AlignedAddress;\r
  UINTN                                    *TopaMemArray;\r
  PROC_TRACE_TOPA_TABLE                    *TopaTable;\r
  PROC_TRACE_DATA                          *ProcTraceData;\r
  BOOLEAN                                  FirstIn;\r
  MSR_IA32_RTIT_CTL_REGISTER               CtrlReg;\r
  MSR_IA32_RTIT_STATUS_REGISTER            StatusReg;\r
  MSR_IA32_RTIT_OUTPUT_BASE_REGISTER       OutputBaseReg;\r
  MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER  OutputMaskPtrsReg;\r
  RTIT_TOPA_TABLE_ENTRY                    *TopaEntryPtr;\r
\r
  //\r
  // The scope of the MSR_IA32_RTIT_* is core for below processor type, only program\r
  // MSR_IA32_RTIT_* for thread 0 in each core.\r
  //\r
  if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))\r
  {\r
    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
      return RETURN_SUCCESS;\r
    }\r
  }\r
\r
  ProcTraceData = (PROC_TRACE_DATA *)ConfigData;\r
  ASSERT (ProcTraceData != NULL);\r
\r
  //\r
  // Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CTL[0]==1b\r
  //\r
  CtrlReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64;\r
  if (CtrlReg.Bits.TraceEn != 0) {\r
    ///\r
    /// Clear bit 0 in MSR IA32_RTIT_CTL (570)\r
    ///\r
    CtrlReg.Bits.TraceEn = 0;\r
    CPU_REGISTER_TABLE_WRITE64 (\r
      ProcessorNumber,\r
      Msr,\r
      MSR_IA32_RTIT_CTL,\r
      CtrlReg.Uint64\r
      );\r
\r
    ///\r
    /// Clear MSR IA32_RTIT_STS (571h) to all zeros\r
    ///\r
    StatusReg.Uint64 = 0x0;\r
    CPU_REGISTER_TABLE_WRITE64 (\r
      ProcessorNumber,\r
      Msr,\r
      MSR_IA32_RTIT_STATUS,\r
      StatusReg.Uint64\r
      );\r
  }\r
\r
  if (!State) {\r
    return RETURN_SUCCESS;\r
  }\r
\r
  MemRegionBaseAddr = 0;\r
  FirstIn           = FALSE;\r
\r
  if (ProcTraceData->ThreadMemRegionTable == NULL) {\r
    FirstIn = TRUE;\r
    DEBUG ((DEBUG_INFO, "Initialize Processor Trace\n"));\r
  }\r
\r
  ///\r
  /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding\r
  ///\r
  MemRegionSize = (UINT32)(1 << (ProcTraceData->ProcTraceMemSize + 12));\r
  if (FirstIn) {\r
    DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));\r
  }\r
\r
  if (FirstIn) {\r
    //\r
    //   Let BSP allocate and create the necessary memory region (Aligned to the size of\r
    //   the memory region from setup option(ProcTraceMemSize) which is an integral multiple of 4kB)\r
    //   for all the enabled threads to store Processor Trace debug data. Then Configure the trace\r
    //   address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be\r
    //   aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 cleared.\r
    //\r
    ThreadMemRegionTable = (UINTN *)AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));\r
    if (ThreadMemRegionTable == NULL) {\r
      DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));\r
      return RETURN_OUT_OF_RESOURCES;\r
    }\r
\r
    ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable;\r
\r
    for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) {\r
      Pages          = EFI_SIZE_TO_PAGES (MemRegionSize);\r
      Alignment      = MemRegionSize;\r
      AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);\r
      if (AlignedAddress == 0) {\r
        DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads));\r
        if (Index == 0) {\r
          //\r
          // Could not allocate for BSP even\r
          //\r
          FreePool ((VOID *)ThreadMemRegionTable);\r
          ThreadMemRegionTable = NULL;\r
          return RETURN_OUT_OF_RESOURCES;\r
        }\r
\r
        break;\r
      }\r
\r
      ThreadMemRegionTable[Index] = AlignedAddress;\r
      DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64)ThreadMemRegionTable[Index]));\r
    }\r
\r
    DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads));\r
  }\r
\r
  if (ProcessorNumber < ProcTraceData->AllocatedThreads) {\r
    MemRegionBaseAddr = ProcTraceData->ThreadMemRegionTable[ProcessorNumber];\r
  } else {\r
    return RETURN_SUCCESS;\r
  }\r
\r
  ///\r
  /// Check Processor Trace output scheme: Single Range output or ToPA table\r
  ///\r
\r
  //\r
  //  Single Range output scheme\r
  //\r
  if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&\r
      (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))\r
  {\r
    if (FirstIn) {\r
      DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));\r
    }\r
\r
    //\r
    // Clear MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)\r
    //\r
    CtrlReg.Bits.ToPA = 0;\r
    CPU_REGISTER_TABLE_WRITE64 (\r
      ProcessorNumber,\r
      Msr,\r
      MSR_IA32_RTIT_CTL,\r
      CtrlReg.Uint64\r
      );\r
\r
    //\r
    // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region\r
    //\r
    OutputBaseReg.Uint64      = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;\r
    OutputBaseReg.Bits.Base   = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;\r
    OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;\r
    CPU_REGISTER_TABLE_WRITE64 (\r
      ProcessorNumber,\r
      Msr,\r
      MSR_IA32_RTIT_OUTPUT_BASE,\r
      OutputBaseReg.Uint64\r
      );\r
\r
    //\r
    // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)\r
    //\r
    OutputMaskPtrsReg.Uint64                 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;\r
    OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF;\r
    OutputMaskPtrsReg.Bits.OutputOffset      = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;\r
    CPU_REGISTER_TABLE_WRITE64 (\r
      ProcessorNumber,\r
      Msr,\r
      MSR_IA32_RTIT_OUTPUT_MASK_PTRS,\r
      OutputMaskPtrsReg.Uint64\r
      );\r
  }\r
\r
  //\r
  //  ToPA(Table of physical address) scheme\r
  //\r
  if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&\r
      (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA))\r
  {\r
    //\r
    //  Create ToPA structure aligned at 4KB for each logical thread\r
    //  with at least 2 entries by 8 bytes size each. The first entry\r
    //  should have the trace output base address in bits 47:12, 6:9\r
    //  for Size, bits 4,2 and 0 must be cleared. The second entry\r
    //  should have the base address of the table location in bits\r
    //  47:12, bits 4 and 2 must be cleared and bit 0 must be set.\r
    //\r
    if (FirstIn) {\r
      DEBUG ((DEBUG_INFO, "ProcTrace: Enabling ToPA scheme \n"));\r
      //\r
      // Let BSP allocate ToPA table mem for all threads\r
      //\r
      TopaMemArray = (UINTN *)AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));\r
      if (TopaMemArray == NULL) {\r
        DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"));\r
        return RETURN_OUT_OF_RESOURCES;\r
      }\r
\r
      ProcTraceData->TopaMemArray = TopaMemArray;\r
\r
      for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) {\r
        Pages          = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));\r
        Alignment      = 0x1000;\r
        AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);\r
        if (AlignedAddress == 0) {\r
          if (Index < ProcTraceData->AllocatedThreads) {\r
            ProcTraceData->AllocatedThreads = Index;\r
          }\r
\r
          DEBUG ((DEBUG_ERROR, "ProcTrace:  Out of mem, allocated ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads));\r
          if (Index == 0) {\r
            //\r
            // Could not allocate for BSP even\r
            //\r
            FreePool ((VOID *)TopaMemArray);\r
            TopaMemArray = NULL;\r
            return RETURN_OUT_OF_RESOURCES;\r
          }\r
\r
          break;\r
        }\r
\r
        TopaMemArray[Index] = AlignedAddress;\r
        DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64)TopaMemArray[Index]));\r
      }\r
\r
      DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads));\r
    }\r
\r
    if (ProcessorNumber < ProcTraceData->AllocatedThreads) {\r
      TopaTableBaseAddr = ProcTraceData->TopaMemArray[ProcessorNumber];\r
    } else {\r
      return RETURN_SUCCESS;\r
    }\r
\r
    TopaTable                 = (PROC_TRACE_TOPA_TABLE *)TopaTableBaseAddr;\r
    TopaEntryPtr              = &TopaTable->TopaEntry[0];\r
    TopaEntryPtr->Uint64      = 0;\r
    TopaEntryPtr->Bits.Base   = (MemRegionBaseAddr >> 12) & 0x000FFFFF;\r
    TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;\r
    TopaEntryPtr->Bits.Size   = ProcTraceData->ProcTraceMemSize;\r
    TopaEntryPtr->Bits.END    = 0;\r
\r
    TopaEntryPtr              = &TopaTable->TopaEntry[1];\r
    TopaEntryPtr->Uint64      = 0;\r
    TopaEntryPtr->Bits.Base   = (TopaTableBaseAddr >> 12) & 0x000FFFFF;\r
    TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;\r
    TopaEntryPtr->Bits.END    = 1;\r
\r
    //\r
    // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base\r
    //\r
    OutputBaseReg.Uint64      = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;\r
    OutputBaseReg.Bits.Base   = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;\r
    OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;\r
    CPU_REGISTER_TABLE_WRITE64 (\r
      ProcessorNumber,\r
      Msr,\r
      MSR_IA32_RTIT_OUTPUT_BASE,\r
      OutputBaseReg.Uint64\r
      );\r
\r
    //\r
    // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0\r
    //\r
    OutputMaskPtrsReg.Uint64                 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;\r
    OutputMaskPtrsReg.Bits.MaskOrTableOffset = 0;\r
    OutputMaskPtrsReg.Bits.OutputOffset      = 0;\r
    CPU_REGISTER_TABLE_WRITE64 (\r
      ProcessorNumber,\r
      Msr,\r
      MSR_IA32_RTIT_OUTPUT_MASK_PTRS,\r
      OutputMaskPtrsReg.Uint64\r
      );\r
    //\r
    // Enable ToPA output scheme by enabling MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)\r
    //\r
    CtrlReg.Bits.ToPA = 1;\r
    CPU_REGISTER_TABLE_WRITE64 (\r
      ProcessorNumber,\r
      Msr,\r
      MSR_IA32_RTIT_CTL,\r
      CtrlReg.Uint64\r
      );\r
  }\r
\r
  ///\r
  /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)\r
  ///\r
  CtrlReg.Bits.OS       = 1;\r
  CtrlReg.Bits.User     = 1;\r
  CtrlReg.Bits.BranchEn = 1;\r
  CtrlReg.Bits.TraceEn  = 1;\r
  CPU_REGISTER_TABLE_WRITE64 (\r
    ProcessorNumber,\r
    Msr,\r
    MSR_IA32_RTIT_CTL,\r
    CtrlReg.Uint64\r
    );\r
\r
  return RETURN_SUCCESS;\r
}\r