[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / CpuS3.c

/** @file\r
Code for Processor S3 restoration\r
\r
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "PiSmmCpuDxeSmm.h"\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINTN             Lock;\r
  VOID              *StackStart;\r
  UINTN             StackSize;\r
  VOID              *ApFunction;\r
  IA32_DESCRIPTOR   GdtrProfile;\r
  IA32_DESCRIPTOR   IdtrProfile;\r
  UINT32            BufferStart;\r
  UINT32            Cr3;\r
  UINTN             InitializeFloatingPointUnitsAddress;\r
} MP_CPU_EXCHANGE_INFO;\r
#pragma pack()\r
\r
typedef struct {\r
  UINT8 *RendezvousFunnelAddress;\r
  UINTN PModeEntryOffset;\r
  UINTN FlatJumpOffset;\r
  UINTN Size;\r
  UINTN LModeEntryOffset;\r
  UINTN LongJumpOffset;\r
} MP_ASSEMBLY_ADDRESS_MAP;\r
\r
//\r
// Spin lock used to serialize MemoryMapped operation\r
//\r
SPIN_LOCK                *mMemoryMappedLock = NULL;\r
\r
//\r
// Signal that SMM BASE relocation is complete.\r
//\r
volatile BOOLEAN         mInitApsAfterSmmBaseReloc;\r
\r
/**\r
  Get starting address and size of the rendezvous entry for APs.\r
  Information for fixing a jump instruction in the code is also returned.\r
\r
  @param AddressMap  Output buffer for address map information.\r
**/\r
VOID *\r
EFIAPI\r
AsmGetAddressMap (\r
  MP_ASSEMBLY_ADDRESS_MAP                     *AddressMap\r
  );\r
\r
#define LEGACY_REGION_SIZE    (2 * 0x1000)\r
#define LEGACY_REGION_BASE    (0xA0000 - LEGACY_REGION_SIZE)\r
\r
ACPI_CPU_DATA                mAcpiCpuData;\r
volatile UINT32              mNumberToFinish;\r
MP_CPU_EXCHANGE_INFO         *mExchangeInfo;\r
BOOLEAN                      mRestoreSmmConfigurationInS3 = FALSE;\r
MP_MSR_LOCK                  *mMsrSpinLocks = NULL;\r
UINTN                        mMsrSpinLockCount;\r
UINTN                        mMsrCount = 0;\r
\r
//\r
// S3 boot flag\r
//\r
BOOLEAN                      mSmmS3Flag = FALSE;\r
\r
//\r
// Pointer to structure used during S3 Resume\r
//\r
SMM_S3_RESUME_STATE          *mSmmS3ResumeState = NULL;\r
\r
BOOLEAN                      mAcpiS3Enable = TRUE;\r
\r
UINT8                        *mApHltLoopCode = NULL;\r
UINT8                        mApHltLoopCodeTemplate[] = {\r
                               0x8B, 0x44, 0x24, 0x04,  // mov  eax, dword ptr [esp+4]\r
                               0xF0, 0xFF, 0x08,        // lock dec  dword ptr [eax]\r
                               0xFA,                    // cli\r
                               0xF4,                    // hlt\r
                               0xEB, 0xFC               // jmp $-2\r
                               };\r
\r
/**\r
  Get MSR spin lock by MSR index.\r
\r
  @param  MsrIndex       MSR index value.\r
\r
  @return Pointer to MSR spin lock.\r
\r
**/\r
SPIN_LOCK *\r
GetMsrSpinLockByIndex (\r
  IN UINT32      MsrIndex\r
  )\r
{\r
  UINTN     Index;\r
  for (Index = 0; Index < mMsrCount; Index++) {\r
    if (MsrIndex == mMsrSpinLocks[Index].MsrIndex) {\r
      return mMsrSpinLocks[Index].SpinLock;\r
    }\r
  }\r
  return NULL;\r
}\r
\r
/**\r
  Initialize MSR spin lock by MSR index.\r
\r
  @param  MsrIndex       MSR index value.\r
\r
**/\r
VOID\r
InitMsrSpinLockByIndex (\r
  IN UINT32      MsrIndex\r
  )\r
{\r
  UINTN    MsrSpinLockCount;\r
  UINTN    NewMsrSpinLockCount;\r
  UINTN    Index;\r
  UINTN    AddedSize;\r
\r
  if (mMsrSpinLocks == NULL) {\r
    MsrSpinLockCount = mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter;\r
    mMsrSpinLocks = (MP_MSR_LOCK *) AllocatePool (sizeof (MP_MSR_LOCK) * MsrSpinLockCount);\r
    ASSERT (mMsrSpinLocks != NULL);\r
    for (Index = 0; Index < MsrSpinLockCount; Index++) {\r
      mMsrSpinLocks[Index].SpinLock =\r
       (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreMsr.Msr + Index * mSemaphoreSize);\r
      mMsrSpinLocks[Index].MsrIndex = (UINT32)-1;\r
    }\r
    mMsrSpinLockCount = MsrSpinLockCount;\r
    mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter = 0;\r
  }\r
  if (GetMsrSpinLockByIndex (MsrIndex) == NULL) {\r
    //\r
    // Initialize spin lock for MSR programming\r
    //\r
    mMsrSpinLocks[mMsrCount].MsrIndex = MsrIndex;\r
    InitializeSpinLock (mMsrSpinLocks[mMsrCount].SpinLock);\r
    mMsrCount ++;\r
    if (mMsrCount == mMsrSpinLockCount) {\r
      //\r
      // If MSR spin lock buffer is full, enlarge it\r
      //\r
      AddedSize = SIZE_4KB;\r
      mSmmCpuSemaphores.SemaphoreMsr.Msr =\r
                        AllocatePages (EFI_SIZE_TO_PAGES(AddedSize));\r
      ASSERT (mSmmCpuSemaphores.SemaphoreMsr.Msr != NULL);\r
      NewMsrSpinLockCount = mMsrSpinLockCount + AddedSize / mSemaphoreSize;\r
      mMsrSpinLocks = ReallocatePool (\r
                        sizeof (MP_MSR_LOCK) * mMsrSpinLockCount,\r
                        sizeof (MP_MSR_LOCK) * NewMsrSpinLockCount,\r
                        mMsrSpinLocks\r
                        );\r
      ASSERT (mMsrSpinLocks != NULL);\r
      mMsrSpinLockCount = NewMsrSpinLockCount;\r
      for (Index = mMsrCount; Index < mMsrSpinLockCount; Index++) {\r
        mMsrSpinLocks[Index].SpinLock =\r
                 (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreMsr.Msr +\r
                 (Index - mMsrCount)  * mSemaphoreSize);\r
        mMsrSpinLocks[Index].MsrIndex = (UINT32)-1;\r
      }\r
    }\r
  }\r
}\r
\r
/**\r
  Sync up the MTRR values for all processors.\r
\r
  @param MtrrTable  Table holding fixed/variable MTRR values to be loaded.\r
**/\r
VOID\r
EFIAPI\r
LoadMtrrData (\r
  EFI_PHYSICAL_ADDRESS       MtrrTable\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Sync up the MTRR values for all processors.\r
\r
Arguments:\r
\r
Returns:\r
    None\r
\r
--*/\r
{\r
  MTRR_SETTINGS   *MtrrSettings;\r
\r
  MtrrSettings = (MTRR_SETTINGS *) (UINTN) MtrrTable;\r
  MtrrSetAllMtrrs (MtrrSettings);\r
}\r
\r
/**\r
  Programs registers for the calling processor.\r
\r
  This function programs registers for the calling processor.\r
\r
  @param  RegisterTables        Pointer to register table of the running processor.\r
  @param  RegisterTableCount    Register table count.\r
\r
**/\r
VOID\r
SetProcessorRegister (\r
  IN CPU_REGISTER_TABLE        *RegisterTables,\r
  IN UINTN                     RegisterTableCount\r
  )\r
{\r
  CPU_REGISTER_TABLE_ENTRY  *RegisterTableEntry;\r
  UINTN                     Index;\r
  UINTN                     Value;\r
  SPIN_LOCK                 *MsrSpinLock;\r
  UINT32                    InitApicId;\r
  CPU_REGISTER_TABLE        *RegisterTable;\r
\r
  InitApicId = GetInitialApicId ();\r
  RegisterTable = NULL;\r
  for (Index = 0; Index < RegisterTableCount; Index++) {\r
    if (RegisterTables[Index].InitialApicId == InitApicId) {\r
      RegisterTable =  &RegisterTables[Index];\r
      break;\r
    }\r
  }\r
  ASSERT (RegisterTable != NULL);\r
\r
  //\r
  // Traverse Register Table of this logical processor\r
  //\r
  RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;\r
  for (Index = 0; Index < RegisterTable->TableLength; Index++, RegisterTableEntry++) {\r
    //\r
    // Check the type of specified register\r
    //\r
    switch (RegisterTableEntry->RegisterType) {\r
    //\r
    // The specified register is Control Register\r
    //\r
    case ControlRegister:\r
      switch (RegisterTableEntry->Index) {\r
      case 0:\r
        Value = AsmReadCr0 ();\r
        Value = (UINTN) BitFieldWrite64 (\r
                          Value,\r
                          RegisterTableEntry->ValidBitStart,\r
                          RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
                          (UINTN) RegisterTableEntry->Value\r
                          );\r
        AsmWriteCr0 (Value);\r
        break;\r
      case 2:\r
        Value = AsmReadCr2 ();\r
        Value = (UINTN) BitFieldWrite64 (\r
                          Value,\r
                          RegisterTableEntry->ValidBitStart,\r
                          RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
                          (UINTN) RegisterTableEntry->Value\r
                          );\r
        AsmWriteCr2 (Value);\r
        break;\r
      case 3:\r
        Value = AsmReadCr3 ();\r
        Value = (UINTN) BitFieldWrite64 (\r
                          Value,\r
                          RegisterTableEntry->ValidBitStart,\r
                          RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
                          (UINTN) RegisterTableEntry->Value\r
                          );\r
        AsmWriteCr3 (Value);\r
        break;\r
      case 4:\r
        Value = AsmReadCr4 ();\r
        Value = (UINTN) BitFieldWrite64 (\r
                          Value,\r
                          RegisterTableEntry->ValidBitStart,\r
                          RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
                          (UINTN) RegisterTableEntry->Value\r
                          );\r
        AsmWriteCr4 (Value);\r
        break;\r
      default:\r
        break;\r
      }\r
      break;\r
    //\r
    // The specified register is Model Specific Register\r
    //\r
    case Msr:\r
      //\r
      // If this function is called to restore register setting after INIT signal,\r
      // there is no need to restore MSRs in register table.\r
      //\r
      if (RegisterTableEntry->ValidBitLength >= 64) {\r
        //\r
        // If length is not less than 64 bits, then directly write without reading\r
        //\r
        AsmWriteMsr64 (\r
          RegisterTableEntry->Index,\r
          RegisterTableEntry->Value\r
          );\r
      } else {\r
        //\r
        // Get lock to avoid Package/Core scope MSRs programming issue in parallel execution mode\r
        // to make sure MSR read/write operation is atomic.\r
        //\r
        MsrSpinLock = GetMsrSpinLockByIndex (RegisterTableEntry->Index);\r
        AcquireSpinLock (MsrSpinLock);\r
        //\r
        // Set the bit section according to bit start and length\r
        //\r
        AsmMsrBitFieldWrite64 (\r
          RegisterTableEntry->Index,\r
          RegisterTableEntry->ValidBitStart,\r
          RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
          RegisterTableEntry->Value\r
          );\r
        ReleaseSpinLock (MsrSpinLock);\r
      }\r
      break;\r
    //\r
    // MemoryMapped operations\r
    //\r
    case MemoryMapped:\r
      AcquireSpinLock (mMemoryMappedLock);\r
      MmioBitFieldWrite32 (\r
        (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),\r
        RegisterTableEntry->ValidBitStart,\r
        RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
        (UINT32)RegisterTableEntry->Value\r
        );\r
      ReleaseSpinLock (mMemoryMappedLock);\r
      break;\r
    //\r
    // Enable or disable cache\r
    //\r
    case CacheControl:\r
      //\r
      // If value of the entry is 0, then disable cache.  Otherwise, enable cache.\r
      //\r
      if (RegisterTableEntry->Value == 0) {\r
        AsmDisableCache ();\r
      } else {\r
        AsmEnableCache ();\r
      }\r
      break;\r
\r
    default:\r
      break;\r
    }\r
  }\r
}\r
\r
/**\r
  AP initialization before then after SMBASE relocation in the S3 boot path.\r
**/\r
VOID\r
InitializeAp (\r
  VOID\r
  )\r
{\r
  UINTN                      TopOfStack;\r
  UINT8                      Stack[128];\r
\r
  LoadMtrrData (mAcpiCpuData.MtrrTable);\r
\r
  SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable, mAcpiCpuData.NumberOfCpus);\r
\r
  //\r
  // Count down the number with lock mechanism.\r
  //\r
  InterlockedDecrement (&mNumberToFinish);\r
\r
  //\r
  // Wait for BSP to signal SMM Base relocation done.\r
  //\r
  while (!mInitApsAfterSmmBaseReloc) {\r
    CpuPause ();\r
  }\r
\r
  ProgramVirtualWireMode ();\r
  DisableLvtInterrupts ();\r
\r
  SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable, mAcpiCpuData.NumberOfCpus);\r
\r
  //\r
  // Place AP into the safe code, count down the number with lock mechanism in the safe code.\r
  //\r
  TopOfStack  = (UINTN) Stack + sizeof (Stack);\r
  TopOfStack &= ~(UINTN) (CPU_STACK_ALIGNMENT - 1);\r
  CopyMem ((VOID *) (UINTN) mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate));\r
  TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumberToFinish);\r
}\r
\r
/**\r
  Prepares startup vector for APs.\r
\r
  This function prepares startup vector for APs.\r
\r
  @param  WorkingBuffer  The address of the work buffer.\r
**/\r
VOID\r
PrepareApStartupVector (\r
  EFI_PHYSICAL_ADDRESS  WorkingBuffer\r
  )\r
{\r
  EFI_PHYSICAL_ADDRESS                        StartupVector;\r
  MP_ASSEMBLY_ADDRESS_MAP                     AddressMap;\r
\r
  //\r
  // Get the address map of startup code for AP,\r
  // including code size, and offset of long jump instructions to redirect.\r
  //\r
  ZeroMem (&AddressMap, sizeof (AddressMap));\r
  AsmGetAddressMap (&AddressMap);\r
\r
  StartupVector = WorkingBuffer;\r
\r
  //\r
  // Copy AP startup code to startup vector, and then redirect the long jump\r
  // instructions for mode switching.\r
  //\r
  CopyMem ((VOID *) (UINTN) StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size);\r
  *(UINT32 *) (UINTN) (StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32) (StartupVector + AddressMap.PModeEntryOffset);\r
  if (AddressMap.LongJumpOffset != 0) {\r
    *(UINT32 *) (UINTN) (StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32) (StartupVector + AddressMap.LModeEntryOffset);\r
  }\r
\r
  //\r
  // Get the start address of exchange data between BSP and AP.\r
  //\r
  mExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) (StartupVector + AddressMap.Size);\r
  ZeroMem ((VOID *) mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));\r
\r
  CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN) mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));\r
  CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN) mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));\r
\r
  mExchangeInfo->StackStart  = (VOID *) (UINTN) mAcpiCpuData.StackAddress;\r
  mExchangeInfo->StackSize   = mAcpiCpuData.StackSize;\r
  mExchangeInfo->BufferStart = (UINT32) StartupVector;\r
  mExchangeInfo->Cr3         = (UINT32) (AsmReadCr3 ());\r
  mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;\r
}\r
\r
/**\r
  The function is invoked before SMBASE relocation in S3 path to restores CPU status.\r
\r
  The function is invoked before SMBASE relocation in S3 path. It does first time microcode load\r
  and restores MTRRs for both BSP and APs.\r
\r
**/\r
VOID\r
InitializeCpuBeforeRebase (\r
  VOID\r
  )\r
{\r
  LoadMtrrData (mAcpiCpuData.MtrrTable);\r
\r
  SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable, mAcpiCpuData.NumberOfCpus);\r
\r
  ProgramVirtualWireMode ();\r
\r
  PrepareApStartupVector (mAcpiCpuData.StartupVector);\r
\r
  mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;\r
  mExchangeInfo->ApFunction  = (VOID *) (UINTN) InitializeAp;\r
\r
  //\r
  // Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots.\r
  //\r
  mInitApsAfterSmmBaseReloc = FALSE;\r
\r
  //\r
  // Send INIT IPI - SIPI to all APs\r
  //\r
  SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector);\r
\r
  while (mNumberToFinish > 0) {\r
    CpuPause ();\r
  }\r
}\r
\r
/**\r
  The function is invoked after SMBASE relocation in S3 path to restores CPU status.\r
\r
  The function is invoked after SMBASE relocation in S3 path. It restores configuration according to\r
  data saved by normal boot path for both BSP and APs.\r
\r
**/\r
VOID\r
InitializeCpuAfterRebase (\r
  VOID\r
  )\r
{\r
  SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable, mAcpiCpuData.NumberOfCpus);\r
\r
  mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;\r
\r
  //\r
  // Signal that SMM base relocation is complete and to continue initialization.\r
  //\r
  mInitApsAfterSmmBaseReloc = TRUE;\r
\r
  while (mNumberToFinish > 0) {\r
    CpuPause ();\r
  }\r
}\r
\r
/**\r
  Restore SMM Configuration in S3 boot path.\r
\r
**/\r
VOID\r
RestoreSmmConfigurationInS3 (\r
  VOID\r
  )\r
{\r
  if (!mAcpiS3Enable) {\r
    return;\r
  }\r
\r
  //\r
  // Restore SMM Configuration in S3 boot path.\r
  //\r
  if (mRestoreSmmConfigurationInS3) {\r
    //\r
    // Need make sure gSmst is correct because below function may use them.\r
    //\r
    gSmst->SmmStartupThisAp      = gSmmCpuPrivate->SmmCoreEntryContext.SmmStartupThisAp;\r
    gSmst->CurrentlyExecutingCpu = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;\r
    gSmst->NumberOfCpus          = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r
    gSmst->CpuSaveStateSize      = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveStateSize;\r
    gSmst->CpuSaveState          = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveState;\r
\r
    //\r
    // Configure SMM Code Access Check feature if available.\r
    //\r
    ConfigSmmCodeAccessCheck ();\r
\r
    SmmCpuFeaturesCompleteSmmReadyToLock ();\r
\r
    mRestoreSmmConfigurationInS3 = FALSE;\r
  }\r
}\r
\r
/**\r
  Perform SMM initialization for all processors in the S3 boot path.\r
\r
  For a native platform, MP initialization in the S3 boot path is also performed in this function.\r
**/\r
VOID\r
EFIAPI\r
SmmRestoreCpu (\r
  VOID\r
  )\r
{\r
  SMM_S3_RESUME_STATE           *SmmS3ResumeState;\r
  IA32_DESCRIPTOR               Ia32Idtr;\r
  IA32_DESCRIPTOR               X64Idtr;\r
  IA32_IDT_GATE_DESCRIPTOR      IdtEntryTable[EXCEPTION_VECTOR_NUMBER];\r
  EFI_STATUS                    Status;\r
\r
  DEBUG ((EFI_D_INFO, "SmmRestoreCpu()\n"));\r
\r
  mSmmS3Flag = TRUE;\r
\r
  InitializeSpinLock (mMemoryMappedLock);\r
\r
  //\r
  // See if there is enough context to resume PEI Phase\r
  //\r
  if (mSmmS3ResumeState == NULL) {\r
    DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));\r
    CpuDeadLoop ();\r
  }\r
\r
  SmmS3ResumeState = mSmmS3ResumeState;\r
  ASSERT (SmmS3ResumeState != NULL);\r
\r
  if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {\r
    //\r
    // Save the IA32 IDT Descriptor\r
    //\r
    AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);\r
\r
    //\r
    // Setup X64 IDT table\r
    //\r
    ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);\r
    X64Idtr.Base = (UINTN) IdtEntryTable;\r
    X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);\r
    AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);\r
\r
    //\r
    // Setup the default exception handler\r
    //\r
    Status = InitializeCpuExceptionHandlers (NULL);\r
    ASSERT_EFI_ERROR (Status);\r
\r
    //\r
    // Initialize Debug Agent to support source level debug\r
    //\r
    InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *)&Ia32Idtr, NULL);\r
  }\r
\r
  //\r
  // Skip initialization if mAcpiCpuData is not valid\r
  //\r
  if (mAcpiCpuData.NumberOfCpus > 0) {\r
    //\r
    // First time microcode load and restore MTRRs\r
    //\r
    InitializeCpuBeforeRebase ();\r
  }\r
\r
  //\r
  // Restore SMBASE for BSP and all APs\r
  //\r
  SmmRelocateBases ();\r
\r
  //\r
  // Skip initialization if mAcpiCpuData is not valid\r
  //\r
  if (mAcpiCpuData.NumberOfCpus > 0) {\r
    //\r
    // Restore MSRs for BSP and all APs\r
    //\r
    InitializeCpuAfterRebase ();\r
  }\r
\r
  //\r
  // Set a flag to restore SMM configuration in S3 path.\r
  //\r
  mRestoreSmmConfigurationInS3 = TRUE;\r
\r
  DEBUG (( EFI_D_INFO, "SMM S3 Return CS                = %x\n", SmmS3ResumeState->ReturnCs));\r
  DEBUG (( EFI_D_INFO, "SMM S3 Return Entry Point       = %x\n", SmmS3ResumeState->ReturnEntryPoint));\r
  DEBUG (( EFI_D_INFO, "SMM S3 Return Context1          = %x\n", SmmS3ResumeState->ReturnContext1));\r
  DEBUG (( EFI_D_INFO, "SMM S3 Return Context2          = %x\n", SmmS3ResumeState->ReturnContext2));\r
  DEBUG (( EFI_D_INFO, "SMM S3 Return Stack Pointer     = %x\n", SmmS3ResumeState->ReturnStackPointer));\r
\r
  //\r
  // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase\r
  //\r
  if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {\r
    DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));\r
\r
    SwitchStack (\r
      (SWITCH_STACK_ENTRY_POINT)(UINTN)SmmS3ResumeState->ReturnEntryPoint,\r
      (VOID *)(UINTN)SmmS3ResumeState->ReturnContext1,\r
      (VOID *)(UINTN)SmmS3ResumeState->ReturnContext2,\r
      (VOID *)(UINTN)SmmS3ResumeState->ReturnStackPointer\r
      );\r
  }\r
\r
  //\r
  // If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase\r
  //\r
  if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {\r
    DEBUG ((EFI_D_INFO, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));\r
    //\r
    // Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.\r
    //\r
    SaveAndSetDebugTimerInterrupt (FALSE);\r
    //\r
    // Restore IA32 IDT table\r
    //\r
    AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);\r
    AsmDisablePaging64 (\r
      SmmS3ResumeState->ReturnCs,\r
      (UINT32)SmmS3ResumeState->ReturnEntryPoint,\r
      (UINT32)SmmS3ResumeState->ReturnContext1,\r
      (UINT32)SmmS3ResumeState->ReturnContext2,\r
      (UINT32)SmmS3ResumeState->ReturnStackPointer\r
      );\r
  }\r
\r
  //\r
  // Can not resume PEI Phase\r
  //\r
  DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));\r
  CpuDeadLoop ();\r
}\r
\r
/**\r
  Initialize SMM S3 resume state structure used during S3 Resume.\r
\r
  @param[in] Cr3    The base address of the page tables to use in SMM.\r
\r
**/\r
VOID\r
InitSmmS3ResumeState (\r
  IN UINT32  Cr3\r
  )\r
{\r
  VOID                       *GuidHob;\r
  EFI_SMRAM_DESCRIPTOR       *SmramDescriptor;\r
  SMM_S3_RESUME_STATE        *SmmS3ResumeState;\r
  EFI_PHYSICAL_ADDRESS       Address;\r
  EFI_STATUS                 Status;\r
\r
  if (!mAcpiS3Enable) {\r
    return;\r
  }\r
\r
  GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid);\r
  if (GuidHob != NULL) {\r
    SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);\r
\r
    DEBUG ((EFI_D_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));\r
    DEBUG ((EFI_D_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));\r
\r
    SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;\r
    ZeroMem (SmmS3ResumeState, sizeof (SMM_S3_RESUME_STATE));\r
\r
    mSmmS3ResumeState = SmmS3ResumeState;\r
    SmmS3ResumeState->Smst = (EFI_PHYSICAL_ADDRESS)(UINTN)gSmst;\r
\r
    SmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmRestoreCpu;\r
\r
    SmmS3ResumeState->SmmS3StackSize = SIZE_32KB;\r
    SmmS3ResumeState->SmmS3StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)SmmS3ResumeState->SmmS3StackSize));\r
    if (SmmS3ResumeState->SmmS3StackBase == 0) {\r
      SmmS3ResumeState->SmmS3StackSize = 0;\r
    }\r
\r
    SmmS3ResumeState->SmmS3Cr0 = mSmmCr0;\r
    SmmS3ResumeState->SmmS3Cr3 = Cr3;\r
    SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;\r
\r
    if (sizeof (UINTN) == sizeof (UINT64)) {\r
      SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;\r
    }\r
    if (sizeof (UINTN) == sizeof (UINT32)) {\r
      SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;\r
    }\r
  }\r
\r
  //\r
  // Patch SmmS3ResumeState->SmmS3Cr3\r
  //\r
  InitSmmS3Cr3 ();\r
\r
  //\r
  // Allocate safe memory in ACPI NVS for AP to execute hlt loop in\r
  // protected mode on S3 path\r
  //\r
  Address = BASE_4GB - 1;\r
  Status  = gBS->AllocatePages (\r
                   AllocateMaxAddress,\r
                   EfiACPIMemoryNVS,\r
                   EFI_SIZE_TO_PAGES (sizeof (mApHltLoopCodeTemplate)),\r
                   &Address\r
                   );\r
  ASSERT_EFI_ERROR (Status);\r
  mApHltLoopCode = (UINT8 *) (UINTN) Address;\r
}\r
\r
/**\r
  Copy register table from ACPI NVS memory into SMRAM.\r
\r
  @param[in] DestinationRegisterTableList  Points to destination register table.\r
  @param[in] SourceRegisterTableList       Points to source register table.\r
  @param[in] NumberOfCpus                  Number of CPUs.\r
\r
**/\r
VOID\r
CopyRegisterTable (\r
  IN CPU_REGISTER_TABLE         *DestinationRegisterTableList,\r
  IN CPU_REGISTER_TABLE         *SourceRegisterTableList,\r
  IN UINT32                     NumberOfCpus\r
  )\r
{\r
  UINTN                      Index;\r
  UINTN                      Index1;\r
  CPU_REGISTER_TABLE_ENTRY   *RegisterTableEntry;\r
\r
  CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));\r
  for (Index = 0; Index < NumberOfCpus; Index++) {\r
    if (DestinationRegisterTableList[Index].AllocatedSize != 0) {\r
      RegisterTableEntry = AllocateCopyPool (\r
        DestinationRegisterTableList[Index].AllocatedSize,\r
        (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry\r
        );\r
      ASSERT (RegisterTableEntry != NULL);\r
      DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;\r
      //\r
      // Go though all MSRs in register table to initialize MSR spin lock\r
      //\r
      for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {\r
        if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {\r
          //\r
          // Initialize MSR spin lock only for those MSRs need bit field writing\r
          //\r
          InitMsrSpinLockByIndex (RegisterTableEntry->Index);\r
        }\r
      }\r
    }\r
  }\r
}\r
\r
/**\r
  Get ACPI CPU data.\r
\r
**/\r
VOID\r
GetAcpiCpuData (\r
  VOID\r
  )\r
{\r
  ACPI_CPU_DATA              *AcpiCpuData;\r
  IA32_DESCRIPTOR            *Gdtr;\r
  IA32_DESCRIPTOR            *Idtr;\r
  VOID                       *GdtForAp;\r
  VOID                       *IdtForAp;\r
  VOID                       *MachineCheckHandlerForAp;\r
\r
  if (!mAcpiS3Enable) {\r
    return;\r
  }\r
\r
  //\r
  // Prevent use of mAcpiCpuData by initialize NumberOfCpus to 0\r
  //\r
  mAcpiCpuData.NumberOfCpus = 0;\r
\r
  //\r
  // If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM\r
  //\r
  AcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);\r
  if (AcpiCpuData == 0) {\r
    return;\r
  }\r
\r
  //\r
  // For a native platform, copy the CPU S3 data into SMRAM for use on CPU S3 Resume.\r
  //\r
  CopyMem (&mAcpiCpuData, AcpiCpuData, sizeof (mAcpiCpuData));\r
\r
  mAcpiCpuData.MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (MTRR_SETTINGS));\r
  ASSERT (mAcpiCpuData.MtrrTable != 0);\r
\r
  CopyMem ((VOID *)(UINTN)mAcpiCpuData.MtrrTable, (VOID *)(UINTN)AcpiCpuData->MtrrTable, sizeof (MTRR_SETTINGS));\r
\r
  mAcpiCpuData.GdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));\r
  ASSERT (mAcpiCpuData.GdtrProfile != 0);\r
\r
  CopyMem ((VOID *)(UINTN)mAcpiCpuData.GdtrProfile, (VOID *)(UINTN)AcpiCpuData->GdtrProfile, sizeof (IA32_DESCRIPTOR));\r
\r
  mAcpiCpuData.IdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));\r
  ASSERT (mAcpiCpuData.IdtrProfile != 0);\r
\r
  CopyMem ((VOID *)(UINTN)mAcpiCpuData.IdtrProfile, (VOID *)(UINTN)AcpiCpuData->IdtrProfile, sizeof (IA32_DESCRIPTOR));\r
\r
  mAcpiCpuData.PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));\r
  ASSERT (mAcpiCpuData.PreSmmInitRegisterTable != 0);\r
\r
  CopyRegisterTable (\r
    (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.PreSmmInitRegisterTable,\r
    (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->PreSmmInitRegisterTable,\r
    mAcpiCpuData.NumberOfCpus\r
    );\r
\r
  mAcpiCpuData.RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));\r
  ASSERT (mAcpiCpuData.RegisterTable != 0);\r
\r
  CopyRegisterTable (\r
    (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.RegisterTable,\r
    (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->RegisterTable,\r
    mAcpiCpuData.NumberOfCpus\r
    );\r
\r
  //\r
  // Copy AP's GDT, IDT and Machine Check handler into SMRAM.\r
  //\r
  Gdtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.GdtrProfile;\r
  Idtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.IdtrProfile;\r
\r
  GdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) +  mAcpiCpuData.ApMachineCheckHandlerSize);\r
  ASSERT (GdtForAp != NULL);\r
  IdtForAp = (VOID *) ((UINTN)GdtForAp + (Gdtr->Limit + 1));\r
  MachineCheckHandlerForAp = (VOID *) ((UINTN)IdtForAp + (Idtr->Limit + 1));\r
\r
  CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);\r
  CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);\r
  CopyMem (MachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize);\r
\r
  Gdtr->Base = (UINTN)GdtForAp;\r
  Idtr->Base = (UINTN)IdtForAp;\r
  mAcpiCpuData.ApMachineCheckHandlerBase = (EFI_PHYSICAL_ADDRESS)(UINTN)MachineCheckHandlerForAp;\r
}\r
\r
/**\r
  Get ACPI S3 enable flag.\r
\r
**/\r
VOID\r
GetAcpiS3EnableFlag (\r
  VOID\r
  )\r
{\r
  mAcpiS3Enable = PcdGetBool (PcdAcpiS3Enable);\r
}\r